Course Introduction. Purpose: The intent of this module is to provide an overview of the Freescale clock product categories and clock devices.

Transcription

1 Course Introduction Purpose: The intent of this module is to provide an overview of the Freescale clock product categories and clock devices Objectives: Identify the Freescale clock product categories Describe the PowerQUICC III clocking requirements Identify the Freescale QUICC Clocks Describe clock characteristics Identify signal integrity issues Content: 27 pages 4 questions Learning Time: 40 minutes The intent of this course, Timing Solutions Products, is to provide you with an overview of the Freescale clock product categories and identify the types of clock devices you can use to satisfy PowerQUICC III (PQIII) clocking requirements You will also examine clock characteristics and signal integrity issues that are fundamental to understanding PowerQUICC, PowerPC, and other microprocessor types of environments

2 Clock Driver Product Types Mouse over the clock products to learn more Clock Buffer Q0 Q0 QN QN Q0 Q1 QN Clock Copies(1:N) Levels and Translation Min skew, Min Delay Clock Generator Synthesizer PLL xtal osc M N P PLL N M Divider Program Q0 Q1 QN Number of outputs and frequencies Synchronization of master clock(s) Freq ratios, freq and skew PLL design with internal or ext FB Synthesize high frequency clocks Frequency/resolution Digitally programmable PLL Pre, post and feedback divider Zero-delay Buffer PLL Q0 Q1 QN Clock Copies(1:N) Virtually zero insertion delay Skew and SPO (ZDB Delay) PLL with external feedback IDCS Clock Backup Clock Flags Control 0 1 Monitor and switch logic Optimized PLL Smooth clock transition Low Jitter Zero Delay with ext feedback There are five Freescale clock product categories The first category is the clock buffer The clock buffer consists of both differential output and single-ended output buffers Single-ended output buffers may have either single-ended or differential inputs Single-ended output clock buffers are LVCMOS while differential output buffers may be LVPECL, HSTL or Low Voltage Differential Signaling (LVDS) Clock buffers provide multiple copies of an input clock for individual clock distribution across a PC board The frequency coming out of the buffer is typically the same as the frequency going in Some buffers have an optional divide by two on one or more outputs Clock buffers are designed to have a low but consistent propagation delay and a low output skew The other four Freescale clock categories are Phase Locked Loop (PLL)-based These devices multiply the input clock up to a higher VCO frequency, and then divide the VCO frequency down to the output frequency or frequencies required by the PowerPC or PowerQUICC clocking environment Clock generators require an input clock which is typically in the range of 16 MHz to 25 MHz This input, or reference frequency, is multiplied up in frequency with the PLL clock and then divided down to produce multiple clock outputs and perhaps at multiple frequencies The output frequency is usually an increment of the input frequency Therefore, the clock generator might use a reference of 25 MHz and be configured to produce an output of 100 MHz Other clock generator configurations might produce output frequencies of 125 MHz or 150 MHz Clock generators usually have multiple outputs and those outputs may be divided into multiple banks, allowing each bank to have a different output frequency The synthesizer category is similar to the clock generator category except that the input frequency is much lower Quite often, the input frequency is derived by using a higher frequency crystal, such as 16 MHz, dividing it by the P counter as shown in the block diagram The P counter value might be as high as 16, producing a 1 MHz input or reference frequency to the PLL With the 1 MHz reference frequency, the PLL multiplies the reference to a higher VCO frequency and with output divider stages produces the desired output The advantage of synthesizers is that you can get any frequency you want on the output Whatever output frequency you need 198, 199, 200, or 201 MHz it can be achieved Synthesizers typically only have one or two outputs In many cases, the output is a LVPECL differential output To generate multiple outputs, you would follow the synthesizer with a multiple output buffer The zero-delay buffer category is a PLL version of the clock buffer The zero-delay buffer uses a PLL to compensate for the delay path through the device As its name implies, this buffer essentially has a propagation delay of zero, whereas the clock buffer has a propagation delay between the input and the output Zero delay buffers also have an external feedback path, and by adjusting the physical length of the feedback PC board trace, you can align the clock output with the input at any point on the PC board The output frequency of a zero-delay buffer is usually the same as the input frequency The zero-delay buffer also has multiple outputs to provide multiple copies of the input signal for distribution across the PC board The last clock product category is the Intelligent Dynamic Clock Switch (IDCS) These types of clocks are also known as redundant or failover clocks IDCS clock generators have multiple inputs of the same frequency, but these inputs are not necessarily phase-related clock references A typical application for a redundant or failover clock generator might be the backplane distribution of clocks Perhaps two independent copies of a 625 MHz reference frequency are to be delivered as two independent signals on a backplane If one of these should fail, due to a broken wire, failed oscillator, or an accidentally pulled card, the redundant clock generator will detect this condition and automatically switch over to the backup clock The IDCS device will switch to the backup clock and continue to produce an output clock that has no phase hit, runt pulses, or lack of a clock for a time period on the output Move your mouse pointer over each Freescale clock product category for more information

3 SYSCLK is a single-frequency LVCMOS input Its specifications are outlined in the MPC8560 PowerQUICC III Integrated Communications Processor Reference Manual and the MPC8560 Integrated Processor Hardware Specifications PQIII Clock Requirements Clock Subsystem cfg_core_pll[0:1] e500 Core Core PLL core_clk cfg_sys_pll[0:3] SYSCLK/ PCI_CLK CCB_clk Device PLL DLL DLL MSYNC_IN MSYNC_OUT MCK[0:5] MCK[0:5] LSYNC_IN LSYNC_OUT LCK0 LCK1 CCB_clk to rest of the platform Now, let s examine the PowerQUICC III clock requirements This clock input diagram is from the user's manual for the PowerQUICC III MPC8560 The processor requires a single LVCMOS clock labeled SYSCLK or PCI_CLK This clock input can be at any one of several user-determined frequencies ranging from 16 MHz to 166 MHz Typical values are 33, 66, 100, or 133 MHz This value is user selected and is based upon the overall system design This clock becomes the input to the first of two internal PLLs that are contained within the PowerQUICC III The first internal PLL multiplies the SYSCLK input frequency up in frequency to a platform clock referred to here as CCB_clk The CCB_clk is used for the memory clocks and other aspects of the PowerQUICC III Memory clocking for the PowerQUICC III is provided by two DLL blocks as shown on the right Memory for the PowerQUICC III consists of two types: main memory and local memory The main memory DLL provides differential clocks for DDR1 memory The package pins labeled MCK[0:5] provide six differential clock outputs for clocking DDR1 memory The package pin MSYNC_OUT output signal and the MSYNC_IN input signal allows the system designer the ability to skew the edge alignment of the memory clock This is achieved by routing the MSYNC_OUT across the PC board for the required trace delay length and then returning this signal back into the MSYNC_IN pin Similar functionality is provided with the DLL for the local memory clock Local memory is set for SDRAM with two clock output signals available Similar pins of LSYNC_OUT and LSYNC_IN also allows the edge alignment of the local memory clock to be adjusted via the PC board trace delay path The CCB_clk also becomes the input to the second PLL, referred to in this diagram as the core PLL This PLL takes the CCB_clk and multiplies the CCB_clk frequency up to the desired core clock for the PowerQUICC III CPU operation Due to the PowerQUICC III internal PLLs, the actual input clock or the SYSCLK will be at a much lower frequency than the CPU frequency Again, this input frequency is selected by the user and depends upon the overall system requirements

4 PQIII RapidIO Transmit Clock RIO_RCK RIO_RCK Clock Synthesis Chip RIO_TX_CLK_IN RIO_TX_CLK_IN CCB_clk RIO_TCK RIO_TCK cfg_rio_clk In addition to the SYSCLK, a second clock input requirement for the PowerQUICC III is the RapidIO transmit clock The RapidIO is a data interface between RapidIO-based devices from the PowerQUICC III to other RapidIO devices in the system Typically, the RapidIO interface is clocked from a single input called the RapidIO transmit clock (RIO_TX_CLK_IN) This clock, as shown in the block diagram, is a differential clock and, depending upon system requirements, can be 125 MHz, 250 MHz, or 500 MHz This PowerQUICC III clock input is differential and requires a standard LVDS clock The RapidIO clock can also be referenced from the receiver circuitry and used to drive the transmit clock, as shown in the diagram

5 MPC8560w/MPC9850 QUICC Clock This block diagram shows the clocking system for a PowerQUICC III device The device on the right shows the PowerQUICC III with the two PLLs mentioned previously We multiply the SYSCLK or PCI_CLK frequency up to the platform clock, and multiply that frequency again up to the core clock that is used in the system This single input clock will be somewhere in the range of 166 MHz to 133 MHz In this example, the required clock for the RapidIO clock is a 500 MHz LVDS differential clock A third clock requirement for the PowerQUICC III is the Gigabit Ethernet input/output (I/O) clock The Gigabit Ethernet clock input is 125 MHz This particular clock is usually supplied from the Gigabit Ethernet PHY as shown Typically, the PHY derives the 125 MHz from a lower frequency of 25 MHz This 25 MHz source may be provided from a simple crystal oscillator The device on the left is a clock generator created by Freescale Semiconductor's Timing Solutions Organization, which provides the clocks required by the PowerQUICC III The MPC9850 clock generator is driven by a single 25 MHz source, illustrated by the OSC oval shape in the diagram This reference is routed through the part and used to drive the Gigabit Ethernet PHY The MPC9850 clock generator provides all three clocks that are required for the PowerQUICC III The 25 MHz source is shown on the left-hand side of the MPC9850 and on the right-hand side are a series of LVCMOS outputs One of these outputs will be used for the PCI or system clock input of the PowerQUICC III On the right of the MPC9850 is the 500 MHz LVDS RapidIO clock One more output clock on the right hand side of the MPC9850 is the 25 MHz clock for the Gigabit Ethernet PHY This clock is a copy of the 25 MHz input oscillator All three clocks required for the MPC9850 are generated from a single MPC9850 device Note that the memory clock for the PowerQUICC III is generated by the previously mentioned main and local DLL circuitry If this memory clocking system is not available, the multiple copies of the PCI or system clock that are generated by the MPC9850 can provide the memory clocks However, the benefits of the DLLs for edge alignment will be lost

6 Question Question Is the following statement true or false? Click Done when you are finished Memory clocking for the PowerQUICC III is provided by two DLL blocks True False Consider this question regarding the PowerQUICC III clocking requirements Correct Memory clocking for the PowerQUICC III is provided by two DLL blocks, one for main memory and one for local memory

7 Clock Generator for MPC9850 Mouse over the diagram for a list of features System and RapidIO clocks 25 MHz or 33 MHz reference input Ext Osc or 25 MHz crystal 8 LVCMOS in two output banks 2 LVDS outputs for RapidIO VCO = 2000 MHz System output = 200, 166, 133, 125, 111, 100, 83, 66, 50, 33 or 16 MHz RapidIO = 500, 250 or 125 MHz LVDS Ref_out for I/O clock source Low cycle-to-cycle and period jitter 33V core w/25 or 33V output supply Package = 100 MAPBGA Ambient temp = -40 C to 85 C Clk PClk xtal Config OSC PLL 2GHz Data Generator QA0 QA3 QB0 QB3 QC0 QC0 QC1 QC1 Ref_Out Here is a block diagram of the MPC9850 The MPC9850 has three types of 25 MHz clock sources: a single-ended clock input called Clk, a LVPECL differential input called PClk, and a crystal oscillator input The crystal oscillator input requires an external user-provided crystal for the completion of the circuitry In either of these three cases, the source should be at 25 MHz Pins on the package allow selection of the desired input, which becomes the input to the MPC9850 PLL The 25 MHz reference is multiplied up in frequency by the PLL to 2000 MHz or 2 GHz This 2 GHz frequency is then divided down with the data generator block and provides a series of 8 LVCMOS outputs These outputs are divided into two banks labeled bank A, which is the outputs of QA0 through QA3 for a total of four, and bank B, which is QB0 through QB3 Bank B also has four outputs The MPC9850 also provides a third bank Bank C output is a differential output Bank C consists of two outputs: QC0,QC0 inverted (~QC0) and QC1, QC1 inverted (~QC1) Each of the three output banks can be set at any one of several different frequencies The selection of bank A and bank B frequencies include 200, 166, 133, 125, 111, 100, 83, 66, 50, 33, or 16 MHz There are also additional frequencies that these outputs can be set at, but the system outputs mentioned here are the typical output frequencies you would choose for the clock associated with a PowerQUICC II or PowerQUICC III system The RapidIO clock output can be selected from any one of three different frequencies, 500, 250, or 125 MHz The RapidIO outputs are LVDS In addition to bank A, bank B, and bank C, you should notice that the reference output in the lower right-hand corner comes directly from the 25 MHz source This reference output is always at 25 MHz, independent of the programming for banks A, B, and C On the left-hand side of the diagram are the configuration pins (Config) This series of pins allows you to select the frequencies for bank A, bank B, and bank C for the specific frequency you need Because banks A and B are independently programmed, they can be put at different frequencies depending upon the system For example, if you need both 66 MHz and 33 MHz for a PCI type of bus, you can put bank A at 66 MHz and bank B at 33 MHz; alternatively, you can use the processor at 133 MHz and a PCI output at 66 MHz on bank B, and so on The input reference that we have discussed up to this point has been a constant 25 MHz It is also possible to use a 33 MHz reference If a 33 MHz reference is to be used, the MPC9850 must be configured appropriately through a pin on the package If 33 MHz is used for the reference, the reference output will be 33 MHz instead of 25 MHz However, the output frequencies selected on banks A, B, and C will still be the same values The VCO and the PLL will still run at the same frequency regardless of whether the reference is 25 MHz or 33 MHz The MPC9850 operates on a 33V power supply However, separate power supply pins are provided for banks A and B, and one or both of these banks can be set to either 33V or 25V levels The MPC9850 device comes in a 100-pin BGA-type package 100 pins provide the power supply and ground pins for low-noise type applications The temperature range on the device is in the industrial temperature range of -40 C to 85 C Move your mouse pointer over the diagram to see a complete list of MPC9850 features

8 MPC9850 Block Diagram Here is a more detailed block diagram of the MPC9850 device On the upper lefthand side is the Clk input, the PCLK for differential input, the crystal input, and the select lines that are used to select between the three input sources Here you can see the select lines, CLK_A, for configuring bank A outputs Likewise, there are similar select lines for CLK_B, which configures the bank B output Two additional select lines configure the RapidIO bank C (RIO_C) On the right-hand side of the diagram are the outputs of bank A, bank B, and bank C Finally, on the lower right-hand corner is the REF_Out

9 MPC9850 Clock Architecture F REF P F FB Phase Detector Low Pass Filter VCO N Clock Dividers MPC9850 F OUT M F OUT = F REF /P * M/N with P = 1, F REF = 25 MHz and M = 80 F VCO = F REF /P * M = 25 MHz * 80 = 2000 MHz with N = 15 F OUT = F VCO /N = 2000 MHz/15 = 133 MHz Here you can see a block diagram of a generic PLL adapted to the MPC9850 clock architecture The signal F REF is a 25 MHz reference input There is an optional divide by a P prescaler block, which in the case of the MPC9850 has a value of one The PLL consists of a phase detector, a low-pass filter, a VCO, and a data generator or output dividers This is the formula for determining the F OUT frequency F OUT equals F REF divided by P multiplied by the value of the feedback counter, which is M, divided by the value of the output divider, which is N In the case of the MPC9850, P has a value of 1, the reference frequency is 25 MHz, and the M divider has a value of 80 Therefore, the VCO frequency is 25 MHz divided by 1 times 80, which is 2000 MHz, or 2 GHz The VCO frequency, 2000 MHz, divided by an N divider with a value of 15, provides an output frequency of 133 MHz If you are driving this device with an F REF of 33 MHz, the VCO still runs at 2 GHz, but to achieve this frequency, the M feedback divider needs to be 66 instead of 80 The configuration pin of SEL_33 changes the feedback divider to maintain the 2000 MHz VCO frequency

10 Low-Cost MPC9855 Mouse over the diagram for a list of features 25 MHz or 33 MHz reference input Ext Osc or 25 MHz crystal 8 LVCMOS in two output banks VCO = 2000 MHz System Output = 200, 166, 133, 125, 111, 100, 83, 66, 50, 33 or 16 MHz Ref_out for I/O clock source Low cycle-to-cycle and period jitter 33V core w/25 or 33V output supply Package = 100 MAPBGA Same footprint as MPC9850 Ambient temp = -40 C to 85 C Available Cclk Pclk xtal Config OSC PLL 2GHz Data Generator QA0 QA3 QB0 QB3 Ref_Out 0 Ref_Out 1 Another version of the QUICC Clock generator is the low-cost MPC9855 This device is pin-compatible with the same footprint as the MPC9850 The MPC9855 differs from the MPC9850 in that it has bank A and bank B outputs, but does not have bank C outputs In addition, there are two reference outputs, Ref_Out0 and Ref_Out1 This device was designed to be a lower-cost device with PowerQUICC III applications where the RapidIO is not used, or for other microprocessor systems such as the PowerQUICC II Move your mouse pointer over the diagram to see a complete list of MPC9855 features

11 Low-Cost MPC9817 Mouse over the diagram for a list of features QA0 25 MHz reference input 25 MHz crystal source or Ext Osc 5 LVCMOS outputs VCO = 400 MHz System Output = 25, 33, 50 or 66 MHz 3 reference outputs for I/O clock source Low cycle-to-cycle and period jitter 33V supply Package = 20 SSOP Ambient temp = -40 C to 85 C Available 25 MHz xtal 2 Config OSC PLL 400 MHz Data Generator QA1 QA2 QA3 QA4 QREF0 QREF1 QREF2 MR/OE A third device in the series of QUICCClock or PowerQUICC processor clock generators is the MPC9817 This clock generator is a reduced feature, low-cost clock generator that comes in a smaller package Like the MPC9850, the MPC9817 uses a 25 MHz reference, which is typically provided from a crystal across the two crystal pins However, the crystal input pin can be driven with a 25 MHz external oscillator if desired If an external source is to be used, the crystal output pin should be left open The 25 MHz reference is multiplied by the PLL to 400 MHz The 400 MHz is divided down in frequency with a data generator to provide a single bank output of five outputs called QA0 through QA4 These five outputs can be selected for a system output of 25, 33, 50, or 66 MHz, providing clocks that match the typical PCI frequencies of 33 MHz or 66 MHz In addition, the 25 MHz reference is buffered to the output on three pins called QREF0, QREF1, and QREF2 When the configuration pins are set for 25 MHz on the bank A outputs, the PLL is actually bypassed, and the 25 MHz input is buffered to all eight outputs, the five outputs of QA0 through QA4 and the QREF outputs, at the same time This device is available in a 20-pin SSOP package with an industrial temperature range of -40 C to 85 C Move your mouse pointer over the diagram to see a complete list of MPC9817 features

12 Low Cost PCI Clock Generator- MPC9819 PCI Clock Generator for PowerQUICC, PowerPC and other Microprocessor Architectures 25 MHz Reference Input 25 MHz Crystal Source or Ext Osc 5 LVCMOS outputs VCO = 400/500 MHz System Output = 66, 100, 125, or 133 MHz 3 Reference outputs for I/O clock source Low cycle-to-cycle and period jitter 33V supply Package = 20 SSOP Ambient temp = -40 to 85 deg C 25 MHz xtal 2 Config MR/OE OSC PLL Data Generator QA0 QA1 QA2 QA3 QA4 QREF0 QREF1 QREF2 [Reference Slide for Slide 11] Shown here is The MPC9819 clock generator This device is a pin and functional equivalent to the MPC9817 except for the selectable output frequencies The MPC9819 has five outputs with output frequencies of 66, 100, 125, or 133 MHz The device uses the same 25 MHz reference crystal or external oscillator This 25MHz reference is also buffered to three output pins (QREF[0:3]) as is the case with the MPC9817

13 Low Cost Microprocessor Clock Generator- MPC9824 QA0 PCI Clock Generator for PowerQUICC, PowerPC and other Microprocessor Architectures 25 MHz Reference Input 25 MHz Crystal Source or Ext Osc 6 LVCMOS outputs VCO = 400 or 500 MHz System Output = 33, 50, 66, 100, , 166, or 200 MHz 3 Reference outputs for I/O clock source Low cycle-to-cycle and period jitter 33V supply Package = 32 LQFP Ambient temp = -40 to 85 deg C 25 MHz xtal 3 Config MR/OE OSC PLL Data Generator QA1 QA2 QA3 QA4 QA5 QREF0 QREF1 QREF2 [Reference Slide for Slide 11] The MPC9824 combines the frequency options of the MPC9817 and MPC9819 with additional frequencies in a single output bank of six LVCMOS outputs The selectable frequencies are 33, 50, 66, 100, 125, 133, 166, or 200 MHz As with the other devices in this series, the reference is 25 MHz and is supplied from a selectable input of either an externally supplied source or the internal crystal oscillator A user supplied crystal is used to drive the oscillator The MPC9824 is available in a 32 pin LQFP package with ample power and ground pins for low noise operation

14 Question Question Match the device type to its description by dragging the letters on the left to their correct location on the right and click Done A MPC9850 B A clock generator that has bank A and B outputs, but does not have bank C outputs B MPC9855 C A clock generator that has reduced features and comes in a smaller package C MPC9817 A A clock generator that matches all PowerQUICC III clock requirements Done Reset Show Solution Consider this question regarding microprocessor clock generation Correct The MPC9850 matches all PowerQUICC III clock requirements, the MPC9855 has bank A and B outputs, but does not have bank C outputs, and the MPC9817 has reduced features and comes in a smaller package than the other two clock generators

15 Output-to-output Output Skew Output skew: tsk(o), within a bank, across a bank - single logic device, all inputs connected together, all outputs driving identical loads Process: tsk(pr), identical outputs on two different devices Part-to-part: tsk(pp) any two outputs on two different devices Output 1 Output 2 tsk(o) 1 n Differential Output 1 Output 2 tsk(o) 1 n Now, let s examine the characteristics of clocks and signal integrity relating to the distribution of the clocks across a PC board Many of these characteristics are found in the AC characterization section of a typical clock data sheet The first characteristic is output skew This characteristic is found in the datasheets associated with clock devices that have multiple outputs As taken from the JEDEC specification on skew and jitter, there are three specifications for output skew The first of these specifications is Output-to-output skew, or tsk(o) This is the skew from one output to the next within a bank of outputs or across a bank of outputs in a single logic device This skew parameter is usually specified on the datasheet associated with a clock generator or a clock buffer and is measured in picoseconds Process skew compares identical outputs on two different devices; however, this skew specification is not often specified The third specification for skew is part-to-part This skew definition compares any two outputs on two different devices and is widely found on data sheets for both LVCMOS and differential buffers This skew definition indicates the difference in the output phase when multiple devices are used on a PC board or the difference in output phase from one board to the next In the case of the MPC9850 or the MPC9855, the output skew is specified with two versions of output skew Skew within a bank is specified and skew across a bank is specified Skew within a bank is the difference in the output phase alignment between QA0 and QA1 and QA2 and QA3, and also QB0, QB1, QB2 and QB3 Skew across a bank is also specified, which is the difference between any output in bank A and any output in bank B

16 Jitter Statistical measure of clock cycles Presented as a maximum value, often as rms Jitter = rms * confidence factor Measurements made with a high bandwidth scope The next series of characteristics on a clock datasheet is jitter Jitter is a statistical measurement of many clock cycles Because of the statistical nature of jitter, values actually measured do not guarantee that no clock cycle will ever exceed the calculated clock cycle plus jitter value Jitter may be presented on the data sheet as a maximum value, but often jitter is presented as an rms value If the rms value is used, then the max jitter must be calculated by multiplying the rms value by a confidence factor This confidence factor is dependant on the users reliability requirements and may be 3, 4, 5, 7 or more The rms values also assume the jitter in the clock periods corresponds to the statistical bell curve If not, and often they do not, then manipulating the rms values will not necessarily represent the real statistical nature of jitter Lastly, actual jitter measurements are made with a high bandwidth scope that captures the period information over a large number of clock cycles This period information is then used as the input to a computer program that analyzes the zero crossings, or period values, and displays the resultant information as graphs, tables, or final jitter values Many hardware and software vendors provide proven techniques and equipment for jitter measurement

17 Cycle-to-Cycle Jitter Cycle-to-cycle: tjit(cc) Period variations between adjacent cycles, over a random sample of adjacent cycle pairs t n t n+1 t Jit(CC) = t n -t n+1 Ideally, jitter should be zero, but unfortunately in a real system it's not, so there are different specifications depending upon the different types of measurements associated with jitter The first type of jitter is cycle-to-cycle jitter, or tjit(cc) Cycle-to-cycle jitter is the period variation between adjacent cycles over a random number of adjacent cycle pairs As shown in the diagram, the comparison is made between the period of t(n) versus the period on the cycle t(n+1) This equation above subtracts the period of t(n+1) from the period of t(n) The absolute value is taken to ensure that the result value is always a positive number Either the next two cycles will be compared, or after some random period of time, two more adjacent cycles are compared This type of jitter is measured in picoseconds and is usually represented as the worse case value of the adjacent pairs Cycle-to-cycle jitter may be calculated over as many as adjacent pairs of cycles with the value reported on the data sheet being the worse case value plus margin The extra margin is to ensure that the value shown is indeed the worse case jitter for the device Ideally, cycle-to-cycle jitter is zero, but typical values are 100 to 150 picoseconds for LVCMOS clock generators Cycle-to-cycle jitter is important to the design of the PowerQUICC III system as well as the system components that are associated with the PowerQUICC III processor Jitter affects the timing calculations by requiring you to subtract the jitter value from the overall clock period

18 Period Jitter Period jitter: tjit(per) The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles 1/f 0 Ideal Output t cycle n Actual Output t jit(per) = t cycle n -1/f 0 A second jitter specification is period jitter Period jitter is the deviation in cycle time of a signal with respect to the ideal period As with cycle-to-cycle jitter, the measurement is made over a random sample of cycles This equation shows the subtraction of period of t(cycle n) from the ideal cycle As with cycle-to-cycle jitter, you take the absolute value of this difference The value presented on the datasheet will always be a positive number The data sheet value represents the worse case difference in the period as accumulated over a large number of cycles

19 Phase Jitter Phase jitter: tjit(φ) Alias Input-to-Output Jitter Reference Clock Input Feedback Input tjit(φ) = t(φ) - t(φ) mean t(φ) Phase jitter is a third jitter type that is quite often found on clock driver data sheets It is only associated with PLL-based clock devices Phase jitter compares the input clock reference against the feedback input of the PLL Phase jitter compares the difference between the average value of the reference input clock and the feedback clock The absolute value is taken such that the jitter value is always positive Phase jitter may or may not be specified on the specific datasheet Depending upon your specific application, any or all of the three types of jitter, cycle-tocycle, period, or phase, may interest you

20 Question Question Match the clock characteristics to their descriptions by dragging the letters on the left to their correct location on the right and click Done A Output skew B The period variation between adjacent cycles over a random number of adjacent cycle pairs B Cycle-to- Cycle jitter C The deviation in cycle time of a signal with respect to the ideal period C Period jitter A The skew from one output to the next within a bank of outputs or across a bank of outputs in a single logic device D Phase jitter D The comparison of the input clock reference against the feedback input of the PLL Done Reset Show Solution Consider this question regarding the characteristics of clocks and signal integrity Correct! Output skew is the skew from one output to the next within a bank of outputs or across a bank of outputs in a single logic device Cycle-to-cycle jitter is the period variation between adjacent cycles over a random number of adjacent cycle pairs Period jitter is the deviation in cycle time of a signal with respect to the ideal period Phase jitter compares the input clock reference against the feedback input of the PLL

21 LVDS LVDS: TIA/EIA-644-A Low signaling voltage (330mv) Voltage offset = VB VA VA-VB 12V typical VA +250 to +450mv 0V (Diff) -250 to- 450mv Let s examine some other topics of interest pertaining to clock tree design and specifically PowerQUICC III clock design The MPC9850 generates the LVDS clock level that is used for the RapidIO clock input of the PowerQUICC III The clock levels of LVDS is one of several popular differential clock levels in use today The specification for LVDS is found in a TIA/EIA specification The LVDS requires an approximate 330 mv swing, and it is a differential signal with an offset of approximately 12V The typical application is to distribute the differential clock across the PC board to the receiver input and terminate the differential pair with a 100 ohm resistor that is either inside the receiver device or with a user-supplied resistor at the input of the receiver Here you can see the LVDS voltage levels are shown on the right

22 Power Supply Filter Many clock drivers have separate output and PLL VCC pins R S is calculated based upon Maximum PLL current Inductor may be used for R S Filter with high quality caps at package V DDA V DD 25V or 33V R S 01µf 22µf 01µf Another requirement of clean, jitter-free clock generation is to provide circuitry with the cleanest power supply possible Jitter or noise on the power supply will show up on the clock outputs The impact can be minimized using several methods, including multiple power and ground pins and separating the power supply pins to minimize noise on the most sensitive portions of the circuitry As always, proper supply bypassing with lots of caps is a must The power supplies associated with the MPC9850 and MPC9855 are divided into three different supplies The main 33V supply is the VDD supply There are separate supplies for the A bank of outputs and the B bank of outputs The power supply has a separate pin called VDDA This supply is used for the more sensitive portion of the analog PLL: the goal is to ensure that this supply pin is as clean and noise free as possible To achieve this, the main supply is filtered with a RC filter The resistor (R S ), which is typically about 15 ohms, provides the R, and 01 and 22 microfarad caps are used for the C Two separate, different values and cap types are used for the value of C Using two sizes and types of capacitors provides both a highfrequency capacitor and a low-frequency larger valued capacitor In addition, the VDD should have multiple 001 or 01 microfarad capacitors surrounding the clock generator package

23 Traces and Transmission Lines PC board traces at the frequencies typically associated with clocks are transmission lines Transmissions lines have a propagation delay Transmissions lines have a characteristic impedance Match the clock drive impedance to the impedance of the line to minimize waveform reflections Engineer the PC board trace as a controlled impedance microstrip or stripline Differential clocks may ease PC board layout due to ground plane issues Let s look at the traces and transmission lines on the PC board The frequencies that you typically deal with in these types of applications imply that the PC board traces become transmission lines Transmission lines have a propagation delay as the clock is moved from source to destination They also have a characteristic impedance Many transmission line designs on PC boards are typically at 50 ohms To deliver the highest quality clock signal to the destination, the clock design needs to match the clock drive impedance to the impedance of the transmission line This helps to minimize waveform reflections on the transmission line You should engineer the PC board trace as a controlled impedance microstrip or stripline and make sure that the source impedance matches the characteristic impedance of the transmission line Designs may also use differential clocks, which can ease the PC board layout due to ground plane issues Differential signals are especially valuable in higher-frequency clock design such as the 500 MHz RapidIO clock

24 Parallel Terminated Lines Point A tpd Z0 Point B R0 VDDQ VTT = VDD/2 Point A VDD tpd VDDQ 2 * R0 Point B 2 * R0 PC board clock distribution transmission lines should be terminated, and you can use one of these common techniques: parallel termination and series termination Either one can be chosen as the termination technique for distributing clocks across the PC board to ensure the best signal integrity of the clock signal The diagram above represents the parallel termination of a transmission line The parallel terminating resistor is placed at the destination, which is at the input to the receiver The terminating resistor is labeled as R0 The value of R0 is chosen to match the characteristic impedance of the transmission line If the characteristic impedance of the transmission line is 50 ohms, then R0 will equal 50 ohms R0 is connected between the receiver input and a voltage called VTT In the case of LVCMOS types of transmission lines and voltage levels, VTT will be half the VDD level If a VTT source is not directly available, it can be created by using two resistors between the input One resistor is tied to ground and the other one is tied to the VDD supply The parallel combination of the two resistors equals 50 ohms, and the voltage level at the input to the receiver will be VDD divided by 2 The length of the transmission line is shown as the propagation time for the signal as it travels down the transmission line The tpd represents this time period Typical propagation times are approximately 2 ns/ft of PC board trace The actual value can be calculated based upon PC board material characteristics, and this value should be available from the PC board supplier

25 Series Terminated Lines Point A Rout R S Point B tpd Z0 Point C R S = ZO - R out Point A VDDQ tpd tpd VDDQ Point B VDDQ/2 VDDQ Point C Series termination is a more common technique for terminating LVCMOS clocks It relies upon a single resistor connecting the clock driver output to the transmission line The single resistor is located at the source The far end of the transmission line, or the receiver end, is left unconnected to anything other than the high-impedance receiver Series termination requires that a series resistor be chosen such that the combination of the series resistor plus the internal output impedance of the clock driver equals the characteristic impedance of the transmission line Therefore, if the impedance of the transmission line is 50 ohms, the value of R S is selected to be 50 ohms minus the internal impedance of the clock driver The internal output impedance of the driver might be 10 ohms, 15 ohms, or as high as 20 ohms The data sheet for the specific device should specify the output impedance of the clock driver Series termination works as follows Note the labeling of points A, B, and C in the diagram Point A is located between the receiver output and the termination resistor Point B is located between the far side of the termination resistor and the start of the transmission line Thus the termination resistor is located very close to the clock driver output Point C is located at the far end of the transmission line and right at the receiver input Remember that the output impedance of the clock driver plus the R S equals the characteristic impedance of the transmission line As the clock waveform transitions from low to high, the voltage on Point B will be the full clock driver supply voltage, divided by the voltage divider produced by the output impedance of the clock driver plus R S and the characteristic impedance of the transmission line Both elements of this voltage divider are the same, therefore the voltage at point B is half of the full output voltage This half voltage is then propagated down the transmission line At point B, and for a rising edge, you would see the voltage go from zero to half of the VDD voltage value As this voltage propagates down to the far end of the transmission line in time period tpd, 05 times the full output voltage reaches the receiver A high impedance exists at the receiver, so 100 percent of the incoming waveform reflects back up the transmission line following the original waveform s path 100 percent reflection means that the reflected waveform is added to the existing waveform value Thus 05 of the full output voltage plus 05 of the full output voltage implies Point C goes to the value of full output voltage This additional half voltage waveform takes the propagation time of one tpd time to travel back to the series resistor plus the clock driver output impedance combination at point B Next, another half of the full output voltage is added to point B s existing half of the full output voltage from the original voltage divider Now, Point B is up to the full output voltage However, Point B has a termination resistance of the characteristic impedance of the transmission line, so the waveform is properly terminated and no further reflection occurs This termination resistance is the combination of R S and the output impedance of the clock driver or 50 ohms The steady state condition of the transmission line is full output voltage at both ends of the transmission line, therefore no current flows down the transmission line until the next clock transition appears on the output of the clock driver The advantage of the series termination technique is that it only requires a single output resistor and does not require a VTT voltage to be generated The disadvantage is that it requires the selection of R S to be used in conjunction with the output impedance of the clock generator Different clock driver output impedances require different R S values

26 Question What is the advantage of the series termination technique? Select the correct answer and then click Done a This technique requires the selection of R s to be used in conjunction with the output impedance of the clock generator b This technique requires a single output resistor and does not require a VTT voltage to be generated c This technique requires the parallel terminating resistor to be placed at the destination or at the input to the receiver d This technique requires one resister to be tied to ground and the other one to be tied to the VDD supply Done Consider this question regarding series terminated lines Correct The advantage of the series termination technique is that it only requires a single output resistor and does not require a VTT voltage to be generated

27 Clock Drivers on the Web Web site Data Book and Selector Guide DL207 Data Book SG392 Selector Guide Application Notes AN1091 Low Skew Clock Drivers and Their System Design Considerations AN1405 ECL Clock Distribution Techniques AN1545 Thermal Data for MPC Clock Drivers AN1934 Effects of Skew and Jitter on Clock Tree Design AN1939 Clock Driver Primer - Functionality and Usage AN1993 Clock Generation for PowerQUICC III Evaluation Boards MPC9850EVM Evaluation Board for MPC9850 MPC9817EVM Evaluation Board for MPC9817 Let s take a look at some of the documentation that is available on the clock devices that we have examined and some additional application information that is available from Freescale Semiconductor, Technical and Sales Collateral Here is the website location for Freescale s clock datasheets Also available is a hard copy data book, which you can order as DL207 The Advanced Clock Driver selector guide, SG392, is available in both hardcopy and online The selector guide has the usual clock selector tables followed by block diagrams for each clock driver available from Freescale Also available is series of application notes dealing with clock topics Application note AN1934 focuses on skew and jitter of clock trees Application note AN1939 goes through the basics of clock generation, basics of PLL operation, and termination of transmission lines Application note AN1993 covers clock generation for the PowerQUICC III processor and parallels much of the discussion in this course Additional evaluation boards for the MPC9850 and the MPC9817 are available

28 MPC9850 EVAL Board 5V Power Supply 100-pin BGA 25 MHz Crystal SMA Connectors Here you can see the MPC9850 evaluation board In the center of the board is the 100-pin BGA-type package of the MPC9850 Here you can see the 25 MHz crystal that drives the MPC9850 to the 2 GHz VCO frequency The outputs of bank A and bank B are available through SMA connectors The board is powered by a 5V supply using an on-board voltage regulator for the 33V supply

29 Course Summary Freescale clock product categories PowerQUICC III clocking requirements Freescale QUICC Clocks Clock characteristics Signal Integrity Thank you for taking this course on Freescale timing solutions products This course provided you with an overview of the five Freescale clock product categories and identified the types of clock devices you can use to satisfy PowerQUICC III clocking requirements You learned that Freescale Semiconductor currently offers three devices that are specifically designed for PowerPC and PowerQUICC types of devices: the MPC9850, the MPC9855, and the MPC9817 You also examined clock characteristics and signal integrity issues that are fundamental to understanding PowerQUICC, PowerPC, and other microprocessor environments