ECE 5745 Complex Digital ASIC Design Topic 7: Packaging, Power Distribution, Clocking, and I/O

Transcription

1 ECE 5745 Complex Digital ASIC Design Topic 7: Packaging, Power Distribution, Clocking, and I/O Christopher Batten School of Electrical and Computer Engineering Cornell University

2 Packaging Power Distribution Clocking I/O Part 1: ASIC Design Overview P M P M Topic 1 Hardware Description Languages Topic 4 Full-Custom Design Methodology Topic 6 Closing the Gap Topic 5 Automated Design Methodologies Topic 8 Testing and Verification Topic 3 CMOS Circuits Topic 2 CMOS Devices Topic 7 Clocking, Power Distribution, Packaging, and I/O ECE 5745 T07: Packaging, Power Distribution, Clocking, and I/O 2 / 39

3 Packaging Power Distribution Clocking I/O Agenda Packaging Power Distribution Clocking I/O ECE 5745 T07: Packaging, Power Distribution, Clocking, and I/O 3 / 39

4 Packaging Power Distribution Clocking I/O Basic Approaches to Packaging Ball Grid Array (BGA) Adapted from [Terman 02] ECE 5745 T07: Packaging, Power Distribution, Clocking, and I/O 4 / 39

5 Packaging Power Distribution Clocking I/O Basic Package Types What makes a good package? Low cost Small size Good thermal performance Large number of pins Low pin parasitics Easy to test Highly reliable Adapted from [Weste 11] ECE 5745 T07: Packaging, Power Distribution, Clocking, and I/O 5 / 39

6 Packaging Power Distribution Clocking I/O Basic Package Types DIP 8 64 Two rows of through-hole pins. 100mil pitch. Low cost. Long wires between chip and corner pins. PGA Array of through-hole pins. 100mil pitch. Low thermal resistance and higher pin counts. SOIC 8 28 Two rows of SMT pins. 50mil pitch. Low cost. TSOP Two rows of SMT pin mil pitch in thin package. Used in DRAMs. QFP SMT pins on 4 sides mil pitch. High density. BGA Array of SMT solder balls on underside of package on 15 50mil pitch. Very high density with low parasitics. Costly assembly. LGA Many Similar to BGA but with gold pads instead of solder balls. Commonly used with sockets (processors). Adapted from [Weste 11] ECE 5745 T07: Packaging, Power Distribution, Clocking, and I/O 6 / 39

7 Packaging Power Distribution Clocking I/O Wire-Bond Pad Ring Adapted from [Weste 11] ECE 5745 T07: Packaging, Power Distribution, Clocking, and I/O 7 / 39

8 6.371 Fall /1/02 L17 Packaging 6 Packaging Power Distribution Clocking I/O Wire Bonding Process Bond Wires Wire bonding machine Usually ultrasonic welding connects wire to package and die pad Bond wires can be aluminum or gold Different thicknesses of bond wire tradeoff parasitic inductance and resistance versus density Can wirebond to die pad pitches of around 100 m Adapted from [Terman 02] ECE 5745 T07: Packaging, Power Distribution, Clocking, and I/O 8 / 39

9 Packaging Power Distribution Clocking I/O Pin-Grid Array Assembly Process Pin-Grid Array Assembly Process Saw Die Attach (glue to package) Oven Cure Die Attach Tested Wafer Die Wire bond pads on die to pads on package Final Test Screen Printing Oven Cure Lid Attach Fall /1/02 Glue lid on package Adapted from [Terman 02] L17 Packaging 5 ECE 5745 T07: Packaging, Power Distribution, Clocking, and I/O 9 / 39

10 Packaging Power Distribution Clocking I/O Summary of Package Parasitics Adapted from [Weste 11] ECE 5745 T07: Packaging, Power Distribution, Clocking, and I/O 10 / 39

11 Packaging Power Distribution Clocking I/O Pad on die Pin Parasitics Pin Parasitics Bond wire Package trace Package pin R bond L bond R trace L trace R pin L pin C pad C bond C trace C pin Wire bond, C bond =1pF, L bond =1nH bond wire L approx. 1nH/mm Solder bump, C bond =0.5pF, L bond =0.1nH 68-pin DIP, C pin =4pF, L pin =35nH 256-pin PGA, C pin =3-5pF, L pin =5-15nH BGA, C pin =2-4pF, L pin =1-8nH Fall /1/02 Adapted from [Terman 02] L17 Packaging 8 ECE 5745 T07: Packaging, Power Distribution, Clocking, and I/O 11 / 39

12 Packaging Power Distribution Clocking I/O Challenge: Power Delivery Scaling Power = Volts Amps CPU power consumption is increasing 2x per technology generation Supply voltages are dropping have to control electric field strength as transistors shrink keep power from growing even faster Power is going up, voltage is going down = current rising fast 100W at 1V implies 100A of current ECE 5745 T07: Packaging, Power Distribution, Clocking, and I/O 12 / 39

13 Packaging Power Distribution Clocking I/O Challenge: Static IR Droop IR Drop V DD I supply V DD -(I supply *R supply ) R supply Chip Want to keep voltage droop (V = IR) small Example, for 100W@1V, I=100A 5% droop is 50mV At 100A, need effective supply resistance < Dissipate 5W heat just in power supply leads Use multiple parallel Vdd/GND pins Need very short fat wires to board power regulator Want very low resistance on-chip power network Adapted from [Terman 02] Fall /1/02 L17 Packaging 11 ECE 5745 T07: Packaging, Power Distribution, Clocking, and I/O 13 / 39

14 Packaging Power Distribution Clocking I/O Challenge: Dynamic di/dt Droop Simultaneous Output Switching Noise V B A s switch V DD L package L package I A B 64 L package t A large number of output drivers A switching high try to pull current through the power supply inductance, causing the internal power rail connected to gate B to droop (V=LdI/dt) Gates driven by B may switch incorrectly. Adapted from [Terman 02] ECE Fall 2002 T07: Packaging, Power Distribution, 11/1/02 Clocking, and I/O L17 Packaging 14 / 399

15 Packaging Power Distribution Clocking I/O Challenge: Heat Dissipation One Dimensional Thermal Model Heatsink Die Airflow Thermal Slug (Tungsten) Die Attach Glue (silver filled) Sample overall ja: DIP 38 C/W still air DIP 25 C/W forced air PGA 5-10 C/W forced air Microproc.and fan <3 C/W (fluid pumped through die microchannels 0.02 C/W) Power Tjunction glue Tglue Tslug sink Tsink air Tambient C die C glue C slug C sink Adapted from [Terman 02] Fall 2002 ECE /1/02 T07: Packaging, Power Distribution, Clocking, and I/O L17 Packaging / 39

16 Packaging Power Distribution Clocking I/O Agenda Packaging Power Distribution Clocking I/O ECE 5745 T07: Packaging, Power Distribution, Clocking, and I/O 16 / 39

17 Power Distribution: The Issue Possible IR drop across power network Packaging Power Distribution Clocking I/O Power Distribution Network Parasitics VDD VDD R eff R eff C g Reff C d C g Reff C d GND GND Spring 2006 L06 Managing Physical Design Issues in ASIC Toolflows 39 ECE 5745 T07: Packaging, Power Distribution, Clocking, and I/O 17 / 39

18 Power Distribution: The Issue IR drop can be static or dynamic Packaging Power Distribution Clocking I/O Static and Dynamic IR Drop Static IR Drop Dynamic IR Drop Are these parasitic capacitances bad? VDD VDD R eff R eff C g Reff C d C g Reff C d GND GND Spring 2006 L06 Managing Physical Design Issues in ASIC Toolflows 40 ECE 5745 T07: Packaging, Power Distribution, Clocking, and I/O 18 / 39

19 Packaging Power Distribution Clocking I/O Realistic Power Distribution Networks Adapted from [Weste 11] ECE 5745 T07: Packaging, Power Distribution, Clocking, and I/O 19 / 39

20 Power Distribution: Custom Approach Carefully Varioustailor Approaches power tonetwork Power Distribution Packaging Power Distribution Clocking I/O G V G V B A Routed power distribution on two stacked layers of metal (one for VDD, one for GND). OK for lowcost, low-power designs with few layers of metal. V G V G V G V G V G V G Power Grid. Interconnected vertical and horizontal power bars. Common on most high-performance designs. Often well over half of total metal on upper thicker layers used for VDD/GND. V G V G V G V V G V G V G V Dedicated VDD/GND planes. Very expensive. Only used on Alpha Simplified circuit analysis. Dropped on subsequent Alphas. G G V G V G Spring 2006 L06 Managing Physical Design Issues in ASIC Toolflows 41 ECE 5745 T07: Packaging, Power Distribution, Clocking, and I/O 20 / 39

21 Packaging Power Distribution Clocking I/O Power Distribution for Standard Cells Adapted from [Weste 11] ECE 5745 T07: Packaging, Power Distribution, Clocking, and I/O 21 / 39

22 Power Distribution: ASIC Approach Packaging Power Distribution Clocking I/O Modular Power Distribution Networks Power rings partition the power problem Early physical partitioning and prototyping is essential Can use special filler cells to help add decoupling cap Spring 2006 L06 Managing Physical Design Issues in ASIC Toolflows 43 ECE 5745 T07: Packaging, Power Distribution, Clocking, and I/O 22 / 39

23 Fine-grain power distribution over entire chip reduces IR d Example of power distribution netw Packaging Power Distribution Clocking I/O Scale Power Distribution Network using commercial ASIC back-end to ade au sma Works ECE 5745 T07: Packaging, Power Distribution, Clocking, and I/O 23 / 39

24 Packaging Power Distribution Clocking I/O Agenda Packaging Power Distribution Clocking I/O ECE 5745 T07: Packaging, Power Distribution, Clocking, and I/O 24 / 39

25 Clock Distribution: The Issue Packaging Power Distribution Clocking I/O Goal of Clock Distribution Clock propagates across entire chip Clock Cannot really distribute clock instantaneously with a perfectly regular period Spring 2006 L06 Managing Physical Design Issues in ASIC Toolflows 28 ECE 5745 T07: Packaging, Power Distribution, Clocking, and I/O 25 / 39

26 Clock Distribution: The Issue Packaging Power Distribution Clocking I/O Clock Skew Two forms of variability Clock Skew Difference in clock arrival time at two spatially distinct points B A A B Skew Usable Clock Period Spring 2006 L06 Managing Physical Design Issues in ASIC Toolflows 29 ECE 5745 T07: Packaging, Power Distribution, Clocking, and I/O 26 / 39

27 Clock Distribution: The Issue Packaging Power Distribution Clocking I/O Clock Jitter Two forms of variability Period A!= Period B Clock Jitter Difference in clock period over time Spring 2006 L06 Managing Physical Design Issues in ASIC Toolflows 30 ECE 5745 T07: Packaging, Power Distribution, Clocking, and I/O 27 / 39

28 Clock Distribution: The Issue Packaging Power Distribution Clocking I/O Why is minimizing skew and jitter hard? Sources of Clock Skew and Jitter Clock Distribution Network Variations in trace length, metal width and height, coupling caps Central Clock Driver Variations in local clock load, local power supply, local gate length and threshold, local temperature Local Clock Buffers ECE 5745 T07: Packaging, Power Spring Distribution, 2006 L06 Clocking, Managing andphysical I/O Design Issues in ASIC Toolflows 28 / 31 39

29 Clock Distribution: Custom Approach Packaging Power Distribution Clocking I/O Clock grids lower skew but high power Clock Grids: Low Skew but High Power Grid feeds flops directly, no local buffers Clock driver tree spans height of chip Internal levels shorted together Spring 2006 L06 Managing Physical Design Issues in ASIC Toolflows 32 ECE 5745 T07: Packaging, Power Distribution, Clocking, and I/O 29 / 39

30 Clock Distribution: Custom Approach Packaging Power Distribution Clocking I/O Trees have more skew but less power Clock Trees: More skew but Less Power H-Tree RC-Tree Recursive pattern to distribute signals uniformly with equal delay over area Each branch is individually routed to balance RC delay ECE 5745 T07: Packaging, Power Distribution, Clocking, and I/O 30 / Spring 2006 L06 Managing Physical Design Issues in ASIC Toolflows 33

31 Packaging Power Distribution Clocking I/O ample of clock tree synthesis Example using of clock tree synthesis usin mmercial ASIC back-end Clocktools commercial Tree Synthesis ASIC back-end tools CAD tools generate balanced RC trees Spring 2006 L06 Managing Physical Design Issues in ASIC Toolflows 37 Static analysis to measure clock skew and factor it into static timing analysis Spring 2006 L06 Managing Physical Design Issues in ASIC ECE 5745 T07: Packaging, Power Distribution, Clocking, and I/O 31 / 39

32 Packaging Power Distribution Clocking I/O Example Skew/Jitter Analysis Adapted from [Xiu 08] ECE 5745 T07: Packaging, Power Distribution, Clocking, and I/O 32 / 39

33 Packaging Power Distribution Clocking I/O Example Skew/Jitter Analysis Adapted from [Xiu 08] ECE 5745 T07: Packaging, Power Distribution, Clocking, and I/O 33 / 39

34 Clock Distribution: Custom Approach Packaging Power Distribution Clocking I/O Active Deskewing Circuits in Intel Itanium Active deskewing circuits in Intel Itanium Active Deskew Circuits (cancels out systematic skew) Phase Locked Loop (PLL) Regional Grid Spring 2006 L06 Managing Physical Design Issues in ASIC Toolflows 34 ECE 5745 T07: Packaging, Power Distribution, Clocking, and I/O 34 / 39

35 Packaging Power Distribution Clocking I/O Agenda Packaging Power Distribution Clocking I/O ECE 5745 T07: Packaging, Power Distribution, Clocking, and I/O 35 / 39

36 Packaging Power Distribution Clocking I/O Single-Ended I/O Standards Adapted from [ ECE 5745 T07: Packaging, Power Distribution, Clocking, and I/O 36 / 39

37 Packaging Power Distribution Clocking I/O I/O Pads Adapted from [Weste 11] ECE 5745 T07: Packaging, Power Distribution, Clocking, and I/O 37 / 39

38 Packaging Power Distribution Clocking I/O High-Speed Serial I/Os Pins are an expensive part of a system Physical cost of adding pin to package Size of package increases with more pins and on-pkg routing to pin Bonding cost per pin Size of motherboard depends on package size More pins complicates board-level routing Board testing time grows with number of pins Reliability is function of number of solder connections Trend towards high-speed serial I/O As computing performance grows, pins become system bottleneck Want maximum bandwidth from available pins Current SerDes run at 3 6 Gb/s per link at <200 mw ECE 5745 T07: Packaging, Power Distribution, Clocking, and I/O 38 / 39

39 Packaging Power Distribution Clocking I/O Acknowledgments [ Chart of Low Voltage IC Switching. [Terman 02] C. Terman and K. Asanović, MIT Introduction to VLSI Systems, Lecture Slides, [Weste 11] N. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 4th ed, Addison Wesley, [Xiu 08] L. Xiu, VLSI Circuit Design Methodologies, Wiley-IEEE Press, ECE 5745 T07: Packaging, Power Distribution, Clocking, and I/O 39 / 39