Moore s s Law, 40 years and Counting

Transcription

1 Moore s s Law, 40 years and Counting Future Directions of Silicon and Packaging Bill Holt General Manager Technology and Manufacturing Group Intel Corporation InterPACK Heat Transfer Conference

2 Key Messages Systems/platform focus drives increased requirements for silicon and packaging Making the right choice between on-chip and in/on package integration is critical to cost effective solutions Moore s s Law is the engine for continued growth Silicon is ideal for homogenous integration Packaging is ideal for heterogeneous integration

3 Next Decade s s Platform Evolution IDENTITY TRUST AUTONOMICS SPECIAL PURPOSE HARDWARE 3D Packaging SPEECH Photonics Parallel Processing Machine Learning SENSORS Planetary Computing Virtual Platforms Reconfigurable Cache LOW POWER VISION

4 Growth also Driven by Better User Experiences Security User Virtualization Experience Multitasking Manageability Ease of Use Battery Life Compactness Wireless Mobility Multimedia Networking Graphics Computing Memory

5 Engineering Platform Requirements and then there are the Engineering System Volume ( cubic inch) PC tower Mini tower µ tower Slim line Small pc Shrinking volume Quieter Yet, High Performance Thermal Budget ( o C/W) Pentium III Pentium 4 Projected Air Flow Rate Projected Heat Dissipation Volume Thermal Budget Power (W) Heat-Sink Volume (in 3 ) Air Flow Rate (CFM) Thermal budget decreasing Higher heat sink volume Higher air flow rate Source: Intel

6 Memory Challenges Bandwidth driven requirements 1,800 6 Host Pin Count 1, MB Channel Width Host Pin Count 3 Channel Width MHz Latency Logic 500 Memory GAP Source: IDF

7 Interconnect RC Delay Challenges Clock Period 1000 Delay (ps) RC delay of 1mm interconnect Copper Interconnect nm 130nm 90nm 65nm Process Technology Source: IDF

8 Low-K K ILD Integrity Challenges Die Package Reduce stress transmitted to die to enable lower-k k ILD Source: Intel

9 Thermal Management S17 0 S S1 Challenges Infrared image Hot spot mitigation Reduce thermal resistance (bulk & interface) Holistic system level optimization Airflow and layout enhancements Power distribution Focus on optimizing all aspects of the cooling system Source: Intel

10 Key Messages Systems/platform focus drives increased requirements for silicon and packaging Making the right choice between on-chip and in/on package integration is critical to cost effective solutions Moore s s Law is the engine for continued growth Silicon is ideal for homogenous integration Packaging is ideal for heterogeneous integration

11 System on a Chip Definition: Integration of all components into a single chip Integrating similar technologies provides cost and performance/power advantages Example: Logic, processing, SRAM, etc in Digital CMOS Integrating dissimilar technologies requires balancing cost, process, and functional tradeoffs edram SiGe + CMOS Flash Memory + Logic

12 Integration via Silicon (SoC) Logic 90nm 90nm Transistor Gate on 0.13µm Process Intel MicroSignal Architecture Flash+Logic S R A M Flash Power mgmt & peripherals 0.16µm2 Flash Cell Cell phone stds. PXA800F Cellular Processor Density, Speed, & Power Consumption are improved Cost, complexity, and flexibility suffer Source: Intel

13 System in a Package Definition: Integration of all components in/on a single package Ideal for Integrating functions delivered by dissimilar technologies Example: Memory, RF, communications, etc Provides size, flexibility, and performance/power advantages Will eventually lose to SoC (ie Moore s s Law) when integrating functions implemented in similar technology Example: Logic + SRAM, Stacking for bit density

14 Integration via Package (SiP) Pragmatic SIP Sub-System System in a Package : Relevant functionality combined in single package (e.g. Logic + Memory, RF etc.) when it makes business & technical sense Analog Power Mgmt DRAM DATA FLASH Module Computation Cellular application Ultimate SIP Single multi-function, package with all needed system-level functions (e.g. Analog, Digital, Optical, RF and MEMs)? Source: Intel

15 Success is determined by making the right tradeoffs SIP Flexibility TTM Opportunity For Advantage Performance SOC Optimization will occur as cost, performance and flexibility/ttm balance

16 Key Messages Systems/platform focus drives increased requirements for silicon and packaging Making the right choice between on-chip and in/on package integration is critical to cost effective solutions Moore s s Law is the engine for continued growth Silicon is ideal for homogenous integration Packaging is ideal for heterogeneous integration

17 Moore s s Law Transistors Per Die Reduced cost is one of the big attractions of integrated electronics, and the cost advantage continues to increase as the technology evolves toward the production of larger and larger circuit functions on a single semiconductor substrate. Electronics, Volume 38, Number 8, April 19, Data (Moore) Source: Intel

18 Moore s s Law Transistors Per Die K 512M 1G 256M 2G 128M 64M Itanium 2 Processor 16M Itanium Processor 4M Pentium 4 Processor 1M Pentium III Processor 256K Pentium II Processor Pentium Processor 64K 16K 486 Processor 4K Processor Data (Moore) Memory Microprocessor Source: Intel

19 The Economics of Moore s s Law As the number of transistors goes UP Cost per transistor goes DOWN Source: WSTS/Dataquest/Intel, 3/04

20 Scaling: The Fundamental Cost Driver 350nm 200mm 250nm 200mm 180nm 200mm 130nm 200mm 90nm 300mm 65nm 300mm Dual Core Twice the circuitry in the same space (architectural innovation) The same circuitry in half OR = the space (cost reduction) Half the die size for the same capability than in the prior process

21 Wafer Size: Enables Cost Efficiency Wafer Diameter (mm) mm development 300mm mm 150mm 125mm m 75m m 50mm m Projected Year That Industry Exceeds 3 Million wafers/year Source: VLSIR 450mm

22 Moore s s Law + Bigger Wafers = Lower Cost/function 100 nanodollars per transistor (1 cent = 100,000 transistors) '68 '70 '72 '74 '76 '78 '80 '82 '84 '86 '88 '90 '92 '94 '96 '98 '00 '02 Source: WSTS/Dataquest/Intel, 3/04

23 Key Messages Systems/platform focus drives increased requirements for silicon and packaging Making the right choice between on-chip and in/on package integration is critical to cost effective solutions Moore s s Law is the engine for continued growth Silicon is ideal for homogenous integration Packaging is ideal for heterogeneous integration

24 Silicon Technology Reaches Nanoscale 10 Nominal feature size Micron Gate Length Nanotechnology (< 100nm) nm 90nm 0.7X every 2 years 65nm 45nm 32nm 70nm 22nm 50nm 35nm 25nm 18nm 12nm 1000 Nano- meter Source: Intel

25 Strained Silicon Improves Transistor Performance and Leakage Today 1000 Std Strain Std Strain Transistor Leakage Current (na/um) % I ON +10% I ON 0.20x I OFF 0.04x I OFF 1 PMOS NMOS Transistor Drive Current (ma/um) Source: Intel

26 High-k k Dielectric Can Reduce Gate Leakage Tomorrow Gate 1.2nm SiO 2 Gate 3.0nm High-k Silicon substrate Silicon substrate Gate capacitance Gate dielectric leakage High-k k vs. SiO 2 60% greater > 100x reduction Benefit Faster transistors Lower power Process integration is the key challenge Source: Intel

27 Transistors Require Optimization to the Application Performance vs. Leakage Optimized transistors can provide ~1000x lower leakage

28 Sleep Transistor Reduces SRAM Leakage Power V DD 70 Mbit SRAM leakage current map SRAM Cache Block NMOS Sleep Transistor Accessed block V SS Without sleep transistor With sleep transistor >3x SRAM leakage reduction on inactive blocks Source: Intel

29 Advances in Power Efficient Design Power (W) ISSCC 2005 P10.1 The Implementation of a 2-core 2 Multi-Threaded Itanium TM Family Processor Using prior design techniques With new power reduction techniques

30 Silicon Scaling Still Improves Density, Performance, Power, Cost 130 nm 90 nm Madison Montecito Cores/Threads 1/1 2/4 Transistors Billion L3 Cache 6 24 MByte Frequency 1.5 >1.7 GHz Relative Performance 1 >1.5x Thermal Design Power 130 ~100 Watt Source: Intel

31 Innovation-Enabled Technology Pipeline Technology Technology Generation Generation 90 nm 65 nm 45 nm nm 32 nm Manufacturing Development Research 50 nm SiGe S/D Strained Silicon 35 nm SiGe S/D Strained Silicon 30 nm Metal Gate High-k 20 nm Tri-Gate 10 nm 5 nm Nanowire Si Substrate S D S Future options subject to change G III-V Carbon Nanotube FET Source: Intel

32 Transistors/Die Moore s s Law Will Outlive CMOS 10µm 13 Bipolar PMOS NMOS CMOS Voltage Scaling Data (Moore) Memory Microprocessor Kilo Xtor 1µm 100nm 10nm Mega Xtor Pwr Eff Scaling Giga Xtor New Nano- structures Beyond CMOS? Spin based? Molecular? Other? Tera Xtor Through Innovation Source: Intel

33 SoC for Integration of Similar Technologies L2I Cache Fuse Branch Unit L1I Cache Bus Arbiter HPW ALAT L2D Cache Bus Logic CLK Floating Point Pipeline Control L1D Cache Integer Datapath L3 Tag Charge Rationing Unit Bus I/O Bus I/O Bus I/O L3 Cache L3 Cache Datapath Source: Intel

34 Key Messages Systems/platform focus drives increased requirements for silicon and packaging Making the right choice between on-chip and in/on package integration is critical to cost effective solutions Moore s s Law is the engine for continued growth Silicon is ideal for homogenous integration Packaging is ideal for heterogeneous integration

35 Convergence Increases Silicon Usage and Need for System in Package Solutions Communications Computing Memory Package z x y System in Packaging Mips & Mbit / milliwatt & millimeter 3 At the Right Cost

36 SiP Value Proposition Form factor Reduces total component volume TTM of new features New features into products sooner Flexibility for customer differentiation System cost Integration should reduce system cost Customer ease of use Ease of sourcing Fewer board spins Focused validation Integration of highly valued elements into a smaller form factor that delivers new capabilities to the end user sooner and at a lower cost

37 Many Options for SiP Multi-Chip Package Wire-Bonded Stacked Die Flash DRAM CPU CPU, DRAM, or? Logic Source: Intel

38 3D Package Stacking Many Possible Configurations Intel Folded Stacked Chip Scale Package Source: Intel

39 3D Silicon Stacking Wafer Die Top Thin Wafer Bottom Wafer Logic, Memory, or? Logic Source: Intel

40 SiP Provides Flexibility to Integrate Varied Functions and Technology Memory-Memory Logic-Memory Stacked Packaging Logic & Memory Advanced Interconnect Logic, Memory, RF Complex Systems Silicon cap wafer Cap Material MEMS IC IC Active substrate with integrated MEMS, passives, and HD Vias Other Devices Source: Intel

41 Conclusions Systems/platform focus drives increased requirements for silicon and packaging Making the right choice between on-chip and in/on package integration is critical to cost effective solutions Moore s s Law is the engine for continued growth AND IT IS ALIVE AND WELL Silicon is ideal for homogenous integration Packaging is ideal for heterogeneous integration