Aspects of Computer Architecture

Transcription

1 T V Atkinson, Ph D Senior Academic Specialist Department of Chemistry Michigan State University East Lansing, MI Table of Contents List of Tables...3 List of Figures...3. Introduction Why should Chemists care about this mateial? How can we characterize the people who use computers? By the Type of Use By frequency of use of a particular program or facility By level of expertise for a given program or facility Number Systems Range of Numbers Converting Between Different Moduli Binary to/from Hexadecimal Binary to/from Octal Signed Integers Sign/Magnitude One's Complement Two's Complement Floating Point Numbers Useful Tables of Numbers Powers of Two Character Codes Six Bit Character Codes ASCII Character Codes ANSI Character Codes Unicode Character Codes Logic Single Bit Logic Truth Tables Multibit Logic Examples Gates and Latches Simple Computer Digital Buses A Simple Example A 4-Bit Bus An 8-Bit Bus System A Simple Input/Output System...43 November 2,

2 List of Tables A More Complete I/O Bus Architecture Reads Writes Post Office (Programmers) Model of Computing Uses of collections of n binary bits Instruction Sets Addressing Operation An Example Computer Registers Instruction format Instruction Set An Example Program Example Program An Example Application of Hardware and Software Sample Program Computer Architecture Taxonomy Special Buses Coprocessors Multiple I/O buses Problems Examples Multiple Processors Disk Drives General Architecture Disk Format Mapping Sectors into Logical Blocks Figures of Merit for a Disk Combinations of Disks Combinations of Simple Disks Memory Utilization Boot Straps Simple Typical of Modern Machines with a Volatile Executive Machines with a ROM based Operating System Memory Systems Increasing Performance Concurrent Tasks Tasks are completely independent Pipelines (Tasks are somewhat independent) Cache Direct Memory Access (DMA) Programmed I/O (Example: reading a block of data) Asynchronous I/O (Interrupt Structures) Interrupt Structure... 7 November 2,

3 List of Tables DMA I/O (Example: Write a block to disk) Memory Management Introduction Motivations for Memory Management Software solutions Chaining Overlaying Hardware/Software Solutions Bank Switching Bank Switching (Partial) Segmentation Paging Virtual Memory Memory Protection Value of a Particular Computing Environment Measurement of Performance Benchmarks CISC vs RISC Main Attributes of RISC...34 List of Tables Table Number Formats...7 Table 2 Symbol Definitions...8 Table 3 Powers of Table 4 Counting in Different Moduli...2 Table 5 to in Multiple Moduli...2 Table 6 Six Bit Character Codes...25 Table 7 ASCII Character Codes...26 Table 8 ASCII Control Characters...27 Table 9 ANSI Character Set...28 Table UNICODE Character Codes...3 Table Logic Truth Tables...3 Table 2 Logic Examples...3 Table 5 Disks: Mapping Physical Sectors into Logical Blocks...86 Table 6 Disks: Example Drives...87 Table 7 Powers of 2 (Abbreviated)...98 Table 8 Representative Examples of DRAM Chips...99 Table 9 Representative Examples of SIMMS... List of Figures Figure Intel Number Representations...6 Figure 2 Intel Floating Point Storage...7 Figure 3 Intel Integer Storage...8 November 2,

4 List of Figures Figure 4 Generic Gate, Switch, and Latch...33 Figure 6 Von Neumann Model of Computer...35 Figure 7 Strobe...37 Figure 8 A Digital Bus with Three Devices...37 Figure 9 A -Bit Bus with Three Devices (Equivalent Schemat)...37 Figure Timing - Transfer Contents of A () to C...38 Figure Timing - Transfer Contents of A () to C...39 Figure 2 4-Bit Bus...4 Figure 3 Simple 8-Bit Bus and Slave Register...4 Figure 4 - Simple 8-Bit Bus and Master Register...42 Figure 5 Simple 8-Bit Bus and Master Register...43 Figure 6 Simple 8-Bit Bus and Master Register...43 Figure 7 Simple I/O Bus: Bus Master...45 Figure 8 Simple I/O Bus: Slave...46 Figure 9 Simple I/O Bus: Slave (Continued)...47 Figure 2 Post Office Model of Computing...5 Figure 2 Bit Byte Word Relationship...55 Figure 22 Laser Experiment...64 Figure 23 Laser Experiment Interface (software View)...66 Figure 24 Laser Experiment Timing (microseconds)...7 Figure 25 Special Memory Bus...72 Figure 26 Special CPU Bus...73 Figure 27 Floating Point CoProcessor I...73 Figure 28 Complex I/O...74 Figure 29 Complex I/O: An Example...75 Figure 3 Multiple Processors: Very Loosely Coupled...77 Figure 3 Multiple Processors: Loosely Coupled...78 Figure 32 Multiple Processors: Parallel...79 Figure 33 Multiple Processors: Connection Topologies...79 Figure 34 Generalized Drive (Cross Section...8 Figure 35 Head Positioners...8 Figure 36 Generalized Controller...82 Figure 37 Track Sector Layout: CAV...83 Figure 38 Track Sector Layout: CLV...84 Figure 39 Track Skew - Interleave...85 Figure 4 Disk System Strategies...88 Figure 4 Disk Groupings - Raid...9 Figure 42 Disk Groupings - Raid...9 Figure 43 Disk Groupings - Raid Alternative...9 Figure 44 Disk Groupings - Raid Figure 45 Disk Groupings - Raid Figure 46 Memory Utilization...93 Figure 47 Boot Strapping...94 Figure 48 Front Panel Emulator...96 Figure 49 Booting a ROM Based OS...97 November 2,

5 Figure 5 Concurrent Tasks...2 Figure 5 Concurrent Tasks (Partial Dependence)...3 Figure 52 Cache and RAM Disk...4 Figure 53 Memory Cache Controller...4 Figure 54 Program I/O...6 Figure 55 DMA Example...9 Figure 56 Program Exceeds Memory Available... Figure 57 Memory Limited Programming (Chaining)...3 Figure 58 Memory Limited Programming (Overlaying)...4 Figure 59 Overlaying (Memory Layout)...5 Figure 6 Memory Management...6 Figure 6 Bank Switching: Mapping...7 Figure 62 Bank Switching: Memory Space...8 Figure 63 Bank Switching (Partial)...9 Figure 64 Bank Switching (Partial): Memory Spaces...2 Figure 65 Bank Switching(Partial): Mapping...2 Figure 66 Segmentation: Mapping...22 Figure 67 Segmentation: Memory Spaces...23 Figure 68 Paging: Mapping...24 Figure 69 Paging: Memory Spaces...25 Figure 7 Paging: Page Table...25 Figure 7 Paging: An Example...28 Figure 72 Virtual Memory: Page Table...29 Figure 73 Virtual Memory: An Example...3 Figure 74 Common Sections...32 Figure 75 Memory Protection...33 November 2,

6 Introduction. Introduction.. Why should Chemists care about this mateial?. Typically, the chemistry professionals will encounter many different computer environments during their careers. 2. We (want to, need to, have to) use computers to do our work and have fun..2. How can we characterize the people who use computers?.2.. By the Type of Use. Application user 2. Operator 3. System manager 4. Application programmer 5. System programmer 6. Hardware developer 7. Software maintainer 8. Hardware maintainer 9. Hardware and software documentor. User support.2.2. By frequency of use of a particular program or facility. Occasional 2. Frequent.2.3. By level of expertise for a given program or facility. Novice 2. Versed 3. Expert/wizard/guru November 2,

7 Number Systems 2. Number Systems An integer is represented in our system of writing by a string of symbols, digits, ( d i ) from the set {,, 2, b-} as shown below where "b" is the base of the representation. number L d d d b dndn 2 Numerically, the above notation represents the following sum. number = n di i= b i As an example, the following are different representations of the same number. number = = 2662 = 496 = A3B Fractional numbers can also be represented. number d d 2 L d m + d m number = m i= i d i b The following are different representations of the same numbers. number number number =. = 4. = 5. = =. = 2. = 25. = =. = 7. = 75. =. C The general notation is as follows where "s" is the sign of the number and may be though of as being either + or -. number sd2dd. d d 2L d m+ d m i number = s d b i= n i Scientific notation can be generalized as follows. In the following "sm" is the sign of the mantissa, "se" is the sign of the exponent, and "B" is a symbol characteristic of the base. number sd d d. d d Ld m+ d mbse enen L eee number = s i b bs n n m d i e i= m j= e j b j m November 2,

8 Number Systems 2.. Range of Numbers A given modulus, b, and a fixed number, n, of digits can express bn numbers that range from to bn -. For example, in base, 5 digits can represent numbers from to For base 2, 6 digits can represent (26) numbers from to Converting Between Different Moduli Conversion of a number from one power of two modulus to another power of two modulus is fairly simple and very useful. The following discussion will assume unsigned integers that can be expressed in 6 binary digits (bits). number b 5 b 4 b 3 b 2 b b b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b b number = b5 2 + b4 2 + b3 2 + b2 2 + b 2 + b 2 + b9 2 + b b 2 + b 2 + b 2 + b 2 + b 2 + b 2 + b 2 + b Binary to/from Hexadecimal Notice that the terms can be grouped in subsets of 4 as follows. number = ( b5 2 + b4 2 + b3 2 + b2 2 ) + ( b 2 + b 2 + b9 2 + b8 2 ) ( b 2 + b 2 + b 2 + b 2 ) + ( b 2 + b 2 + b 2 + b 2 ) Various powers of two can be factored out of the individual groups of 4 terms. number = ( b5 2 + b4 2 + b3 2 + b2 2 ) 2 + ( b 2 + b 2 + b9 2 + b8 2 ) ( b 2 + b 2 + b 2 + b 2 ) 2 + ( b 2 + b 2 + b 2 + b 2 ) Realizing that 2 4 = 6, the above can be transformed as follows. number = ( b5 2 + b4 2 + b3 2 + b2 2 ) 6 + ( b 2 + b 2 + b9 2 + b8 2 ) ( b 2 + b 2 + b 2 + b 2 ) 6 + ( b 2 + b 2 + b 2 + b 2 ) The traditional decimal number system (base = ) has the ten symbols (,, 2, 3,4, 5, 6, 7, 8, 9). The hexadecimal system (base = 6) does not have a corresponding traditional set of 6 symbols. The set (,, 2, 3,4, 5, 6, 7, 8, 9,A,B, C, D, E, F) has been adopted November 2,

9 Number Systems Binary Hexadecimal Decimal A B C 2 D 3 E 4 F 5 6 The factors of the powers of 6 can be replaced with the symbols h i 3 2 number = h 6 + h 6 + h 6 + h 6 number hhhh Thus, the binary number has been converted to the corresponding hexadecimal number with out any excessive arithmetic. Conversion of a hexadecimal number to the corresponding binary number is the inverse process. November 2,

10 Number Systems As an example the following binary number will be converted to hexadecimal. First, the binary number is grouped into sets of 4 bits. number number = = 2 2 Then, each set of four bits is replaced with the corresponding hexadecimal symbol. The number can then be regrouped. number number = A B C 6 = ABC 6 As a second example the following hexadecimal number will be converted to binary. number number = = C73 6 C 73 6 Each hexadecimal symbol is then replaced with the corresponding set of four binary bits. The number can then be regrouped. number number = 2 = Binary to/from Octal In this case the terms in the binary representation are grouped into groups of three terms. number = ( b5 2 ) + ( b4 2 + b3 2 + b2 2 ) ( b 2 + b 2 + b9 2 ) + ( b8 2 + b7 2 + b6 2 ) ( b 2 + b 2 + b 2 ) + ( b 2 + b 2 + b 2 ) Now factor the appropriate power of two out of each group. number = ( b5 2 ) 2 + ( b4 2 + b3 2 + b2 2 ) ( b 2 + b 2 + b9 2 ) 2 + ( b8 2 + b7 2 + b6 2 ) ( b 2 + b 2 + b 2 ) 2 + ( b 2 + b 2 + b 2 ) Given that 2 3 = 8, the following transformation is made November 2,

11 Number Systems number = ( b5 2 ) 8 + ( b4 2 + b3 2 + b2 2 ) ( b 2 + b 2 + b9 2 ) 8 + ( b8 2 + b7 2 + b6 2 ) 2 2 ( b 2 + b 2 + b 2 ) 8 + ( b 2 + b 2 + b 2 ) The coefficients of the powers of 8 can be replaced by the octal symbols defined below Binary Octal Decimal number = o 8 + o 8 + o 8 + o 8 + o 8 + o 8 number o 4 o 3 o 2 o o As an example the following binary number will be converted to octal. First, the binary number is grouped into sets of three bits. number number = = 2 2 Then each set of three bits is replaced with the corresponding octal symbol. The number can then be regrouped. November 2,

12 Number Systems number number = = The inverse operation will serve as a second example. The following octal number will be converted to binary. Begin by separating the octal symbols. number = number = Each octal symbol is then replaced with the corresponding set of three binary bits. The number can then be regrouped. number number = 2 = Signed Integers A set of n binary bits, b n-, b n-2,, b, b, may also be used to represent a signed integer. Three different representations have been used Sign/Magnitude This representation uses one bit to represent the sign of the number. The most significant bit is used for the sign bit. b s = b n- = for a positive number. b s = b n- = for a negative number. The absolute value of the number is placed in the remaining bits as an unsigned integer. Examples, using 6 bit numbers: November 2,

13 Number Systems Signed Sign/Magnitude Representation Number Binary Oct Dec Hex FFF FFFF One's Complement This representation again uses the most significant bit to represent the sign of the number. b n- = b s = for a positive number. b n- = b s = for a negative number. The absolute value of the number to be represented has to be less than 2 n- -. Convert the absolute value of the number to a binary number of n bits. Since the number is less than 2 n- -, the sign bit, b s = b n-, will be zero. If the number being converted is negative, invert all n bits. Notice that the sign bit will be appropriate. As an example convert the number 6 to one's complement. 2 = 6 = 3C 6 Convert absolute value to binary. Now convert -6 to one's complement. Finished. 2 = 6 = 3C 6 Convert absolute value to binary. 2 = = FFC3 6 Invert all bits. Done Further examples, using 6 bit numbers: November 2,

14 Number Systems Signed One's Complement Representation Number Binary Oct Dec Hex FFFE FFF FFFF Two's Complement This representation again uses the most significant bit to represent the sign of the number. b s = b n- = for a positive number. b s = b n- = for a negative number. Again, the absolute value of the number to be represented has to be less than 2 n- -. Convert the absolute value of the number to a binary number of n bits. Since the number is less than 2 n- -, the sign bit, b s = b n-, will be zero. If the number being converted is negative, invert all n bits. Then add one to the resultant. Notice that the sign bit will be appropriate. This representation avoids the problem of + and - of the one's complement representation. This is now the typical representation used. As an example convert the number 6 to two's complement. 2 = 6 = 3C 6 Convert absolute value to binary. Now convert -6 to two's complement. Finished. 2 = 6 = 3C 6 Convert absolute value to binary. 2 = = FFC3 6 Invert all bits. 2 Add one. 2 = = FFC4 6 Done. November 2,

15 Number Systems Further examples, using 6 bit numbers: Signed Two's Complement Number Binary Oct Dec Hex FFFF FFE FFF At this point, a few simple aritmetic examples might be useful. These examples use two's complement arithmetic. First there is the binary addition table for adding two binary single bit numbers (A + B). Multiple bit additions are performed bit by bit with the adding in of any carry from the previous position A B A+B Carry Add the binary equivalents of -6 and Carry 2 = 6 = 3C 6 First number 2 = -6 = FFC4 6 Second number 2 6 Sum November 2,

16 Number Systems 2.4. Floating Point Numbers This section summarizes the formats of several of the data types supported by Intel. The value of a floating point number is given by the following S E Bias ( ) ( )F number = 2 where S is the sign bit, E is the exponent, F is the fractional mantissa, and BIAS is an integer that varies with representation and is listed below for these particular representations Word Integer S 5 Short Integer S 3 Long Integer S 6 3 Single Precision S biased exp. 3 fraction 2 3 Double Precision S 6 3 biased exp. fraction 5 2 Extended Precision S biased exponent I fraction Figure Intel Number Representations Microprocessors, page 4-59, Intel Corporation, Literature Sales, PO Box 764, Mt. Prospect IL , 99. November 2,

17 Number Systems Table Number Formats Data Type Bits Significant Digits Range Word Integer X Short Integer x 9 X 2 x 9 Long Integer x 8 X 9 x 8 Single Precision x -37 X 3.37 x 38 Double Precision x -37 X.67 x 38 Extended Precision x X.2 x 4932 A+7 A+6 7 S M S E L S E M S F A+9 A+8 A+7 A+6 7 S I M S E M S F L S E A+5 A+5 7 A+4 A+4 A+3 A+2 S L S E M S E M S F A+3 A+2 A+3 A+2 A+ A+ A+ A+ L S F A+ L S F A+ L S F Single Precision Double Precision Figure 2 Intel Floating Point Storage Extended Precision November 2,

18 Number Systems A+7 7 S M S B A+6 A+5 A+3 7 S M S B A+4 A+3 A+ A+ 7 S M S B L S B A+2 A+ A+ L S B A+2 A+ A+ L S B Word Intege r Short Intege r Figure 3 Intel Integer Storage Long Intege r Table 2 Symbol Definitions Symbol Description A Base address of the stored number S Sign of the number ( = positive, = negative) MSB Most Significant Bit of integer LSB Least Significant Bit of Integer MSF Most Significant Bit of fraction LSF Least Significant Bit of fraction MSE Most Significant Bit of the exponent LSE Least Significant Bit of the exponent Bias Single 27 (7F 6 ) Double 23 (3FF 6 ) Extended 6383 (3FFF 6 ) November 2,

19 Number Systems 2.5. Useful Tables of Numbers Powers of Two Table 3 Powers of 2 n DEC OCT HEX Common Name K K K K K K K K K K M or Meg M or 2Meg M or 4Meg M or 8Meg M or 6Meg M or 32Meg M or 64Meg M or 28Meg M or 256Meg M or 52Meg G or Gig G or 2Gig G or 4Gig November 2,

20 Number Systems The above table contains the values of the first 32 powers of 2 expressed in base (decimal or DEC), base 8 (octal or Oct), and base 6 (hexadecimal or Hex). The right most column of the table contains the common names often given to the corresponding quantities. This nomenclature is an artifact of the computer industry which early on chose to use the short hand name one K to represent the much longer and more appropriate name One thousand twenty four, etc. Table 4 Counting in Different Moduli DEC Binary OCT HEX Items being counted * ** *** **** ***** ****** ******* 8 8 ******** 9 9 ********* 2 A ********** 3 B *********** 2 4 C ************ 3 5 D ************* 4 6 E ************** 5 7 F *************** 6 2 **************** 7 2 ***************** ****************** ******************* ******************** ********************* ********************** *********************** ************************ ************************* A ************************** B *************************** C **************************** D ***************************** 3 36 E ****************************** 3 37 F ******************************* ******************************** ********************************* November 2,

21 Number Systems Table 5 to in Multiple Moduli DEC BIN BIN OCT BIN HEX DEC A 3 B 2 4 C D E F A B C D E F November 2,

22 Number Systems DEC BIN BIN OCT BIN HEX DEC A B C D E F A B C D E F A B C D E F November 2,

23 Number Systems DEC BIN BIN OCT BIN HEX DEC A B C D E F A B C D E 57 6F November 2,

24 Number Systems DEC BIN BIN OCT BIN HEX DEC A B C D E F FFFA FFFB FFFC FFFD FFFE FFFF November 2,

25 Character Codes 3. Character Codes 3.. Six Bit Character Codes These codes were used in the early days of computing when memory and bandwidth was very expensive. Notice that there are only upper case characters. Table 6 Six Bit Character Codes Char Octal Dec Hex Char Octal Dec space A! B " C # D $ E % F & G ' H 8 8 ( I 9 9 ) J 2 A * A K 3 B B L 4 2 C, C M 5 3 D D N 6 4 E E O 7 5 F / F P Q R S T U V W X Y Z A : A [ B ; B \ C < C ] D = D ^ 36 3 E > E 37 3 F? F November 2,

26 Character Codes 3.2. ASCII Character Codes Table 7 ASCII Character Codes Character Octal Dec Hex Char Octal Dec Hex Char Octal Dec Hex Char Octal Dec Hex <NULL> ` <SOH>! A 65 4 a <STX> " B b <ETX> # C c <EOT> $ D d <ENQ> % E e <ACK> & F f <BEL> ' G g <BS> 8 8 ( H h <HT> 9 9 ) I i <LF> 2 A * A J A j A <VT> 3 B B K B k B <FF> 4 2 C, C L C l C <CR> 5 3 D D M D m D <SO> 6 4 E E N E n 56 6E <SI> 7 5 F / F O F o 57 6F <DLE> P p <DC> Q q <DC2> R r <DC3> S s <DC4> T t <NAK> U u <SYN> V v <ETB> W w <CAN> X x <EM> Y y <SUB> A : A Z A z A <ESC> B ; B [ B { B <FS> C < C \ C C <GS> D = D ] D } D <RS> 36 3 E > E ^ E ~ E <US> 37 3 F? F _ F DEL F November 2,

27 Character Codes Table 8 ASCII Control Characters <NUL> Null <SOH> Start of heading <STX> Start of text <ETX> End of text <EOT> End of transmission <ENQ> Enquiry <ACK> Acknowledge <BEL> Bell (audible signal) <BS> Backspace <HT> Horizontal Tabulation <LF> Line Feed - go to new line <VT> Vertical tabulation <FF> Form Feed - go to new page <CR> Carriage return - return to left margin <SO> Shift out <SI> Shift in <DLE> Data link escape <DC> Device Control - XON <DC2> Device Control 2 <DC3> Device Control 3 - XOFF <DC4> Device Control 4 <NAK> Negative Acknowledge <SYN> Synchronous idle <ETB> End of transmission block <CAN> Cancel <EM> End of medium <SUB> Substitute <ESC> Escape <FS> File Separator <GS> Group Separator <RS> Record Separator <US> Unit Separator <DEL> Delete November 2,

28 Character Codes 3.3. ANSI Character Codes Table 9 ANSI Character Set The ANSI character set consists of the ASCII character set plus the set of characters in this table. Char Octal Dec Hex Char Octal Dec Hex Char Octal Dec Hex Char Octal Dec Hex A À 3 92 C à E A Á 3 93 C á E A2  C2 â E2 ƒ A3 à C3 ã E A4 Ä C4 ä E A5 Å C5 å E A6 Æ C6 æ E A7 Ç C7 ç E7 ˆ A8 È 3 2 C8 è E A9 É 3 2 C9 é E9 Š A ª AA Ê CA ê EA B «253 7 AB Ë CB ë EB Œ C AC Ì CC ì EC D AD Í CD í ED E AE Î CE î EE F AF Ï CF ï EF B Ð D ð F ± B Ñ D ñ F ² B2 Ò D2 ò F ³ B3 Ó D3 ó F B4 Ô D4 ô F µ B5 Õ D5 õ F B6 Ö D6 ö F B D F B8 Ø D8 ø F ¹ B9 Ù D9 ù F9 š A º BA Ú DA ú FA B» BB Û DB û FB œ C ¼ BC Ü DC ü FC D ½ BD Ý DD ý FD E ¾ BE Þ DE þ FE Ÿ F BF ß DF ÿ FF November 2,

29 Character Codes 3.4. Unicode Character Codes In order to deal with the many character sets used in the written languages of the world, the Unicode Character Codes were developed over the last decade. The standard allows 8, 6, or 32 bit definitions of the characters. The following URL contains the details, and there are many, of the Unicode effort. The table below contains the lay out of the Unicode Character Sets. # Unicode Character Database # Copyright (c) Unicode, Inc. # For terms of use, see # For documentation, see UCD.html November 2,

30 Character Codes Table UNICODE Character Codes 7F Basic Latin 8 FF Latin- Supplement 7F Latin Extended-A 8 24F Latin Extended-B 25 2AF IPA Extensions 2B 2FF Spacing Modifier Letters 3 36F Combining Diacritical Marks 37 3FF Greek and Coptic 4 4FF Cyrillic 5 52F Cyrillic Supplement 53 58F Armenian 59 5FF Hebrew 6 6FF Arabic 7 74F Syriac 78 7BF Thaana 9 97F Devanagari 98 9FF Bengali A A7F Gurmukhi A8 AFF Gujarati B B7F Oriya B8 BFF Tamil C C7F Telugu C8 CFF Kannada D D7F Malayalam D8 DFF Sinhala E E7F Thai E8 EFF Lao F FFF Tibetan 9F Myanmar A FF Georgian FF Hangul Jamo 2 37F Ethiopic 3A 3FF Cherokee 4 67F Unified Canadian Aboriginal Syllabics 68 69F Ogham 6A 6FF Runic 7 7F Tagalog 72 73F Hanunoo 74 75F Buhid 76 77F Tagbanwa 78 7FF Khmer 8 8AF Mongolian 9 94F Limbu 95 97F Tai Le 9E 9FF Khmer Symbols D D7F Phonetic Extensions E EFF Latin Extended Additional F FFF Greek Extended 2 26F General Punctuation 27 29F Superscripts and Subscripts 2A 2CF Currency Symbols 2D 2FF Combining Diacritical Marks for Symbols 2 24F Letterlike Symbols 25 28F Number Forms 29 2FF Arrows 22 22FF Mathematical Operators 23 23FF Miscellaneous Technical F Control Pictures F Optical Character Recognition FF Enclosed Alphanumerics F Box Drawing F Block Elements 25A 25FF Geometric Shapes 26 26FF Miscellaneous Symbols 27 27BF Dingbats 27C 27EF Miscellaneous Mathematical Symbols- A 27F 27FF Supplemental Arrows-A 28 28FF Braille Patterns F Supplemental Arrows-B FF Miscellaneous Mathematical Symbols- B 2A 2AFF Supplemental Mathematical Operators 2B 2BFF Miscellaneous Symbols and Arrows 2E8 2EFF CJK Radicals Supplement 2F 2FDF Kangxi Radicals 2FF 2FFF Ideographic Description Characters 3 33F CJK Symbols and Punctuation 34 39F Hiragana 3A 3FF Katakana 3 32F Bopomofo 33 38F Hangul Compatibility Jamo 39 39F Kanbun 3A 3BF Bopomofo Extended 3F 3FF Katakana Phonetic Extensions 32 32FF Enclosed CJK Letters and Months 33 33FF CJK Compatibility 34 4DBF CJK Unified Ideographs Extension A 4DC 4DFF Yijing Hexagram Symbols 4E 9FFF CJK Unified Ideographs A A48F Yi Syllables A49 A4CF Yi Radicals AC D7AF Hangul Syllables D8 DB7F High Surrogates DB8 DBFF High Private Use Surrogates DC DFFF Low Surrogates E F8FF Private Use Area F9 FAFF CJK Compatibility Ideographs FB FB4F Alphabetic Presentation Forms FB5 FDFF Arabic Presentation Forms-A FE FEF Variation Selectors FE2 FE2F Combining Half Marks FE3 FE4F CJK Compatibility Forms FE5 FE6F Small Form Variants FE7 FEFF Arabic Presentation Forms-B FF FFEF Halfwidth and Fullwidth Forms FFF FFFF Specials 7F Linear B Syllabary 8 FF Linear B Ideograms 3F Aegean Numbers 3 32F Old Italic 33 34F Gothic 38 39F Ugaritic 4 44F Deseret 45 47F Shavian 48 4AF Osmanya 8 83F Cypriot Syllabary D DFF Byzantine Musical Symbols D DFF Musical Symbols D3 D35F Tai Xuan Jing Symbols D4 D7FF Mathematical Alphanumeric Symbols 2 2A6DF CJK Unified Ideographs Extension B 2F8 2FAF CJK Compatibility Ideographs Supplement E E7F Tags E EEF Variation Selectors Supplement F FFFFF Supplementary Private Use Area-A FFF F Supplementary Private Use Area-B November 2,

31 Logic 4. Logic 4.. Single Bit Logic Truth Tables Table Logic Truth Tables A B A B A B A.AND.B A + B A.OR.B A B A.AND.B A + B A.OR.B A B A.AND.B A + B A.OR.B Notice that the following are true. A B = A + B A + B = A B 4.2. Multibit Logic Examples Table 2 Logic Examples Expression Binary Decimal Octal Hexidecimal A B A.AND.B A.OR.B.NOT.A FFFE.NOT.B FFFE Expression Binary Decimal Octal Hexidecimal A ABCD B A.AND.B A.OR.B ABCD.NOT.A NOT.B FFFF November 2,

32 Logic Expression Binary Decimal Octal Hexidecimal A ABCD B FFFF A.AND.B ABCD A.OR.B FFFF.NOT.A NOT.B Expression Binary Decimal Octal Hexidecimal A ABCD B FF A.AND.B BC A.OR.B AFFD.NOT.A NOT.B FF Expression Binary Decimal Octal Hexidecimal A FF B A.AND.B A.OR.B FF.NOT.A FF.NOT.B Expression Binary Decimal Octal Hexidecimal A FF B A.AND.B A.OR.B FF.NOT.A FF.NOT.B FFEC Expression Binary Decimal Octal Hexidecimal A FF B A.AND.B A.OR.B FF.NOT.A FF.NOT.B CCCC Expression Binary Decimal Octal Hexidecimal A FF B A.AND.B A.OR.B FF98.NOT.A FF.NOT.B November 2,

33 Gates and Latches Expression Binary Decimal Octal Hexidecimal A FF B A.AND.B A.OR.B FF3.NOT.A FF.NOT.B FFEC Expression Binary Decimal Octal Hexidecimal A FF B A.AND.B A.OR.B FF33.NOT.A FF.NOT.B CCCC 5. Gates and Latches Error! Reference source not found. and Table 3 Generic Gate, Switch, Latch - Definitions define three generic devices, which may be either analog or digital devices. The devices are three port devices with two inputs, e.g. e in and a control signal e GC, e SC, or e LC, and one output, e out. The devices have two states. The control signal determines in which of the two states the device is at a particular time. GateSwitchLatch_.cdr 7-Oct-24 e in Gate e out e in Switch e out e in Latch e out e GC e SC e LC Switch Control e SC Figure 4 Generic Gate, Switch, and Latch The gate nomenclature comes from the barnyard gate, i.e. when the gate is open, the animals can go through the gate; when the gate is closed then animals can not go through the gate. The latch is basically a camera, i.e. it captures a snapshot of the value of e in at the time of the transition of e LC and holds it for later inspection. November 2,

34 Gates and Latches Table 3 Generic Gate, Switch, Latch - Definitions Device State Control Signal Behavior Gate Open e GC = Open e out = e in Closed e GC = Closed e out = constant ( also may be disconnected) Switch Closed e SC = Closed e out = e in Open e SC = Open e out = constant Latch Follow e LC = Follow e out = e in Latched e LC = Latch e out = e in (t = Latch Follow ) Error! Reference source not found. illustrates a derivative combination, the tri-state gate which has the characteristics shown in Table 4 Tri-State Gate - Definition Definition. This device derives its name from the fact that there are essentially three states: high, low, and disconnected. Such devices have great utility when constructing a bus, i.e. a party line or shared communication facility. TriStateGate_.cdr -Oct-24 e in Gate Switch e out e GC e SC Figure 5 Tri-State Gate Table 4 Tri-State Gate - Definition Definition Switch Control Gate Control Behavior e SC = Closed e GC = Open e out = e in e SC = Closed e GC = Closed e out = constant e SC = Open e GC = Open Device is disconnected from the following circuitry. e SC = Open e GC = Closed Device is disconnected from the following circuitry. November 2,

35 Simple Computer These generic concepts have widespread application in both digital and analog electronics. The remainder of this document will explore how these devices are implemented and applied in the digital domain. 6. Simple Computer A common model of a simple computer is the "Von Neumann" model shown in Figure 6. This model consists of three types of functional units, Central Processing Unit (CPU), Memory, and I/O units of which there can be varying numbers in any real application. The CPU contains four subsystems, the Command Decoder, CD, arithmetic logical unit, ALU, Control Panel, and the CPU register set. The CPU is the engine that does the computational work of the system. The Command Decoder fetches, interprets, and causes the execution of the program instruction steps. The ALU performs, under the control of the CPU, the integer arithmetic and logical operations required by the program instructions. The I/O units provide the interface between the computing system and the outside world. The Control Panel allows the operator of the system to perform certain basic operations such as starting and stopping operation, and examining and changing aspects of the system. The functional units are connected by the I/O bus, a communication facility that allows information to be moved among the various functional units. CEM 838 CPU.cdr 7-Apr-2 T V Atkinson Department of Chemistry Michigan State University Panel Control Registers Arithmetic Logical Unit Command Decoder CPU Memory External Device I/O Controller # External Device I/O Controller # Control Bus Address Bus Data Bus Model of Simple Computer Figure 6 Von Neumann Model of Computer 6.. Digital Buses I/O buses are actually collections of parallel digital (binary) electrical signals that are simultaneously observed and/or manipulated by multiple functional units. Hence, a bus is an example of a "party-line" communication channel with the connected subsystems being peers on November 2,

36 Simple Computer the channel. Information is typically moved between two of the participants on the bus. The I/O bus is usually considered to consist of three sub buses (Control, Address, and Data) (See Figure 6). The Data Bus is a collection of signals that contain the data being moved from one subsystem to the other. The Address Bus allows the participants on the bus to identify which subsystem is sending the information and which subsystem is receiving the information. The Control Bus is the collection of signals required to affect the transfer of information from one participant to the other. The states of the control signals, i. e. the Control Bus, are defined one of the subsystems called the Bus Master. In simple computers, only the CPU can be master. In more complicated architectures, other functional units can be bus master. There have been many computer buses, e.g. Unibus, Qbus, New Bus, VMEbus, XT bus, ISA (ATBUS), SCSI, EISA, Micro Channel Architecture (MCA) bus, VESA, PCI, IEEE 488. One bus varies from another in the following ways.. Collection of signals (number and definition) 2. Technology used to implement electronics connected to the bus, e.g. TTL, CMOS, ECL, Optical elements (for optical fiber buses). 3. Physical implementation: connectors, conductors, etc. 4. Speed and timing relationships 5. Sequences of events required to effect transfers of information A Simple Example The simple logic devices, i.e. And, Or, Nor, Nand, gates and latches, discussed in the section on logic are the atomic elements of digital devices. Real digital devices, e.g. computers, are, in essence, collections of such elements. As mentioned above, these collections are typically organized into subsystems. One issue is how information is moved from one subsystem of the device to another. Figure 8 and Figure 9 illustrates one such mechanism, a simple digital bus that connects three single bit devices (registers) A, B, and C. In this example, GC a, LC a, GC b, LC b, GC c, and LC c are control signals. L a, L b, and L c are the contents of the registers. As an example, the following steps are performed to move the contents of Device A (L a ) to Device C (L c ).. All control signals are in the off state, i.e. LC i are in the LATCHED state and GC i are in the CLOSED state. The bus is idle. 2. Assert GC a (GC a = OPEN). BUS is now equal to L a 3. Strobe LC c as in Figure 7. L c now equals L a. Transfer is complete. November 2,

37 Simple Computer 4. Deassert GC a (Gate A is CLOSED.) Bus is now idle. Latch Follow Latch Figure 7 Strobe Figure shows the timing of events that would be required to move the contents of Register A into Register C. The contents of A is assumed to be at the beginning, the contents of B and C are. The timing sequences for the control signals GC a, LC a, GC c, and LC c are generated by some outside intelligence (often called the Bus Master). Figure is a similar example with the contents of A being. BusA.cdr 23-Oct-22 T V Atkinson Department of Chemistry Michigan State University A Bus B C Latch L a Gate G a Latch L b Gate G b Latch L c Gate G c LC a GC a LC b GC b LC c GC c Figure 8 A Digital Bus with Three Devices BusA.cdr 2-Oct-22 T V Atkinson Department of Chemistry Michigan State University Bus A B C Latch L a Gate G a Latch L b Gate G b Latch L c Gate G c LC a GC a LC b GC b LC c GC c Figure 9 A -Bit Bus with Three Devices (Equivalent Schemat) November 2,

38 Simple Computer Digital Timing Diagrams GCc LCc Closed Latch Follow Gc Lc GCa Closed Open LCa Latch Ga La Bus Time (millisec) Figure Timing - Transfer Contents of A () to C November 2,

39 Simple Computer Digital Timing Diagrams GCc LCc Closed Latch Follow Gc Lc GCa Closed Open LCa Latch Ga La Bus Time Figure Timing - Transfer Contents of A () to C A 4-Bit Bus Figure 2 illustrates how three 4-bit devices would be connected with the simple bus discussed above. Notice that the control signals are the same for all bits of a device. Thus all four bits of information are eached moved as described above at the same time. November 2,

40 Simple Computer BusA.cdr 2-Oct-22 T V Atkinson Department of Chemistry Michigan State University Data Bus Latch L a Gate G a Latch L b Gate G b Latch L c Gate G c LC a GC a LC b GC b LC c GC c Data Bus Latch L a Gate G a Latch L b Gate G b Latch L c Gate G c LC a GC a LC b GC b LC c GC c Data Bus 2 Latch L a2 Gate G a2 Latch L b2 Gate G b2 Latch L c2 Gate G c2 LC a GC a LC b GC b LC c GC c Data Bus 3 Latch L a3 Gate G a3 Latch L b3 Gate G b3 Latch L c3 Gate G c3 LC a GC a LC b GC b LC c GC c Device A Device B Device C 4-Bit Bus Figure 2 4-Bit Bus November 2,

41 Simple Computer An 8-Bit Bus System Figure 3 and Figure 4 illustrate the next level of complexity. Here, there are two types of devices, i. e. the Master Register and any number of Slave Registers. All registers are 8-bit devices. In this system, the Master Register is involved in all transfers. Reading a register is defined as a transfer that copies information from that register to another. Writing a register is defined as a transfer that copies information from another to that register. The Address Bus is a set of signals that identify which Slave Register is involved in the transfer. Decoder is a function that monitors the Address Bus and goes true when the address of that Slave Register is on the Address Bus. The Control Bus, i.e. STROBE and WRITE are signals generated by the Bus Controller which is described here. RegisterSlave.cdr 7-Dec-23 T V Atkinson Department of Chemistry Michigan State University Address of REGISTER i a i,n- a i,2 a i, Decoder REGISTER i Selected a n- a 2 a a WRITE REGISTER i LC b b b 2 b 3 b 4 b 5 b 6 WRITE STROBE GC STROBE LC DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA DATA GC b 7 READ REGISTER i Address Bus (n signals) Control Bus Data Bus Register i Simple 8-Bit Bus and Slave REGISTER Figure 3 - Simple 8-Bit Bus and Slave Register November 2,

42 Simple Computer RegisterMaster.cdr 7-Dec-23 T V Atkinson Department of Chemistry Michigan State University Bus Controller WRITE MASTER REGISTER LC a n- a 2 a a b b b 2 b 3 b 4 b 5 WRITE STROBE GC STROBE LC DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA DATA b 6 b 7 GC READ MASTER REGISTER Address Bus (n signals) Control Bus Data Bus Master Register Simple 8-Bit Bus and MASTER REGISTER Figure 4 - Simple 8-Bit Bus and Master Register Transfers of information from Slave Register i to the Master Register are accomplished with the following sets of steps.. The address of Slave Register i is placed on the Address Bus. The output of Decoder i goes true. 2. WRITE is set low. 3. STROBE LC and STROBE GC are strobed as indicated in Figure 5. This gates the contents of Slave Register i onto the Data Bus. The contents of the Data Bus are latched into Master Register. November 2,

43 Simple Computer Follow STROBE LC Latch Latch Open STROBE GC Closed Closed A Simple Input/Output System Figure 5 - Simple 8-Bit Bus and Master Register Figure 6 illustrates how one could implement a one bit register that outputs information from the digital device and a one bit register that would input information to the device from the outside world. BusIO.cdr 2-Oct-22 T V Atkinson Department of Chemistry Michigan State University Bus A B Latch L a Gate G a Latch L b Gate G b GC a LC b GC b LC a GC in Gate Digital Device Outside World L out valid L out GC in GC in Figure 6 Simple 8-Bit Bus and Master Register November 2,

44 Simple Computer A More Complete I/O Bus Architecture Figure 7, Figure 8, and Figure 9 depict a fairly simple but more complete bus architecture that illustrates a number of points. This particular architecture was constructed for illustration and does not match any particular computer system. November 2,

45 Simple Computer BUS 24-JAN-993 T V Atkinson Dept of Chemistry Michigan State University Gated Driver Master Address Register GC Master Address Bus ( m signals) Address Bus ( n signals) WRITE STROBE DATA Gated Driver GC Slave Address Register Bus Control Logic Bus Control Decoder ADDRESSi WRITE REGISTER i to BIT, BIT2,... LC Latch to outside world Gated Driver GC to BIT, BIT2,... READ REGISTER i BIT A Simple I/O Bus (Master) Master Register i Figure 7 Simple I/O Bus: Bus Master November 2,

46 Simple Computer Figure 8 illustrates a slave device on the bus. BUS 2 -JUL-995 T V Atkinson Dept of Chemistry Michigan State University Decoder ADDRESS Address Bus ( n signals) WRITE STROBE DATA WRITE REGISTER LC Latch to BIT, BIT2... to outside world Write Only Gated Driver from outside world GC to BIT, BIT2,... READ REGISTER 2 Decoder ADDRESS2 Read Only Decoder ADDRESS3 WRITE REGISTER 3 to BIT, BIT2,... LC Latch to outside world Gated Driver GC to BIT, BIT2,... READ REGISTER 3 BIT A Simple I/O Bus (Slave) Read/Write Figure 8 Simple I/O Bus: Slave November 2,

47 Simple Computer Figure 9 shows the remaining bits of the representative registers forming the slave devices. BUS 3 24-JAN-993 T V Atkinson Dept of Chemistry Michigan State University WRITE REGISTER to BIT3, BIT4,... LC Latch to outside world LC Latch to outside world DATA DATA2 Write Only READ REGISTER 2 to BIT3, BIT4,... GC Gated Driver from outside world GC Gated Driver from outside world Read Only WRITE REGISTER 3 to BIT3, BIT4,... LC Latch to outside world LC Latch to outside world Gated Driver Gated Driver READ REGISTER 3 GC BIT BIT2 GC to BIT3, BIT4,... Read/Write A Simple I/O Bus (Slave continued) Figure 9 Simple I/O Bus: Slave (Continued) November 2,

48 Simple Computer Reads For this simple architecture, a "read" is the transfer of information from the slave register to the master register.. The idle state of the bus consists of STROBE being. As a result, all WRITE REGISTER j and READ REGISTER j AND gates will have an output of. The states of all other signals are of no consequence. 2. Bus Master Bus Control Logic gates the address of the referenced master register onto the Master Address Bus. The output of the decoder for the appropriate Master Register will now change to, indicating selection of that register. 3. Bus Master Bus Control Logic gates the address of the referenced slave register onto the Address Bus. The output of the decoder for the appropriate slave register will now change to, indicating selection of that register. 4. Bus Master Bus Control Logic gates a, i.e. do a read, onto the WRITE line. This will set up the gating of the selected slave register onto the Data bus and the latches of the selected master register to follow the state of the Data bus. 5. A time delay occurs that allows all the above signals to settle and the various decoding to take place. 6. The Bus Master Bus Control Logic gates a onto the signal STROBE. With STROBE now one, all inputs will be one for the WRITE REGISTER i AND gate of the addressed master register and the READ REGISTER j AND gate for the addressed slave register. Thus, these two signals will go to. All other AND gates will have at least one, resulting in outputs of those gates remaining at. Thus, the gate control signal (GC) for the gated driver for each of the bits of the addressed slave register will go to and these signals will be gated onto the Data bus. Simultaneously, the latch control signal (LC) for the latches for each of the bits of the addressed master register will go to and these latches will begin to follow the corresponding bits on the Data bus. 7. A time delay occurs that allows all the above signals to settle. 8. The Bus Master Bus Control Logic gates a onto the signal STROBE. As a result, all WRITE REGISTER j and READ REGISTER j AND gates have an output of. Thus, the latches for the selected master register change to the latched state, freezing the contents of the selected slave register into the master register. The signals from the slave register are also removed from the Data bus. The bus is now in the idle state. November 2,

49 Simple Computer Writes For this simple architecture, a "write" is the transfer of information from the master register to the slave register.. The idle state of the I/O bus consists of STROBE being. As a result, all WRITE REGISTER j and READ REGISTER j AND gates will have an output of. The states of all other signals are of no consequence. 2. Bus Master Bus Control Logic gates the address of the referenced master register onto the Master Address Bus. The output of the decoder for the appropriate master register will now change to, indicating selection of that register. 3. Bus Master Bus Control Logic gates the address of the referenced slave register onto the Address Bus. The output of the decoder for the appropriate slave register will now change to, indicating selection of that register. 4. Bus Master Bus Control Logic gates a, i.e., do a write, onto the WRITE line. This will set up the gating of the selected master register onto the Data bus and the latches of the selected slave register to follow the state of the Data bus. 5. A time delay occurs that allows all the above signals to settle and the various decoding to take place. 6. The Bus Master Bus Control Logic gates a onto the signal STROBE. With STROBE now one, all inputs will be one for the WRITE REGISTER i AND gate of the addressed slave register and the READ REGISTER i AND gate for the addressed master register. Thus, these two signals will go to. All other AND gates will have at least one, resulting in outputs of those gates remaining at. Thus, the gate control signal (GC) for the gated driver for each of the bits of the addressed master register will go to and the master register contents will be gated on to the Data bus. Simultaneously, the latch control signal (LC) for the latches for each of the bits of the addressed slave register will go to and these latches will begin to follow the corresponding bits on the Data bus. 7. A time delay occurs that allows all the above signals to settle. 8. The Bus Master Bus Control Logic gates a onto the signal STROBE. As a result, all WRITE REGISTER j and READ REGISTER j AND gates have an output of. Thus, the latches for the selected slave register change to the latched state, freezing the contents of the selected master register into the slave register. The signals from the master register are also removed from the DATA bus. The bus is now in the idle state. November 2,