Melon S3 FPGA Development Board Product Datasheet

Size: px

Start display at page:

Download "Melon S3 FPGA Development Board Product Datasheet"

Ernest Grant
5 years ago
Views:

Melon S3 FPGA Development Board Product Datasheet The Melon S3 FPGA is open-source, expandable development board perfect for the learning digital circuit design and prototyping of your unique ideas.

1 Melon S3 FPGA Development Board Product Datasheet The Melon S3 FPGA is open-source, expandable development board perfect for the learning digital circuit design and prototyping of your unique ideas. You can customize the capabilities of the FPGA with snap-on 40-pin "Raspberry Pi HAT". There are several shields in the market offers a low cost module that can be purchased off the shelf. These shield modules can be plugged directly to the Melon S3 FPGA board for the creation of powerful embedded and digital system applications. At its heart, the Melon S3 has a Xilinx Spartan 3E 500K FPGA chip from Xilinx. providing a plentiful amount of digital logic to quickly get your prototyping off the ground and WiFi SoC: WROOM-02 certified module (FCC, CE, TELEC, Wi-Fi Alliance, and SRRC) with an onboard antenna. The WROOM-02 comes with a firmware which will allow you to download a (.bit) file over WiFi to the FPGA without having to buy a JTAG programmer.

Once the board is powered on, the WROOM-02 will configures the FPGA from the internal 4MB flash memory.

2 Espressif System's WROOM-02 (ESP8266) is a low cost SoC: WiFi+Microcontroller, A 32- bit low power micro-controller with CPU clock of 80MHz, 50KB of user available RAM and an external 4MB of Flash memory with a full WiFi front-end (both as client and access point). Once the board is powered on, the WROOM-02 will configures the FPGA from the internal 4MB flash memory. After the FPGA is successfully configured the WROOM-02 enters slave mode. This allows your FPGA designs to talk to the microcontroller, giving you develop the MCU + FPGA for co-processing application.

Specification Xilinx Spartan 3E FPGA (PQG208) - 500K gates, (73Kb Distributed RAM, 4 Digital Clock Manager (DCM), 20 Multipliers (18x18), 360 Kb Block RAM) Onboard USB-UART (Silicon Labs) CP2104 for

3 Specification Xilinx Spartan 3E FPGA (PQG208) - 500K gates, (73Kb Distributed RAM, 4 Digital Clock Manager (DCM), 20 Multipliers (18x18), 360 Kb Block RAM) Onboard USB-UART (Silicon Labs) CP2104 for Configuration, Debugging and Power. WiFi 2.4GHz SoC-WROOM-02, 32-bit MCU (Arduino Compatible) Clock 80MHz, 50KB RAM, Integrated TCP/IP protocol stack. Flash 4MB SPI Flash which is 1MB for MCU Firmware and 3MB for FPGA Bit space. 8 Users LEDs 4 DIP Switch user buttons 1 Reset button Onboard FPGA clock 50MHz GPIOs 56 PINs 3.3V Tolerant - 40 PINs x2 (Raspberry Pi 40 PINs Compatible) JTAG Port (Optional for Program/Debugging) Board Front Side Position Reference Description 1 JTAG Port Optional for Programing & Debugging using Xilinx ISE Software 2 FPGA Xilinx FPGA Spartan 3E 500K

4 3 LEDs x8 LED (Green) 4 DIP SWs x4 DIP Switches 5 Pwr LED 3.3V Power LED (Red) 6 7 XSTOP Jumper Status LED FPGA code will STOP if Jumper added (Size 2.5"), Using this jumper as a FPGA stop pin (No jumper by default) User define LED (Green) at GPIO15 of ESP MCU WiFi SoC (ESP8266) Flash 4MB Version 9 Oscillator ABRACON 50 MHz onboard oscillator (50ppm) 10 LED1 User define LED (Green) at GPIO2 of ESP8266, This LED will be flashing during upload firmware to ESP Reset Btn Reset Button for ESP TX/RX Jumper TX/RX Jumper of ESP8266 and USB CP2104 (Size 2.0"), Refer Jumper setting section 13 USB IC CP2104 UART to USB IC 14 USB LED USB Plug-in LED Status (VUSB) 15 Done LED FPGA Status LED if.bit file downloaded to FPGA without error 16 VIN 5V External Power supply +5V can powered the board from this pin TX/RX LEDs USB Connector TX/RX LED Status of USB IC (CP2104) USB Connector for +5V input for powered the board or Debug/Programming port for ESP8266

Bottom Side (Solder pad jumper for the users are willing to use with Raspberry Pi Position Reference 1 2 3 (JP2) RPi 3.

5 Bottom Side (Solder pad jumper for the users are willing to use with Raspberry Pi Position Reference (JP2) RPi 3.3 V Jumper HSWAP Jumper (JP1) Rpi 5V Jumper Description Solder pad Jumper is "Open" by Default, But once the Melon FPGA and Raspberry Pi Shields stacked together at P1 Port, You can powered RPi Shields board at 3.3V P1:1,P1:17 (3V3_RP) by using the power VUSB (5V) or VIN (5V) from Melon FPGA board, by setting the Jumper "Closed (Soldered)", Refer schematic for more information Set the default state of FPGA Pins, Solder pad jumper is "Open"= Pull-down (by Default), Set the jumper pad to "Closed, (Soldered)"= All the FPGA pins are Pull-Up. Solder pad Jumper is "Open" by Default, But once the Melon FPGA and Raspberry Pi Shields are stacked together at P1 Port, if you want to powered RPi Shields P1:2,P2:4 (5V_RP) by using the power VUSB (5V) or VIN (5V) from Melon FPGA board, by setting the Jumper "Closed (Soldered)", Refer schematic for more information

TX/RX Jumper Setting "ESP-PROGRAM" TX/RX Jumper is set to "Open" by Default, In order to re-program ESP8266 firmware, The both jumpers (TX/RX) need to be inserted (Closed).

6 TX/RX Jumper Setting "ESP-PROGRAM" TX/RX Jumper is set to "Open" by Default, In order to re-program ESP8266 firmware, The both jumpers (TX/RX) need to be inserted (Closed). USB TX/RX and ESP TX/RX pins also routed to FPGA refer the diagram below, You can writed the FPGA code to set jumper internally. In this case you can re-program the ESP8266 firmware without any jumpers. Pin Definition

7 Port1 FPGA Pin Number (Pxx) vs Connector Pins (RPi shileds can be connected to this port) Description Pin Number Pin Number Description +3V3_RP Using +5V_RP Using with with RPi shields RPi shields need to need to set 1 2 set solder pad solder pad jumper at bottom jumper at bottom side side P V_RP Using with RPi shields need to set solder pad jumper at bottom side P Ground P P47 Ground 9 10 P42 P P40 P Ground P P35 +3V3_RP Using with RPi shields need to set solder pad P34 jumper at bottom side P Ground P P30 P P28 Ground P25 P P23 P Ground

P19 31 32 P18 P16 33 34 Ground P15 35 36 P12 P11 37 38 P9 Ground 39 40 P8 Port 2: FPGA Pin Number (Pxx) vs Connector Pins

8 P P18 P Ground P P12 P P9 Ground P8 Port 2: FPGA Pin Number (Pxx) vs Connector Pins Description Pin Number Pin Number Description +3V V P V P Ground P P151 Ground 9 10 P147 P P145

P144 13 14 Ground P139 15 16 P140 +3V3 17 18 P138 P137 19 20 Ground P133 21 22 P132 P129 23 24 P128 Ground 25 26 P127

9 P Ground P P140 +3V P138 P Ground P P132 P P128 Ground P127 P P123 P Ground P P119 P Ground P P113 P P109 Ground P108

In addition, The Melon S3 FPGA can be programmed using established development tools, such as Xilinx ISE (Free: Webpack), MATLAB HDL Coder/HDL Verifier and National Instruments LabVIEW FPGA Toolkit.

10 In addition, The Melon S3 FPGA can be programmed using established development tools, such as Xilinx ISE (Free: Webpack), MATLAB HDL Coder/HDL Verifier and National Instruments LabVIEW FPGA Toolkit. Lastly, MCU ESP8266 (WROOM-02) can be programmed using Arduino IDE. 1.ISE WebPACK design software is the industry s only FREE, fully featured front-to-back FPGA design solution. ISE WebPACK is the ideal downloadable solution for FPGA and offering HDL synthesis and simulation, implementation, device fitting, and JTAG programming. ISE WebPACK delivers a complete, front-to-back design flow providing instant access to the ISE features and functionality at no cost. Xilinx has created a solution that allows convenient productivity by providing a design solution that is always up to date with error-free downloading and single file installation. After generated *.bit file you can then upload it to the Melon S3 FPGA via WiFi. 2.With HDL Coder and HDL Verifier, you can automate much of the time-consuming and error-prone work of implementing algorithms on FPGAs. You can quickly evaluate alternative architectures, optimize fixed-point settings, generate HDL code, perform IP core generation and prototype on an FPGA. Additionally, you can use generated HDL code for your ASIC implementation. Using HDL Coder and HDL Verifier, you can: Perform HDL design iterations in minutes rather than weeks Automatically generate HDL code for FPGA programming or ASIC prototyping and design Verify that your HDL design implementation matches the system design specification Program Xilinx and Intel FPGAs from MATLAB and Simulink

by providing a highly integrated development environment, a large ecosystem of IP libraries, a

11 3.The NI LabVIEW FPGA Module extends the LabVIEW graphical development platform to target FPGAs. LabVIEW FPGA gives developers the ability to more efficiently and effectively design complex systems by providing a highly integrated development environment, a large ecosystem of IP libraries, a high-fidelity simulator, and debugging features. *More information please visit

designs to talk to the microcontroller, giving you

12 4.with Arduino IDE you can write your own firmware running in MCU (WROOM-02), This allows your FPGA designs to talk to the microcontroller, giving you develop the MCU + FPGA for coprocessing application. Schematics

13 Download PDF Schematic & PCB Firmware (Arduino C/C++) Xilinx ISE support files Xilinx ISE project examples LabVIEW FPGA (2014) Examples 8 bit Counter Example 8 bit Counter with Raspberry Pi Interface rrypi_linx

QWaveSystems / Melon_S3_FPGA

QWaveSystems / Melon_S3_FPGA A Open-source Hardware : WiFi (ESP8266) FPGA Development Kit Edit Add topics 201 commits 1 branch 0 releases 1 contributor Branch: master New pull request Create new file Upload