New Initiatives and Technologies Brighten Embedded Software Radio

Transcription

1 New Initiatives and Technologies Brighten Embedded Software Radio Embedded Tech Trends January 2018 Rodger Hosking Pentek, Inc.

2 Sensor Open System Architecture (SOSA) Consortium of Air Force, Navy, Army, DoD, Industry, & other Government Agencies Develop & Adopt Open Systems Architecture standards for C4ISR Common multi-purpose backbone architecture for Radar, EO/IR, SIGINT, EW, & communications Platform affordability, rapid fielding, re-configurability & overall performance Re-purposing of hardware/software/firmware Business/acquisition practices to foster innovation, industry engagement and competition 2

3 Modular Open RF Architecture - MORA CERDEC s evolving definition of converged open architecture for open interfaces to enable rapid insertion of new capabilities, interoperability, and a reduced SWaP footprint MORA extends the U.S. Army s VICTORY architecture for vehicle electronics Share hardware and software components among C4ISR/EW capabilities Allow technology refresh to keep pace with threats while improving reliability & robustness Support interoperability requirements and facilitate transition planning Permit innovative unplanned capabilities for quick-reaction future-proofing Reduce developmental and acquisition costs through greater commercial competition 3

4 VITA 49 Virtual Digital RF Transport Protocol (VRT) Traditional radios used stovepipe architectures Application specific, custom analog RF and IF signal cabling & switching Proprietary digital links and switches Each system was dedicated to a specific radio application VITA 49 VRT Flexible RF transceivers deliver and accept digitized signals using a standardized packet protocol Switching, routing and distribution is done across a COTS digital network Metadata, control, and status packets are linked to the digital signal packets Configurable for a wide range of applications using the same hardware Stove-pipe architecture using proprietary analog and digital interfaces Proprietary IF Distribution IF Digitizers Low Band Tuners Sg a ocesso s Signal Processors IF Digitizers RF Distribution Set On Tuners Sg a ocesso s Signal Processors High Band Tuners Proprietary IF Distribution IF Digitizers Digital Recorders Analog Links Digital Links IF Recorders gta eco de s VRT Open architecture using VRT interfaces over a COTS digital network Signal Processors Low Band Transcievers Signal Processors RF Distribution Set On Transcievers Digital Network Signal Processors High Band Transcievers Digital Recorders Analog Links VRT Enabled Digital Links 4

5 Initial Evolution from VICTORY to MORA VICTORY Shared Processing Unit Gigabit Ethernet Switch Radio Heads Antennas RF / IF Power Amps VITA 49 Radio Data MORA High-Speed Bus - 10 GbE VICTORY Data Bus - GbE RF Cables Power Bus Software Defined Radio Boards RF Distribution Unit 5

6 Later Evolution from VICTORY to MORA VICTORY Shared Processing Unit Gigabit Ethernet Switch Radio Heads Antennas RF / IF Power Amps Data Acquisition Modules s + s VITA 49 Radio Data VITA 49 Radio Data MORA High-Speed Bus - 10 GbE VICTORY Data Bus - GbE RF Cables Power Bus Software Defined Radio Boards RF Distribution Unit 6

7 MORA Component Requirements for Board Vendors OpenVPX Architecture compliant with applicable VITA standards Interchangeable system components for reconfiguration and new technology insertion 10 GbE interfaces for digitized C4ISR data signals (evolving to 40 & 100 GbE) 1 GbE interfaces for control and status VITA 49 protocol engines for C4ISR data Runtime reconfigurable via processor software and FPGA IP Scalable channel count, bandwidth, and processing power Synchronous acquisition across multiple RF channels and multiple chassis Backplane I/O when possible for copper and optical digital, timing, and RF signals 7

8 New Technologies and Standards Serve the Mission Kintex UltraScale FPGAs 5520 DSP Engines Over a million logic cells Lower power and cost Fast and Converters Photo: Xilinx VITA 57.4 FMC+ HSPC connector with 80 LVDS + 24 serial lanes HSPCe connector adds 8 more serial lanes Gigabit serial rates to 28 Gbaud Photo: Samtec Sample Rates to 6.4 GS/sec High density low power Photo: Texas Inst VITA 49.2 Radio Transport ANSI/VITA Approved in 2017 JESD204B Device Interfaces Reduces number of PCB traces by 12 times Receive & Transmit Protocols Control & Status Protocols Precision Timing Protocols Supports ADCs & DACs to 6 GS/sec and higher Comprehensive Infrastructure 8

9 New Technologies and Standards Serve the Mission VITA 66.x Optical Backplane VPX I/O Several full- and halfwidth blind-mate optical connector types Provides high bandwidth data paths between boards and chassis VITA 67.x Coax Backplane VPX I/O Several multi-position connector types up to 12 coax signals RF signal bandwidths to 40 GHz Eliminates front panel signal cables Photo: Elma Photo: SV Microwave VITA 65.0 & VITA 65.1 OpenVPX Major enhancements reflect widespread use and adoption of OpenVPX New Card, Slot and Backplane Profiles Radial Backplane Clock distribution ensures precision timing and synchronization across boards Provision for a 100 MHz reference clock New definitions of combinations of VITA 66.x optical and VITA 67.x coaxial backplane I/O Photo: TE Connectivity 9

10 5983 UltraScale 3U VPX JadeFX FMC Carrier Inherits Jade XMC Architecture Navigator BSP and FDK Tools Powerful Kintex UltraScale FPGA KU060, KU085, or KU115 x8 PCIe Gen 3 for 8 GB/sec peak rate 4x Gigabit Serial User I/O 16-pairs LVDS User I/O Optional Precision GPS Receiver 10 MHz Freq ReF + 1 PPS for Time Stamp Flywheel mode with OCXO accuracy Antenna Precision GPS Recvr 1 PPS Ctrl/Status 9 GB DDR4 SDRAM 2400 MHz Data Transfer Rate Optional VITA 66.4 Optical Backplane 12 GB/sec full duplex data transfers FMC or FMC+ Site VITA 57.1 HPC: 160 LVDS + 8x GTH VITA 57.4 HSPC: 160 LVDS + 24x GTH VITA 49.2 Protocol Engine 10 MHz (to FMC) 1 PPS (to FMC) VITA 57.1 HPC FMC SITE VITA 57.4 HSPC FMC+ SITE 160 LVDS 8x (KU060) 24x (KU115) JadeFX Config Port PCIe GTH Kintex UltraScale FPGA KU060, KU085 or KU115 LVDS LVDS VITA 49 GTH GTH Kintex Ultra Scale FPGA PCIe Gen 3 x8 10/40 GbE Optical I/F 66.4 FLASH 1 Gbit VPX x8 PCIe Gen3 VPX 4x Gigabit Serial I/O 32 LVDS User I/O VPX (1/2) 80 DDR4 SDRAM 5 GB 32 DDR4 SDRAM 4 GB 12x Gigabit Serial I/O OPTICAL TRANSCEIVERS VPX (1/2) 12 optical lanes VITA U VPX BACKPLANE 10

11 2-Channel Wideband Analog I/O FMC Module Two 3.0 GHz 14-bit s Texas Inst ADC32RF45 3 db input BW: 3.2 GHz Two Digital Downconverters Two 2.8 GHz 16-bit s Texas Inst DAC39J84 Two Digital Upconverters Timing Bus Generator Programmable Clock Synthesizer phaselocked to 10 MHz input reference Synchronization across multiple boards Full triggering, gating and time-stamping 2-Channel wideband transceiver or transponder for communication and radar Model 3320 FMC Module Sample Clk / Reference Clk In PPS/ Gate/Trigger In VCXO TIMING BUS GENERATOR Clock / Sync Gate / PPS Clock Clock RF XFORMR 3.0 GHz 14-bit & DDC RF In RF XFORMR 3.0 GHz 14-bit & DDC RF In RF XFORMR 2.8 GHz 16-bit & DUC RF Out RF XFORMR 2.8 GHz 16-bit & DUC RF Out FMC Clock Kintex Ultra Scale FPGA with VITA 49 JadeFX Model 5983 PCIe Gen 3 x8 10/40 GbE Optical I/F 66.4 FMC CONNECTOR 11

12 Addressing MORA Requirements Today OpenVPX 3U Chassis SSD SDRAM BIOS FLASH Single Board Computer Intel CPU Linux or Windows 1 GbE 1 GbE PCIe x4 RS232 USB PCIe x4 PCIe x4 Power PCIe Power Bus 1 GbE VICTORY Data Bus FMC RF Cables Clock FMC Kintex Ultra Scale FPGA with VITA 49 JadeFX Model 5983 PCIe Gen 3 x8 10/40 GbE Optical I/F 66.4 PCIe Power Bus MORA High-Speed Bus RF Cables Clock Kintex Ultra Scale FPGA with VITA 49 JadeFX Model 5983 PCIe Gen 3 x8 10/40 GbE Optical I/F 66.4 Power PCIe Power Bus MORA High-Speed Bus 12

13 MORA Remote Data Acquisition Modules Take 1 VICTORY Shared Processing Unit VITA 49 Radio Data MORA High-Speed Bus - 10 GbE VICTORY Data Bus - GbE Power Bus Software Defined Radio Boards Gigabit Ethernet Switch Radio Heads Antennas RF / IF Power Amps Data Acquisition Modules s + s VITA 49 Radio Data RF/IF RF/IF Clock SSD SDRAM BIOS FLASH FMC Single Board Computer Kintex Ultra Scale FPGA with VITA 49 Intel CPU Linux or Windows JadeFX Model 5983 PCIe Gen 3 x8 10/40 GbE Optical I/F Performs analog/digital conversion for transmit and receive signals Includes digital up and down conversion, synchronization, and time stamping VITA 49.2 engine But, requires two boards 1 GbE Victory 1 GbE Data Bus 1 GbE PCIe x4 RS232 USB PCIe x4 PCIe x PCIe Power Power MORA Data Bus 10 GbE 13

14 UltraScale + SoM 3U VPX JadeFX FMC Carrier Adds System-on-Module (SoM) to Model 5983 SoM ARM Cortex-A9 System Controller Linux OS 1 GbE Port for Control and Status 1x PCIe Link to Kintex UltraScale Dedicated 1 GB DDR3 SDRAM Non-volatile SD Memory Card USB Ports for peripherals SoM Functions/Benefits Replaces SBC for many applications Complete Sub-system Reconfigures the FPGA over GbE Control and Monitoring over GbE GbE USB ARM Cortex-A9 System-on- Module SoM SD Memory Card Antenna Precision GPS Recvr 1 PPS Ctrl/Status 64 DDR3 SDRAM 1 GB x1 PCIe Gen2 VPX Config Port FLASH 1 Gbit 10 MHz (to FMC) 1 PPS (to FMC) GTH VPX 4x Gigabit Serial I/O FMC Clock Kintex UltraScale FPGA KU060, KU085, or KU115 LVDS 32 LVDS User I/O VPX (1/2) Kintex Ultra Scale FPGA JadeFX + SoM PCIe 80 DDR4 SDRAM 5 GB ARM Linux USB, RS232 10/40 GbE Optical I/F VITA 57.1 HPC FMC SITE VITA 57.4 HSPC FMC+ SITE LVDS GbE 160 LVDS 32 DDR4 SDRAM 4 GB 3U VPX BACKPLANE 66.4 VITA 49 GTH 8x (KU060) 24x (KU115) GTH 12x Gigabit Serial I/O OPTICAL TRANSCEIVERS VPX (1/2) 12 optical lanes VITA

15 MORA Remote Data Acquisition Modules Take 2 FMC VICTORY Shared Processing Unit VITA 49 Radio Data MORA High-Speed Bus - 10 GbE VICTORY Data Bus - GbE Power Bus Software Defined Radio Boards Gigabit Ethernet Switch Radio Heads Antennas RF / IF Power Amps Data Acquisition Modules s + s VITA 49 Radio Data RF/IF RF/IF Clock Kintex Ultra Scale FPGA with VITA 49 JadeFX + SoM PCIe ARM Linux USB, RS232 10/40 GbE Optical I/F GbE 66.4 Power Complete stand-alone, single board solution for MORA data acquisition Local ARM processor implements API for simplified programming and control FPGA is reconfigurable via 1 GbE Interchangeable front ends for flexibility in channel count and signal bandwidth Range of FPGA devices to match horsepower requirements GbE and 10 GbE network switches allow virtually any number of nodes Victory Data Bus 1 GbE MORA Data Bus 10 GbE 15

16 MORA Component Requirements for Board Vendors OpenVPX Architecture compliant with applicable VITA standards Interchangeable system components for reconfiguration and new technology insertion 10 GbE interfaces for digitized C4ISR data signals (evolving to 40 & 100 GbE) 1 GbE interfaces for control and status VITA 49 protocol engines for C4ISR data Runtime reconfigurable via processor software and FPGA IP Scalable channel count, bandwidth, and processing power Synchronous acquisition across multiple RF channels and multiple chassis Backplane I/O when possible for copper and optical digital, timing, and RF signals FMC Clock Kintex Ultra Scale FPGA with VITA 49 JadeFX + SoM PCIe ARM Linux USB, RS232 10/40 GbE Optical I/F GbE

17 Thank You!! Questions?? 17