COPious-PXIe. Single Board Computer with HPC FMC IO Site DESCRIPTION APPLICATIONS SOFTWARE V0.2 01/17/17

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1 V0.2 01/17/17 Single Board Computer with HPC FMC IO Site FEATURES Combines an Zynq Z7045 SoC with FMC IO module in a compact, stand alone design Powerful, dual, floating-point ARM A9 CPU performance 8HP PXIe form factor Self-bootable, stand-alone operation Able to operate diskless and headless Runs Linux applications Configurable IO uses standard HPC FMC IO module. Add anything from RF receivers to industrial control modules. IO site (VITA 57) deliver up to 6 GB/s to PL memory, 2 GB/s to PS memory IEEE-1588 or GPS-disciplined clock from backplane routed to FMC module PLL matrix Supports Innovative FMC IO module features for private data channels, triggering and timing features USB 2.0, 1 Gb Ethernet, emmc, SPI, RS232 ports Boots Linux from on-board emmc device 12V +/- 5% DC operation APPLICATIONS Embedded instrumentation Remote, autonomous IO Lab/Factory automation Distributed data acquisition SOFTWARE Linux/Windows -host compatible Runs Petalinux on Core 0 Runs standard desktop applications Eclipse C++ Developers Kit supporting IO integration and customization Device drivers, example software and support applets supplied for all peripherals DESCRIPTION is a user-customizable, PXIe plug-in card that includes two A9 CPU cores. Linux runs in core 0 to provide Ethernet, USB and disk connectivity while core 1 runs real-time stand-alone applications. is compatible with Innovative's wide assortment of ultimate-performance FMC modules. With its modular IO, scalable performance and easy to use CPU core architecture, the reduces time-tomarket while providing the performance you need. Distributed Data Acquisition Put the at the data source and reduce system errors and complexity. Available IEEE1588 network or GPS-synchronized timing, triggering and sample control is available for remote IO. Limitless expansion via multiple nodes. Uniquely customizable An HPC FMC site for IO, userprogrammable FPGA for IO interfaces, on-board GbE and USB. Stand-alone, autonomous operation with precision-timed sampling on FMC data. Autonomous Boots Petalinux and user application code from flash when installed in a standard 8HP PXIe chassis slot. Ready for embedded operation. 12V +/- 5% DC-Only Operation - Perfect for offloading real-time applications and functionality within a larger PXIe test environment. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Innovative Integration products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Innovative Integration standard warranty. Production processing does not necessarily include testing of all parameters. 01/18/ Innovative Integration phone fax

2 This electronics assembly can be damaged by ESD. Innovative Integration recommends that all electronic assemblies and components circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION Note: Please consult the Carsharp Production Selection Flowchart here to best understand the configuration options for this product. Product Part Number L0 Description - with Zynq Z7Z045 SoC with dual A9 CPU, active heat sink and fan, 2.5 GB DDR2, 32MB Flash, 32 GB emmc, 2x USB 2.0, 10/100/1000 GbE, 1x RS232. Approx 12W consumption. Innovative Integration phone fax of 14

3 Figure 1. Block Diagram Innovative Integration phone fax of 14

4 Figure 2. Zync SoC block diagram Innovative Integration phone fax of 14

5 Isometric view of front bezel, HPC FMC-site and fan-cooled Zynq Z7045 SoC FPGA. Front view of front bezel. Rear view of PXIe backplane connector. Top viewof showing FMC site and fan assembly atop Zynq Z7045 SoC FPGA. Innovative Integration phone fax of 14

6 Standard Features Z7045 SoC CPU Dual ARM Cortex-A9 MPCore. NEON & Single / Double Precision Floating Point for each processor emmc FLASH Drive Capacity 32 GB Type Embedded Flash Use Boot drive or data storage Cache L1: 512KB, L2: 256KB DDR2 Memory 2x 512 MBx16 for PS (CPU) 3x 512 Mbx16 for for PL (Logic) Logic Cells 444K Sample Clock Sources Block Ram KB Trigger Modes DSP Slices 2020 Tranceivers 16 IO Ports USB 1x, USB 2.0, Type A rear panel port UART 1x RS232 GPIO 8 bits, direction is bit-programmable QSFP 1x Aurora, 40 Gbps (bidirectional) Ethernet 1x 10/100/1000 Mbps Timing and Triggering Support Features PXIe Backplane, FMC site Software, PXIe backplane-synchronized, external input Trigger Outputs FMC site (FMC module type dependent) Trigger Inputs 1 SSMC on FMC site Clock input Use as sample clock or FMC Reference; SSMC on FMC site. Module Synchronization Simultaneously across mesh via PPS/matched reference clocks FMC Sites Module Sites 1 Standards VITA 57.1 FMC VITA 20 Conduction cooling Size 69 x 76.5 mm, 10mm mezzanine height CPU Connections FMC Site 0: HPC Innovative Integration phone fax of 14

7 Customization Features FPGA Power Management Xilinx Zynq 7045 SoC FPGA Controls triggering and has 34 pin connections to FMC Mezzanine Memory-mapped Interface to A9 CPU cores FrameWork Logic available for FPGA in VHDL Power Requirements Input Consumption 12V +/- 5% DC Power States Low power states supported including wake features from CPU and LAN Temperature Monitors 2 total : Zync SoC and COPiousPXIe assembly each have a temperature sensor Alarms Software programmable warning and failure levels Over-temp Monitor Disables power supplies Conductive Cooling Conduction cooling supported for assembly includes heat conduction bars on each edge and VITA57 pattern for FMC module Fans Single integrated fan controller Varies according to FMC module requirements 8W: with no FMC Physicals Form Factor PXIe 3U x 8 HP Weight 1500g (est.) Hazardous Materials Lead-free and RoHS compliant MTBF ~42,000 Hours Innovative Integration phone fax of 14

8 ABSOLUTE MAXIMUM RATINGS!Exposure to conditions exceeding these ratings may cause damage! Parameter Min Max Units Conditions Supply Voltage V Operating Temperature 0 60 C Storage Temperature C ESD Rating - 1k V Human Body Model Vibration - 5 g Hz, Class 3.3 per ETSI EN V2.1.2 ( ) Shock - 40 g peak Class 3.3 per ETSI EN V2.1.2 ( ) Non-condensing, forced air cooling required Innovative Integration phone fax of 14

9 Architecture and Features The combines dual ARM A9 CPU cores with an HPC FMC IO module and high-speed connectivity peripherals to create a autonomous signal processing board for a variety of applications. Embedded CPU cores The Zynq Z045 SoC is a dual A9 CPU core combined with user extensible FPGA fabric that provides a real-time computing engine, suitable for high-speed signal processing while consuming minimal footprint and power. Embedded CPU #0 boots into Linux, which provides sophisticated, mature drivers to high performance connectivity peripherals such as the 1 GbE ethernet port, QSFP port, emmc flash memory and USB port. USB storage devices are supported, to support data logging at rates to 480 Mb/s to each device. Embedded CPU core #1 boots a user-written standalone application to perform real-time I/O via the FMC module. This provides optimal, minimal latency interaction with the FMC peripherals and resources, without inducing OS or stack latencies of any kind. The best of both worlds: highperformance connectivity via CPU 0, determinicity and speed via CPU 1. Each A9 CPU core is mapped directly to the FMC module. The CPU bus tightly couples the CPU to the FMC modules and the SoC DMA engines may be used to accelerate I/O, outperforming Innovative's previous generation SBC systems by 2 to 4 times. Bidirectional data transfer rates between logic memory and FMC resources occur at full memory bus rates: 6000 MB/s. The provides familiar core interfaces for expansion and connectivity: Gigabit Ethernet, USB ports, and emmc disk, as well as numerous connectivity interfaces such as RS232 and SPI. Innovative Integration phone fax of 14

10 XP3 Connectors XP3/XJ3 are the XMC PCI Express connectors to the host. Column Row A B C D E F 1 XMC_P15_TX0_P XMC_P15_TX0_N XMC_P15_TX1_P XMC_P15_TX1_N 2 XMC_JTRST_N XMC_MRSTI_N 3 XMC_P15_TX2_P XMC_P15_TX2_N XMC_P15_TX3_P XMC_P15_TX3_N 4 XMC_JTCK 5 XMC_P15_TX4_P XMC_P15_TX4_N XMC_P15_TX5_P XMC_P15_TX5_N 6 XMC_JTMS 7 XMC_P15_TX6_P XMC_P15_TX6_N XMC_P15_TX7_P XMC_P15_TX7_N 8 XMC_JTDI 9 10 XMC_JTDO 11 P15_RX_0_P P15_RX_0_N P15_RX_1_P P15_RX_1_N P15_RX_2_P P15_RX_2_N P15_RX_3_P P15_RX_3_N P15_RX_4_P P15_RX_4_N P15_RX_5_P P15_RX_5_N P15_RX_6_P P15_RX_6_N P15_RX_7_P P15_RX_7_N XMC_RFU PEX_REFCLK0_P PEX_REFCLK0_N Table 1: P15 Signals Innovative Integration phone fax of 14

11 Signal Name Description 1 No Connect. Do not connect any signals (including ground) to these pins 2 Board Ground 3 Carrier +12V power input. If this power is present, onboard power input (J5) must be left unconnected; otherwise the board might be damaged. 4 XMC_P15_TX0_P/XMC_P15_TX0_N to XMC_P15_TX7_P/XMC_P15_TX7_N High-speed transmitter differential pairs. Typically used for PCIe bus (up to 8 lanes) connection, carrier being the host. Signal direction is from the module (module drives these signals). Can be also used in a QSFP high-speed port. 5 XMC_P15_RX0_P/XMC_P15_RX0_N to XMC_P15_RX7_P/XMC_P15_RX7_N High-speed receiver differential pairs. Typically used for PCIe bus (up to 8 lanes) connection, carrier being the host. Signal direction is to the module (module receives these signals). Can be also used in a QSFP high-speed port. 6 PEX_REFCLK0_P/PEX_REFCLK0_N PCIe Reference Clock (differential) from the carrier board. 7 XMC_MRSTI_N PCIe reset signal. 8 XMC_JTRST_N JTAG Reset signal from the carrier. Used as a board master reset on. 9 XMC_JTCK JTAG Clock signal from the carrier. 10 XMC_JTMS JTAG Mode Select signal from the carrier. 11 XMC_JTDI JTAG Data Input signal from the carrier (module input). 12 XMC_JTDO JTAG Data Output signal from the module (module output). 13 XMC_RFU12 Not used, reserved for future use. Table 2: P15 Signal Description Notes: 1. JTAG signals are also available on connector J3, exposed via the front panel bezel. 2. JTAG signals are 3.3V LVCMOS. Innovative Integration phone fax of 14

12 FMC IO Site A single HPC FMC IO module site enables the to be configured with a wide variety of IO personalities. The FMC site is for FPGA mezzanine cards conforming to VITA 57.1 standard, which are 69 x 75 mm modules. The module site is designed to support cooling via convective air FMC Modules for IO flow provided by the PXIe chassis. - Flexible, modular IO Innovative offers FMC IO offering a range of - Industry-standard VITA 57.1 analog performance mated to the high performance - Up to 6000 MB/s transfer rates FPGA computing cores within the Zynq SoC. Innovative's Velocia architecture data packet - Industry-standard, multi-vendor system allows these modules to stream data continuously to Zynq system memory at rates limited only by the memory subsystem making the well suited for real-time control, digital signal processing and applications requiring deterministic, low-latency. Special features supporting all Innovative FMC module are provided in the for simultaneously sampling, triggering and controls. System triggers and matched clocks from an externally-supplied clock or reference provide simultaneously sampling for the two modules. The FMC module site has 66 differential connections plus eight 12.5 Gbps SERDES links to the on-board FPGA, providing ample bandwidth for even the fastest FMC modules. Triggering and Sample Clocks The has unique clocking and triggering features for the FMC module. The site receives two triggers from the application FPGA and two clock inputs through its connector. Innovative modules can use these to support simultaneous sampling and unique trigger scenarios using the application FPGA. Sample clocks for the FMC site can be synchronized using an optional GPS or IEEE-1588 reference or from an external clock input. FMC module PLLs can use either the external clock input or the disciplined clock as a reference. The disciplined clock allows multiple, remote instruments to sample simultaneously and act cooperatively. Position and time data is also available from the GPS when installed. Remote Operation can be operated using Ethernet as a remote computer or embedded instrument. For pure embedded operation, the can operate headless without monitor, keyboard or mouse. The system boots from an onboard QSPI and emmc FLASH, providing reliable operation even in a rugged environment. This provides independence from the PXIe system controller providing greater determinicity, lower latency and application reliability. Application FPGA The Zynq Z7045 provides a large, user-programmable on-chip FPGA which allows the to be customized for many IO functions, such as triggering and control features. This FPGA is memory-mapped peripheral to the Zync SoC CPUs. New functions can added to the system by adding them to the FPGA design. FPGA logic is provided in the FrameWork Logic tools, which includes the standard functionality that can be modified or used as an example. Software Tools Software development tools for the provide comprehensive support application development including device drivers, peripheral configuration and control, and utilities that allow developers to be productive from the start. Software classes provide C++ developers a powerful, high-level interface to the system devices that makes system integration and achieving real-time, high speed data acquisition easier. Innovative Integration phone fax of 14

13 Software for data logging and analysis are provided with every Innovative FMC module. Data can be logged to system memory at full rate or to disk drives at rates supported by the drive and controller. Triggering and sample rate controls are provided to support data acquisition applications without writing code. Innovative software applets include Binview which provides data viewing, analysis and import to MATLAB for large data files. Support for Eclipse C++ is provided. The PetaLinux OS is supported. For more information, the software tools User Guide and on-line help may be downloaded. Logic Tools Customized IO interfaces, triggering and other unique features may be added to the by modifying the FPGA logic. The FrameWork Logic tools provide support for VHDL/Verilog developments. Application logic can be modified by building upon the Innovative components for hardware interfaces and system functions. Each design is provided as a Xilinx Vivado project with VHDL source for top level logic with a modeling test-bench illustrating logic functionality. FMC Modules Plug FMC modules into the to build your custom, PXIe plug-in card. Innovative Integration offers an array of ultra-performance, CPU FMC modules to create your solution. Innovative FMC module families feature analog and digital IO with FPGA computing cores on high performance CPU modules. The FrameWork Logic development tools allow you to design in MATLAB and VHDL and rapidly implement high speed signal processing on the FMC. See the full list of Innovative FMC modules here. Innovative Integration phone fax of 14

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