op nex t Powered by HITACHI

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1 Technical Data (Rev. 0.1, March 28, 2001) TRV5010/5020/5030CN-xx OC-192 Transceiver with MUX/DMUX op nex t Powered by HITACHI All specifications described herein are subject to change without prior notice TRV5010CN-xx: 1310 nm OC192 Transceiver for 2 km application (-/ I64.1) TRV5020CN-xx: 1310 nm OC192 Transceiver for 12 km application (SR-1/ -) TRV5030CN-xx: 1310 nm OC192 Transceiver for 20 km application (IR-1/ S64.1) FEATURES OC-192 ( Gbit/s) Transceiver with MUX/DMUX Transmission length up to 2, 12 and 20 km 1310 nm direct modulated DFB-LD and PIN-PD 16:1 MUX and 1:16 DMUX integrated Compact size (89 x 114 x 18 mm 3 ) with a 300-pin compact connector OIF compliant 622 Mbit/s LVDS logic interface DESCRIPTION General s 10 Gbit/s transceiver module TRV5010/20/30CN-xx enables a dense-port and high-throughput solution in favor of its compact size and low power consumption. The TRV5010/20/30CN-xx modules can be used in various network applications, such as dense wavelength division multiplexing (DWDM) systems, metropolitan area network (MAN) systems and Internet Protocol (IP) switches and routers. The maximum transmission length of TRV5010/20/30CN-xx is 2, 12, and 20 km respectively using a direct modulated (DM) 1310 nm distributed feedback (DFB) laser and PIN photo-diode. The TRV5010/20/30CN-xx is a fully integrated 10 Gbit/s optical transceiver module that consists of a 10 Gbit/s optical transmitter and receiver, a 16:1 MUX with a clock generation circuit, and a 1:16 DMUX with a clock and data recovery (CDR) circuit. The interface to a framer circuit is compliant with OIF standard, which is 16-wide 622-Mbit/s LVDS parallel I/O with the counter-clocking scheme. The module is integrated with a transmitter-reference-clock jitter filter and FIFO in front of MUX. The module size is 89 mm x 114 mm x 18 mm with 300-pin connector. The power consumption is 9.5 W (typical) and power supply voltages are 3.3 V, 5 V and 5.2 V.

2 Block Diagram TxRESET Automatic Temperature Control LsTEMPALM TxDin TxPICLK 16 FIFO 16:1 Mux Laser Driver LDM Optical Output TxMCLK TxPCLK (*1) TxLOCKERR 10 GHz PLL/VCO Automatic Power Control LsPOWMON LsBIASMON TxREFSEL0 155/622 MHz PLL/VCXO LsBIASALM TxREFCLK LsENABLE RxLCKREF RxREFCLK RxDout RxPOCLK 16 1:16 DMUX CDR Post Amplifier Pin-PD Preamplifier Optical Input RxMCLK RxLOCKERR RxLOPMON RxRESET RxREFSEL0: NA RxLOSMON: NA Figure 1 Schematic block diagram of the transceiver module - 2 -

3 Functional Description Data and Clock (1) Transmitter Data Interface No. Symbol Function I/O Logic Remarks 1 TxDin[15:0]P/N Transmitter 16-bit Parallel Input I LVDS Data 2 TxPICLKP/N Transmitter Source Synchronous I LVDS Input Clock for TxDin 3 TxPCLKP/N Transmitter Counter Clock O LVDS TxPCLK Do not care 1/( MHz) TTf TTr 80% 20% TxPICLK Ts Th TxDin[15:0] Data Valid Window Figure 2 Tx Input Timing Diagram 80% 20% TTr, TTf Framer Optical Module 100 Ω TxDin[15:0] LVDS Driver Z= 100 Ω Input Buffer 100 Ω TxPICLK LVDS Driver Z= 100 Ω Input Buffer 100 Ω Input Buffer Z= 100 Ω LVDS Driver TxPCLK Figure 3 Interface to framer IC - 3 -

4 (2) Receiver Data Interface No. Symbol Function I/O Logic Remarks 1 RxDout[15:0]P/ Receiver 16-bit Parallel Output Data O LVDS N 2 RxPOCLKP/N Receiver Synchronous Output Clock for RxDout O LVDS 1/( MHz) RxPOCLK 80% 20% Tcq_min Tcq_max RTf RTr RxDout[15:0] 80% 20% RTr, RTf Figure 4 Rx Output Timing Diagram Framer Optical Module 100 Ω Input Buffer Z= 100 Ω LVDS Driver RxDout[15:0] 100 Ω Input Buffer Z= 100 Ω LVDS Driver RxPOCLK Figure 5 Interface to framer IC - 4 -

5 (3) Reference Clock No. Symbol Function I/O Logic Remarks 1 TxREFCLKP/N Transmitter Reference Clock I LVPECL AC coupled 2 RxREFCLKP/N Receiver Reference Clock I LVPECL AC coupled VDD Z= 50 Ω Optical Module TxREFCLK Z= 50 Ω 50 Ω VDD Z= 50 Ω VBB RxREFCLK Z= 50 Ω 50 Ω VBB Figure 6 Interface of Reference Clock (4) Monitor Clock No. Symbol Function I/O Logic Remarks 1 TxMCLKP/N Transmitter Monitor Clock O LVDS 155 MHz 2 RxMCLKP/N Receiver Monitor Clock O LVDS 622 MHz Input Buffer 100 Ω Z= 100 Ω Optical Module LVDS Driver TxMCLK 100 Ω Input Buffer Z= 100 Ω LVDS Driver RxMCLK Figure 7 Interface of Monitor Clock - 5 -

6 Control (1) Reference Clock Frequency Selection No. TxREFSEL0 Function Remarks 1 H 622 MHz LVTTL 2 L 155 MHz (2) Laser Enable No. LsENABLE Function Remarks 1 H Laser Disable LVTTL 2 L Laser Enable (3) Lock to Reference Clock No. RxLCKREF Function Remarks 1 H Normal LVTTL 2 L Lock to RxREFCLK (4) Asynchronous Transmitter Reset No. TxRESET Function Remarks 1 H Normal LVTTL 2 L MUX Reset (5) Asynchronous Receiver Reset No. RxRESET Function Remarks 1 H Normal LVTTL 2 L DMUX Reset - 6 -

7 Alarm (1) Tx PLL Lock Detect Error Alarm No. TxLOCKERR Function Remarks 1 H Normal LVTTL 2 L Loss of Lock (2) Rx PLL Lock Detect Error Alarm No. RxLOCKERR Function Remarks 1 H Normal LVTTL 2 L Loss of Lock (3) Laser Temperature Alarm No. LsTEMPALM Function Remarks 1 H Normal LVTTL 2 L Alarm Active (4) Laser Bias Alarm No. LsBIASALM Function Remarks 1 H Normal LVTTL 2 L Alarm Active Monitor (1) Laser Power Monitor LsPOWMON output voltage is normalized (0.5 V) at the beginning of life relative to the initial optical output power. (2) Laser Bias Monitor LsBIASMON output voltage is proportional to the laser bias current with typical slope of 20 mv/ma. (3) Input Power Monitor RxLOPMON output voltage is proportional to the optical mean input power. Typical slope is 0.5 V/mW

8 Voltage Supply +5 V V FIL FIL FIL +5 V Analog K1, K V Analog K4, K V Digital F4, F5, F7, F8-5.2 V Analog K10, K11, K13, K14 Rx FIL -5.2 V Digital F10, F11, F13, F14 FIL +5 V Analog K16, K17 FIL +3.3 V Analog K19, K20, K22, K23 FIL FIL +3.3 V Digital F19, F20, F22, F V Analog K25, K26, K28, K29, Tx FIL -5.2 V Digital F25, F26, F28, F29 Frame GND Analog GND Analog GND Frame GND Digital GND Digital GND H1, H2, H4, H5 H7, H8, H10, H11, H13, H14 H16, H17, H19, H20, H22, H23 H25, H26, H28, H29 Figure 8 Recommended power supply connection VCC (+5 V) TDR2 VDD (+3.3 V) TDR1 TDF VEE (-5.2 V) Figure 9 Recommended power supply application sequence (Power off sequence is Don t Care ) - 8 -

9 PERFORMANCE SPECIFICATIONS Absolute Maximum Ratings Stresses in excess of the Absolute Maximum Ratings can cause permanent damage to the device. Table 1. Absolute Maximum Ratings No. Parameter Symbol Min. Max. Unit Remarks 1 Supply Voltage V CC 0 +6 V +5.0 V 2 Supply Voltage V DD V +3.3 V 3 Supply Voltage V EE -6 0 V -5.2 V 4 Pigtail Fiber Tensile Strength L pg N 5 Pigtail Fiber Bend Radius R pg 30 - mm 6 Storage Temperature T str C 7 Optical receiver input Pimax +2 dbm Average Operating Environment Electrical and optical characteristics below are defined under this operating environment, unless otherwise specified. Table 2. Operating Environment No. Parameter Symbol Min. Typ. Max. Unit Remarks 1 Supply Voltage V CC V 2 Supply Voltage V DD V 3 Supply Voltage V EE V 4 Supply Voltage Noise V NT 50 mvpp (Note 1) Tolerance 5 Case Temperature T C C Note 1: At range of 6 khz to 2 MHz - 9 -

10 Optical Characteristics Table 3.1 TRV5010CN-xx Optical Characteristics (Note1) No. Parameter Symbol Min. Typ. Max. Unit Remarks 1 Center Wavelength λ C nm 2 Optical Output Power P f dbm Average, EOL 3 Extinction Ratio E r db 4 Side-mode Suppression S r db Ratio 5 Receiver Sensitivity P rmin dbm 6 Receiver Overload P ro dbm 7 Optical Path Penalty P P db 6.6 ps/nm 8 Jitter - Compliant with GR Note 1: Data Rate; NRZ at Gbit/s, Mark Ratio 50%, PRBS=2 23-1, 1x10-12 BER Table 3.2 TRV5020CN-xx Optical Characteristics (Note1) No. Parameter Symbol Min. Typ. Max. Unit Remarks 1 Center Wavelength λ C nm 2 Optical Output Power P f -4-0 dbm Average, EOL 3 Extinction Ratio E r db 4 Side-mode Suppression S r db Ratio 5 Receiver Sensitivity P rmin dbm 6 Receiver Overload P ro dbm 7 Optical Path Penalty P P db 40 ps/nm 8 Jitter - Compliant with GR Note 1: Data Rate; NRZ at Gbit/s, Mark Ratio 50%, PRBS=2 23-1, 1x10-12 BER Table 3.3 TRV5030BN-xx Optical Characteristics (Note1) No. Parameter Symbol Min. Typ. Max. Unit Remarks 1 Center Wavelength λ C nm 2 Optical Output Power P f dbm Average, EOL Note 2 3 Extinction Ratio E r db 4 Side-mode Suppression S r db Ratio 5 Receiver Sensitivity P rmin dbm 6 Receiver Overload P ro dbm Note 2 7 Optical Path Penalty P P db 70 ps/nm 8 Jitter - Compliant with GR Note 1: Data Rate; NRZ at Gbit/s, Mark Ratio 50%, PRBS=2 23-1, 1x10-12 BER Note2: ITU-T specification is Pr, max= +5 dbm and Pro min= -1 dbm

11 Electrical Performance Table 4. Power supply Characteristics No. Parameter Symbol Min. Typ. Max. Unit Remarks 1 Supply Voltage V CC V 2 Supply Voltage V DD V 3 Supply Voltage V EE V 4 Supply Current I CC A +5 V 5 Supply Current I DD A +3.3 V 6 Supply Current I EE A -5.2 V 7 Power Consumption P DS W 8 Power supply Sequence Timing TDR µs TDR µs TDF 0-50 ms Table 5. LVDS level No. Parameter Min. Typ. Max. Unit Remarks 1 Input Differential Swing mv Single-ended 2 Input Voltage Range mv 3 Input Differential impedance Ω 4 Output High V RL 100 Ω 5 Output Low V 6 Output Differential Swing mv Single-ended Table 6. LVTTL level No. Parameter Symbol Min. Typ. Max. Unit Remarks 1 Input High Voltage V IH V 2 Input Low Voltage V IL V 3 Output High Voltage V OH V 4 Output Low Voltage V OL V

12 Table 7. Reference Clock Characteristics No. Parameter Symbol Min. Typ. Max. Unit Remarks 1 Tx Reference Clock Input TxREFCLK AC coupled Voltage Swing mv Single-ended Frequency MHz Selectable Frequency Tolerance ppm Duty Cycle % 2 Rx Reference Clock Input RxREFCLK AC coupled Voltage Swing mv Single-ended Frequency MHz Frequency Tolerance ppm Duty Cycle % Table 8. Transmitter Timing Characteristics No. Parameter Symbol Min. Typ. Max. Unit Remarks 1 TxPICLK Duty Cycle TTd % 2 TxDin Setup Time Ts ps (Note 1) 3 TxDin Hold Time Th ps (Note 1) 4 TxPICLK Rise and Fall Time TTr, ps % 5 TxDin Rise and Fall Time TTf ps % Note 1: OIF specifications are both 300 ps. Table 9. Receiver Timing Characteristics No. Parameter Symbol Min. Typ. Max. Unit Remarks 1 RxPOCLK Duty Cycle RTd % 2 RxPOCLK Rise and Fall Time RTr, ps % 3 RxDout Rise and Fall Time RTf ps % 4 RxPOCLK to RxDout Tcq_min ps 5 RxPOCLK to RxDout Tcq_max ps

13 Table 10. Alarm Characteristics No. Parameter Symbol Min. Typ. Max. Unit Remarks 1 Laser Temperature Alarm LsTEMPALM Activate Temperature Drift TBD 2 TBD C 2 Laser Bias Alarm LsBIASALM Threshold Bias current ma Table 11. Analog Monitor Characteristics No. Parameter Symbol Min. Typ. Max. Unit Remarks 1 Laser Power Monitor Voltage LsPOWMON Voltage Range 0 Vcc V Initial Voltage V Slope - (Note 1) - V/mW 2 Laser Bias Monitor Voltage LsBIASMON Voltage Range 0 Vcc V Output Voltage mv/ma (Note 2) Accuracy TBD % 3 Input Power Monitor Voltage RxLOPMON Voltage Range 0 Vcc V Output Voltage V/mW (Note 3) Accuracy TBD % Note 1: See.Figure 10. Note 2: See.Figure 11. Note 3: See.Figure

14 LsPOWMON 0.5V 0 Po mw Average Optical Output Power Figure 10 LsPOWMON characteristics Po is the initial value of average optical output power LsBIASMON 1000 mv Slope 20 mv/ma 0 Laser bias current (ma) 50 ma Figure 11 LsBIASMON characteristics RxLOPMON 500 mv Slope 0.5 V/mW 0 1 mw Recived Power (mw) Figure 12 RxLOPMON characteristics

15 Table 12. Pin Configuration K J H G F E D C B A 1 +5V Analog Reserved FFU Frame GND RxDout12P Reserved FFU RxDout8P Digital GND RxDout4P Digital GND RxDout0P 2 +5V Analog Reserved FFU Frame GND RxDout12N Reserved FFU RxDout8N Digital GND RxDout4N Digital GND RxDout0N 3 Reserved FFU Reserved FFU Reserved FFU Digital GND RxLOPMON Digital GND Reserved FFU Digital GND Reserved FFU Digital GND V Analog Reserved FFU Frame GND RxDout13P +3.3V Digital RxDout9P Digital GND RxDout5P Digital GND RxDout1P V Analog Reserved FFU Frame GND RxDout13N +3.3V Digital RxDout9N Digital GND RxDout5N Digital GND RxDout1N 6 RxRESET Reserved FFU Reserved FFU Digital GND Reserved FFU Digital GND Reserved FFU Digital GND Reserved FFU Digital GND 7 Reserved FFU Reserved FFU Analog GND RxDout14P +3.3V Digital RxDout10P Digital GND RxDout6P Digital GND RxDout2P 8 Reserved FFU Reserved FFU Analog GND RxDout14N +3.3V Digital RxDout10N Digital GND RxDout6N Digital GND RxDout2N 9 Reserved FFU Reserved FFU Reserved FFU Digital GND Reserved FFU Digital GND Reserved FFU Digital GND RxLCKREF Digital GND V Analog Reserved FFU Analog GND RxDout15P -5.2V Digital RxDout11P Digital GND RxDout7P Digital GND RxDout3P V Analog Reserved FFU Analog GND RxDout15N -5.2V Digital RxDout11N Digital GND RxDout7N Digital GND RxDout3N 12 Reserved FFU Reserved FFU Reserved FFU Digital GND Reserved FFU Digital GND Reserved FFU Digital GND Reserved FFU Digital GND V Analog Reserved FFU Analog GND Reserved FFU -5.2V Digital RxPOCLKP Digital GND RxMCLKP Digital GND RxREFCLKP V Analog Reserved FFU Analog GND Reserved FFU -5.2V Digital RxPOCLKN Digital GND RxMCLKN Digital GND RxREFCLKN 15 Reserved FFU Reserved FFU Reserved FFU Digital GND Reserved FFU Digital GND Reserved FFU Digital GND RxLOCKERR Digital GND 16 +5V Analog Reserved FFU Analog GND TxDin12P Reserved FFU TxDin8P Digital GND TxDin4P Digital GND TxDin0P 17 +5V Analog Reserved FFU Analog GND TxDin12N Reserved FFU TxDin8N Digital GND TxDin4N Digital GND TxDin0N 18 Reserved FFU Reserved FFU Reserved FFU Digital GND LsBIASMON Digital GND LsPOWMON Digital GND Reserved FFU Digital GND V Analog Reserved FFU Analog GND TxDin13P +3.3V Digital TxDin9P Digital GND TxDin5P Digital GND TxDin1P V Analog Reserved FFU Analog GND TxDin13N +3.3V Digital TxDin9N Digital GND TxDin5N Digital GND TxDin1N 21 Reserved FFU Reserved FFU Reserved FFU Digital GND LsENABLE Digital GND Reserved FFU Digital GND Reserved FFU Digital GND V Analog Reserved FFU Analog GND TxDin14P +3.3V Digital TxDin10P Digital GND TxDin6P Digital GND TxDin2P V Analog Reserved FFU Analog GND TxDin14N +3.3V Digital TxDin10N Digital GND TxDin6N Digital GND TxDin2N 24 TxRESET Reserved FFU Reserved FFU Digital GND LsBIASALM Digital GND Reserved FFU Digital GND Reserved FFU Digital GND V Analog Reserved FFU Frame GND TxDin15P -5.2V Digital TxDin11P Digital GND TxDin7P Digital GND TxDin3P V Analog Reserved FFU Frame GND TxDin15N -5.2V Digital TxDin11N Digital GND TxDin7N Digital GND TxDin3N 27 Reserved FFU Reserved FFU Reserved FFU Digital GND LsTEMPALM Digital GND Reserved FFU Digital GND Reserved FFU Digital GND V Analog Reserved FFU Frame GND TxPICLKP -5.2V Digital TxPCLKP Digital GND TxMCLKP Digital GND TxREFCLKP V Analog Reserved FFU Frame GND TxPICLKN -5.2V Digital TxPCLKN Digital GND TxMCLKN Digital GND TxREFCLKN 30 Reserved FFU Reserved FFU Reserved FFU Digital GND TxREFSEL0 Digital GND Reserved FFU Digital GND TxLOCKERR Digital GND

16 Table 13. Pin Description Pin# Symbol I/O Logic Description Remarks A1 RxDout0P O LVDS Receiver 622 Mbit/s Data Output LSB A2 RxDout0N O LVDS Receiver 622 Mbit/s Data Output LSB A3 Digital GND I Supply Receiver Digital Ground A4 RxDout1P O LVDS Receiver 622 Mbit/s Data Output A5 RxDout1N O LVDS Receiver 622 Mbit/s Data Output A6 Digital GND I Supply Receiver Digital Ground A7 RxDout2P O LVDS Receiver 622 Mbit/s Data Output A8 RxDout2N O LVDS Receiver 622 Mbit/s Data Output A9 Digital GND I Supply Receiver Digital Ground A10 RxDout3P O LVDS Receiver 622 Mbit/s Data Output A11 RxDout3N O LVDS Receiver 622 Mbit/s Data Output A12 Digital GND I Supply Receiver Digital Ground A13 RxREFCLKP I AC Receiver Reference Clock A14 RxREFCLKN I AC Receiver Reference Clock A15 Digital GND I Supply Receiver Digital Ground A16 TxDin0P I LVDS Transmitter 622 Mbit/s Data Input LSB A17 TxDin0N I LVDS Transmitter 622 Mbit/s Data Input LSB A18 Digital GND I Supply Transmitter Digital Ground A19 TxDin1P I LVDS Transmitter 622 Mbit/s Data Input A20 TxDin1N I LVDS Transmitter 622 Mbit/s Data Input A21 Digital GND I Supply Transmitter Digital Ground A22 TxDin2P I LVDS Transmitter 622 Mbit/s Data Input A23 TxDin2N I LVDS Transmitter 622 Mbit/s Data Input A24 Digital GND I Supply Transmitter Digital Ground A25 TxDin3P I LVDS Transmitter 622 Mbit/s Data Input A26 TxDin3N I LVDS Transmitter 622 Mbit/s Data Input A27 Digital GND I Supply Transmitter Digital Ground A28 TxREFCLKP I AC Transmitter Reference Clock A29 TxREFCLKN I AC Transmitter Reference Clock A30 Digital GND I Supply Transmitter Digital Ground

17 Table 13. Pin Description (Continue) Pin# Symbol I/O Logic Description Remarks B1 Digital GND I Supply Receiver Digital Ground B2 Digital GND I Supply Receiver Digital Ground B3 Reserved FFU Reserved for future use B4 Digital GND I Supply Receiver Digital Ground B5 Digital GND I Supply Receiver Digital Ground B6 Reserved FFU Reserved for future use B7 Digital GND I Supply Receiver Digital Ground B8 Digital GND I Supply Receiver Digital Ground B9 RxLCKREF I LVTTL Locks RxPOCLK to RxREFCLK Active low B10 Digital GND I Supply Receiver Digital Ground B11 Digital GND I Supply Receiver Digital Ground B12 Reserved FFU Reserved for future use B13 Digital GND I Supply Receiver Digital Ground B14 Digital GND I Supply Receiver Digital Ground B15 RxLOCKERR O LVTTL Indicates loss of Rx PLL locks Active low B16 Digital GND I Supply Transmitter Digital Ground B17 Digital GND I Supply Transmitter Digital Ground B18 Reserved FFU Reserved for future use B19 Digital GND I Supply Transmitter Digital Ground B20 Digital GND I Supply Transmitter Digital Ground B21 Reserved FFU Reserved for future use B22 Digital GND I Supply Transmitter Digital Ground B23 Digital GND I Supply Transmitter Digital Ground B24 Reserved FFU Reserved for future use B25 Digital GND I Supply Transmitter Digital Ground B26 Digital GND I Supply Transmitter Digital Ground B27 Reserved FFU Reserved for future use B28 Digital GND I Supply Transmitter Digital Ground B29 Digital GND I Supply Transmitter Digital Ground B30 TxLOCKERR O LVTTL Indicates loss of Tx PLL locks Active low

18 Table 13. Pin Description (Continue) Pin# Symbol I/O Logic Description Remarks C1 RxDout4P O LVDS Receiver 622 Mbit/s Data Output C2 RxDout4N O LVDS Receiver 622 Mbit/s Data Output C3 Digital GND I Supply Receiver Digital Ground C4 RxDout5P O LVDS Receiver 622 Mbit/s Data Output C5 RxDout5N O LVDS Receiver 622 Mbit/s Data Output C6 Digital GND I Supply Receiver Digital Ground C7 RxDout6P O LVDS Receiver 622 Mbit/s Data Output C8 RxDout6N O LVDS Receiver 622 Mbit/s Data Output C9 Digital GND I Supply Receiver Digital Ground C10 RxDout7P O LVDS Receiver 622 Mbit/s Data Output C11 RxDout7N O LVDS Receiver 622 Mbit/s Data Output C12 Digital GND I Supply Receiver Digital Ground C13 RxMCLKP O LVDS Receiver Monitor Clock C14 RxMCLKN O LVDS Receiver Monitor Clock C15 Digital GND I Supply Receiver Digital Ground C16 TxDin4P I LVDS Transmitter 622 Mbit/s Data Input C17 TxDin4N I LVDS Transmitter 622 Mbit/s Data Input C18 Digital GND I Supply Transmitter Digital Ground C19 TxDin5P I LVDS Transmitter 622 Mbit/s Data Input C20 TxDin5N I LVDS Transmitter 622 Mbit/s Data Input C21 Digital GND I Supply Transmitter Digital Ground C22 TxDin6P I LVDS Transmitter 622 Mbit/s Data Input C23 TxDin6N I LVDS Transmitter 622 Mbit/s Data Input C24 Digital GND I Supply Transmitter Digital Ground C25 TxDin7P I LVDS Transmitter 622 Mbit/s Data Input C26 TxDin7N I LVDS Transmitter 622 Mbit/s Data Input C27 Digital GND I Supply Transmitter Digital Ground C28 TxMCLKP O LVDS Transmitter Monitor Clock C29 TxMCLKN O LVDS Transmitter Monitor Clock C30 Digital GND I Supply Transmitter Digital Ground

19 Table 13. Pin Description (Continue) Pin# Symbol I/O Logic Description Remarks D1 Digital GND I Supply Receiver Digital Ground D2 Digital GND I Supply Receiver Digital Ground D3 Reserved FFU Reserved for future use D4 Digital GND I Supply Receiver Digital Ground D5 Digital GND I Supply Receiver Digital Ground D6 Reserved FFU Reserved for future use D7 Digital GND I Supply Receiver Digital Ground D8 Digital GND I Supply Receiver Digital Ground D9 Reserved FFU Reserved for future use D10 Digital GND I Supply Receiver Digital Ground D11 Digital GND I Supply Receiver Digital Ground D12 Reserved FFU Reserved for future use D13 Digital GND I Supply Receiver Digital Ground D14 Digital GND I Supply Receiver Digital Ground D15 Reserved FFU Reserved for future use D16 Digital GND I Supply Transmitter Digital Ground D17 Digital GND I Supply Transmitter Digital Ground D18 LsPOWMON O Analog Laser output power monitor D19 Digital GND I Supply Transmitter Digital Ground D20 Digital GND I Supply Transmitter Digital Ground D21 Reserved FFU Reserved for future use D22 Digital GND I Supply Transmitter Digital Ground D23 Digital GND I Supply Transmitter Digital Ground D24 Reserved FFU Reserved for future use D25 Digital GND I Supply Transmitter Digital Ground D26 Digital GND I Supply Transmitter Digital Ground D27 Reserved FFU Reserved for future use D28 Digital GND I Supply Transmitter Digital Ground D29 Digital GND I Supply Transmitter Digital Ground D30 Reserved FFU Reserved for future use

20 Table 13. Pin Description (Continue) Pin# Symbol I/O Logic Description Remarks E1 RxDout8P O LVDS Receiver 622 Mbit/s Data Output E2 RxDout8N O LVDS Receiver 622 Mbit/s Data Output E3 Digital GND I Supply Receiver Digital Ground E4 RxDout9P O LVDS Receiver 622 Mbit/s Data Output E5 RxDout9N O LVDS Receiver 622 Mbit/s Data Output E6 Digital GND I Supply Receiver Digital Ground E7 RxDout10P O LVDS Receiver 622 Mbit/s Data Output E8 RxDout10N O LVDS Receiver 622 Mbit/s Data Output E9 Digital GND I Supply Receiver Digital Ground E10 RxDout11P O LVDS Receiver 622 Mbit/s Data Output E11 RxDout11N O LVDS Receiver 622 Mbit/s Data Output E12 Digital GND I Supply Receiver Digital Ground E13 RxPOCLKP O LVDS Receiver parallel output clock E14 RxPOCLKN O LVDS Receiver parallel output clock E15 Digital GND I Supply Receiver Digital Ground E16 TxDin8P I LVDS Transmitter 622 Mbit/s Data Input E17 TxDin8N I LVDS Transmitter 622 Mbit/s Data Input E18 Digital GND I Supply Transmitter Digital Ground E19 TxDin9P I LVDS Transmitter 622 Mbit/s Data Input E20 TxDin9N I LVDS Transmitter 622 Mbit/s Data Input E21 Digital GND I Supply Transmitter Digital Ground E22 TxDin10P I LVDS Transmitter 622 Mbit/s Data Input E23 TxDin10N I LVDS Transmitter 622 Mbit/s Data Input E24 Digital GND I Supply Transmitter Digital Ground E25 TxDin11P I LVDS Transmitter 622 Mbit/s Data Input E26 TxDin11N I LVDS Transmitter 622 Mbit/s Data Input E27 Digital GND I Supply Transmitter Digital Ground E28 TxPCLKP O LVDS Transmitter parallel output clock E29 TxPCLKN O LVDS Transmitter parallel output clock E30 Digital GND I Supply Transmitter Digital Ground

21 Table 13. Pin Description (Continue) Pin# Symbol I/O Logic Description Remarks F1 Reserved FFU Reserved for future use Spare pin F2 Reserved FFU Reserved for future use F3 RxLOPMON O Analog Receiver power monitor F4 (+)3.3V Digital I Supply Receiver Digital Power F5 (+)3.3V Digital I Supply Receiver Digital Power F6 Reserved FFU Reserved for future use F7 (+)3.3V Digital I Supply Receiver Digital Power F8 (+)3.3V Digital I Supply Receiver Digital Power F9 Reserved FFU Reserved for future use F10 (-)5.2V Digital I Supply Receiver Digital Power F11 (-)5.2V Digital I Supply Receiver Digital Power F12 Reserved FFU Reserved for future use F13 (-)5.2V Digital I Supply Receiver Digital Power F14 (-)5.2V Digital I Supply Receiver Digital Power F15 Reserved FFU Reserved for future use F16 Reserved FFU Reserved for future use F17 Reserved FFU Reserved for future use F18 LsBIASMON O Analog Laser bias current monitor F19 (+)3.3V Digital I Supply Transmitter Digital Power F20 (+)3.3V Digital I Supply Transmitter Digital Power F21 LsENABLE I LVTTL Laser enable (disable is inverse) Active low F22 (+)3.3V Digital I Supply Transmitter Digital Power F23 (+)3.3V Digital I Supply Transmitter Digital Power F24 LsBIASALM O LVTTL Laser bias current alarm Active low F25 (-)5.2V Digital I Supply Transmitter Digital Power F26 (-)5.2V Digital I Supply Transmitter Digital Power F27 LsTEMPALM O LVTTL Laser temperature alarm Active low F28 (-)5.2V Digital I Supply Transmitter Digital Power F29 (-)5.2V Digital I Supply Transmitter Digital Power F30 TxREFSEL0 I LVTTL Selects TxREFCLK Frequency

22 Table 13. Pin Description (Continue) Pin# Symbol I/O Logic Description Remarks G1 RxDout12P O LVDS Receiver 622 Mbit/s Data Output G2 RxDout12N O LVDS Receiver 622 Mbit/s Data Output G3 Digital GND I Supply Receiver Digital Ground G4 RxDout13P O LVDS Receiver 622 Mbit/s Data Output G5 RxDout13N O LVDS Receiver 622 Mbit/s Data Output G6 Digital GND I Supply Receiver Digital Ground G7 RxDout14P O LVDS Receiver 622 Mbit/s Data Output G8 RxDout14N O LVDS Receiver 622 Mbit/s Data Output G9 Digital GND I Supply Receiver Digital Ground G10 RxDout15P O LVDS Receiver 622 Mbit/s Data Output MSB G11 RxDout15N O LVDS Receiver 622 Mbit/s Data Output MSB G12 Digital GND I Supply Receiver Digital Ground G13 Reserved FFU Reserved for future use G14 Reserved FFU Reserved for future use G15 Digital GND I Supply Receiver Digital Ground G16 TxDin12P I LVDS Transmitter 622 Mbit/s Data Input G17 TxDin12N I LVDS Transmitter 622 Mbit/s Data Input G18 Digital GND I Supply Transmitter Digital Ground G19 TxDin13P I LVDS Transmitter 622 Mbit/s Data Input G20 TxDin13N I LVDS Transmitter 622 Mbit/s Data Input G21 Digital GND I Supply Transmitter Digital Ground G22 TxDin14P I LVDS Transmitter 622 Mbit/s Data Input G23 TxDin14N I LVDS Transmitter 622 Mbit/s Data Input G24 Digital GND I Supply Transmitter Digital Ground G25 TxDin15P I LVDS Transmitter 622 Mbit/s Data Input MSB G26 TxDin15N I LVDS Transmitter 622 Mbit/s Data Input MSB G27 Digital GND I Supply Transmitter Digital Ground G28 TxPICLKP I LVDS Transmitter parallel input clock G29 TxPICLKN I LVDS Transmitter parallel input clock G30 Digital GND I Supply Transmitter Digital Ground

23 Table 13. Pin Description (Continue) Pin# Symbol I/O Logic Description Remarks H1 Frame GND I Supply Frame GND tied to Chassis GND H2 Frame GND I Supply Frame GND tied to Chassis GND H3 Reserved FFU Reserved for future use H4 Frame GND I Supply Frame GND tied to Chassis GND H5 Frame GND I Supply Frame GND tied to Chassis GND H6 Reserved FFU Reserved for future use H7 Analog GND I Supply Receiver Analog GND H8 Analog GND I Supply Receiver Analog GND H9 Reserved FFU Reserved for future use H10 Analog GND I Supply Receiver Analog GND H11 Analog GND I Supply Receiver Analog GND H12 Reserved FFU Reserved for future use H13 Analog GND I Supply Receiver Analog GND H14 Analog GND I Supply Receiver Analog GND H15 Reserved FFU Reserved for future use H16 Analog GND I Supply Transmitter Analog GND H17 Analog GND I Supply Transmitter Analog GND H18 Reserved FFU Reserved for future use H19 Analog GND I Supply Transmitter Analog GND H20 Analog GND I Supply Transmitter Analog GND H21 Reserved FFU Reserved for future use H22 Analog GND I Supply Transmitter Analog GND H23 Analog GND I Supply Transmitter Analog GND H24 Reserved FFU Reserved for future use H25 Frame GND I Supply Frame GND tied to Chassis GND H26 Frame GND I Supply Frame GND tied to Chassis GND H27 Reserved FFU Reserved for future use H28 Frame GND I Supply Frame GND tied to Chassis GND H29 Frame GND I Supply Frame GND tied to Chassis GND H30 Reserved FFU Reserved for future use

24 Table 13. Pin Description (Continue) Pin# Symbol I/O Logic Description Remarks J1 Reserved FFU Reserved for future use J2 Reserved FFU Reserved for future use J3 Reserved FFU Reserved for future use J4 Reserved FFU Reserved for future use J5 Reserved FFU Reserved for future use J6 Reserved FFU Reserved for future use J7 Reserved FFU Reserved for future use J8 Reserved FFU Reserved for future use J9 Reserved FFU Reserved for future use J10 Reserved FFU Reserved for future use J11 Reserved FFU Reserved for future use J12 Reserved FFU Reserved for future use J13 Reserved FFU Reserved for future use J14 Reserved FFU Reserved for future use J15 Reserved FFU Reserved for future use J16 Reserved FFU Reserved for future use J17 Reserved FFU Reserved for future use J18 Reserved FFU Reserved for future use J19 Reserved FFU Reserved for future use J20 Reserved FFU Reserved for future use J21 Reserved FFU Reserved for future use J22 Reserved FFU Reserved for future use J23 Reserved FFU Reserved for future use J24 Reserved FFU Reserved for future use J25 Reserved FFU Reserved for future use J26 Reserved FFU Reserved for future use J27 Reserved FFU Reserved for future use J28 Reserved FFU Reserved for future use J29 Reserved FFU Reserved for future use J30 Reserved FFU Reserved for future use

25 Table 13. Pin Description (Continue) Pin# Symbol I/O Logic Description Remarks K1 (+)5V Analog I Supply Receiver Analog Power K2 (+)5V Analog I Supply Receiver Analog Power K3 Reserved FFU Reserved for future use K4 (+)3.3V Analog I Supply Receiver Analog Power K5 (+)3.3V Analog I Supply Receiver Analog Power K6 RxRESET I LVTTL Receiver Asynchronous system reset Active low K7 Reserved FFU Reserved for future use K8 Reserved FFU Reserved for future use K9 Reserved FFU Reserved for future use K10 (-)5.2V Analog I Supply Receiver Analog Power K11 (-)5.2V Analog I Supply Receiver Analog Power K12 Reserved FFU Reserved for future use K13 (-)5.2V Analog I Supply Receiver Analog Power K14 (-)5.2V Analog I Supply Receiver Analog Power K15 Reserved FFU Reserved for future use K16 (+)5V Analog I Supply Transmitter Analog Power K17 (+)5V Analog I Supply Transmitter Analog Power K18 Reserved FFU Reserved for future use K19 (+)3.3V Analog I Supply Transmitter Analog Power K20 (+)3.3V Analog I Supply Transmitter Analog Power K21 Reserved FFU Reserved for future use K22 (+)3.3V Analog I Supply Transmitter Analog Power K23 (+)3.3V Analog I Supply Transmitter Analog Power K24 TxRESET I LVTTL Transmitter Asynchronous system reset Active low K25 (-)5.2V Analog I Supply Transmitter Analog Power K26 (-)5.2V Analog I Supply Transmitter Analog Power K27 Reserved FFU Reserved for future use K28 (-)5.2V Analog I Supply Transmitter Analog Power K29 (-)5.2V Analog I Supply Transmitter Analog Power K30 Reserved FFU Reserved for future use

26 Mechanical Dimension Unit: mm (inch) 0.2 ± 0.1 ( 0.008) 5.9 ( 0.23) ( 2.76) Side View 36.9 ( 1.45) 4 (0.16) 6.3 (0.248) 1.4 (0.06) ) 9.4 (0.37) 45.7 (1.80) 0.52 ± 0.1 deep 22.2 (0.87) 5 max (0.20) ) 8 x R1.2 4 x M2.5 Threaded bolt holes 3 (0.118) max deep Optical Transmitter Output K30 A (2.92) 88.9 max (3.5) 42.9 (1.68) 46.7 (1.84) (1.98) K1 A1 Optical Receiver Input 6.8 (0.268) 6 max (0.24) ) 2.9 (0.11) 21.6 max (0.85) ( 0.05) 30 (1.18) 300pin MegArray receptacle Connector 30 max (1.18) max (4.5) 1000 ±100 (39.4 ±3.9) 18 max (0.7) Bo ttom View Figure 13 Mechanical dimensions with H type case (-xh)

27 0.2 ± 0.1 ( 0.008) 1.4 (0.06) ) 5.9 ( 0.23) ( 2.76) Side View 36.9 ( 1.45) 4 (0.16) 6.3 (0.248) 9.4 (0.37) 45.7 (1.80) 0.52 ± 0.1 deep 22.2 (0.87) 5 max (0.20) ) 8 x R1.2 4 x M2.5 Threaded bolt holes 3 (0.118) max deep Optical Transmitter Output K30 A (2.92) 88.9 max (3.5) 42.9 (1.68) 46.7 (1.84) (1.98) K1 A1 Optical Receiver Input 6.8 (0.268) 6 max (0.24) ) 2.9 (0.11) 21.6 max (0.85) ( 0.05) 30 (1.18) 300pin MegArray receptacle Connector 30 max (1.18) max (4.5) 1000 ±100 (39.4 ±3.9) 18 max (0.7) Bottom View Figure 14 Mechanical dimensions with V type case (-xv)

28 Unit: mm (inch) 0.2 ± 0.1 ( 0.008) Side View 6.3 (0.248) 11.1 (0.44) 9.4 (0.37) 45.7 (1.80) 45.7 (1.80) 0.52 ± 0.1 deep 47.5 (1.87) 6 x M2.5 Threaded bolt holes 3 (0.118) max deep on top side 4 x M2.5 Threaded bolt holes 3 (0.118) max deep 22.2 (0.87) 5 max (0.20) ) 8 x R1.2 Optical Transmitter Output K30 A (2.92) 88.9 max (3.5) 42.9 (1.68) 46.7 (1.84) (1.98) 76.2 (3.0) K1 A1 Optical Receiver Input 2.9 (0.11) (0.5) 6.8 (0.268) 14 max (0.55) 6 max (0.24) ) 21.6 max (0.85) 30 (1.18) 300pin MegArray receptacle Connector max (4.5) Bottom View 30 max (1.18) 1000 ±100 (39.4 ±3.9) Figure 15 Mechanical dimensions with F type case (-xf)

29 Optical Interface No. Parameter Specifications Remarks 1 Fiber Pigtail SMF 9/125/900 Transmitter Fiber Color Blue Receiver Fiber Color Yellow or White 2 Connector SC-PC (male) (Standard) LC FC-PC See ORDERING INFORMATION Electrical Interface No. Part name Maker Remarks or FCI Module FCI Customer USER INFORMATION Handling Precautions CAUTION: Take proper electrostatic-discharge (ESD) precautions while handling these devices. These devices are sensitive to ESD. Laser Safety This product complies with IEC Class 1. Because of size constraints, laser safety labeling is not affixed to the module but is attached to the outside of the shipping box

30 ORDERING INFORMATION TRV 5 0 x x x x - x x (1) (2)(3)(4)(5)(6)(7) (8)(9) Item Parameter Symbol (1) (2) (3) (4) Product Name TRV5010: -/I64.1 (2km) TRV5020: SR-1 (12 km) TRV5030: IR-1/S64.1 (20 km) 1310 nm direct modulation LD (cooled) / PIN transceiver (5) (6) Product Code CN: Gbit/s and RxMCLK support (7) (Function) (8) Optical Connector Type S: SC (Standard) L: LC F: FC/PC Other Connecters may be available. (9) Case Type H: Parallel to fiber direction heat sink (Figure 13) (Standard) V: Normal to fiber direction heat sink (Figure 14) F: Flat top (Figure 15)

31 Document number: OPN-DS op nex t Powered by HITACHI Document Category: Product Specifications (Data Sheet) Serial number OPN-DS Revision: 0.1 (March 28, 2001) Product Name: TRV5010/5020/5030CN-xx OC-192 Transceiver with MUX/DMUX TRV5010/5020/5030CN-xx Revision History Rev. Date Page/Line/Fig/Table Modification Note 0.0 Feb 01, 2001 Based on TRV5020CN-S, 0.1 Mar 28, 2001 (1) P27, Figure 13 (2) P9, Table2 (1) Draw xv mechanical dimensions (2) Add Supply Voltage Noise Tolerance Rev1.1, Oct 27,