LC75810E, LC75810T 1/8 to 1/10-Duty Dot Matrix LCD Controller / Driver

Transcription

1 L78E, L78T /8 to /-Duty Dot Matrix LD ontroller / Driver Overview The L78E and L78T are /8 to / duty dot matrix LD display controllers/drivers that support the display of characters, numbers, and symbols. In addition to generating dot matrix LD drive signals based on data transferred serially from a microcontroller, the L78E and L78T also provide on-chip character display ROM and RAM to allow display systems to be implemented easily. Features ontrols and drives a 7, 8, or 9 dot matrix LD. Supports accessory display segment drive (up to 8 segments) Display technique: /8-duty, /-bias drive ( 7 dots, 6 7 dots) /9-duty, /-bias drive ( 8 dots, 6 8 dots) /-duty, /-bias drive ( 9 dots, 6 9 dots) Display digits: 6 digits line ( 7 dots), digits line ( 8 or 9 dots) digits line (6 7, 6 8, or 6 9 dots) Display control memory GROM: characters ( 7, 8, or 9 dots) GRAM: 6 characters ( 7, 8, or 9 dots) DRAM: 6 8 bits ALATH: 8 bits Instruction function Display on/off control Smooth up, down, left, and right scrolling of the display Provides a backup function based on power saving mode The frame frequency of the common and segment output waveforms can be controlled by instructions. Built-in display contrast adjustment circuit Serial data input supports B* format communication with the system controller Independent LD driver block power supply Provides a RES pin for I internal initialization. R oscillator circuit PQFP x / QIPE [L78E] TQFP x / TQIP [L78T] * omputer ontrol Bus (B) is an ON Semiconductor s original bus format and the bus addresses are controlled by ON Semiconductor. ORDERING INFORMATION See detailed ordering and shipping information on page of this data sheet. Semiconductor omponents Industries, LL, 7 Publication Order Number : July 7 - Rev. L78E_T/D

2 L78E, L78T Pin Assignments (Top view) OM/S79 OM6 OM VDD VLD S S S6 S S S S9 S S9 S8 S9 S S S S S S S6 S7 S6 S6 S6 S6 S6 S6 S66 S67 S68 S69 S7 S7 S7 S7 S7 S7 S76 S77 S78 S S9 S S DI L OM9/S8 L78E (QFPE) OM8 OM7 OM OM OM OM VLD VLD VLD VLD OS VSS RES S S S S S9 E 8 8 S8 S7 S6 S S S S S S S9 S8 S7 S S S S S8 S7 S6 S8 S7 S6 S S S S S S8 S7 S6 S S S S S S S6 S7 S8 S9 S6 S6 S6 S6 S6 S6 S66 S67 S68 S69 S7 S7 S7 S7 S7 S7 S S S S S S S77 OM/S79 S78 OM9/S8 S76 L78T (TQFP) OM8 OM7 OM6 OM OM OM OM OM VLD VDD VLD VLD VLD VSS VLD OS E RES L S S S S S S9 S S7 S8 S6 DI S S9 S8 S7 S6 S6 S S S S S S S S9 S8 S7 S S S S S9 S8 S7 S6 S S S S S S S9 S8 S7 S6

3 Specifications Absolute Maximum Ratings at Ta, V L78E, L78T Parameter Symbol onditions Ratings Unit Maximum supply voltage Input voltage Output voltage Output current Allowable power dissipation V DD max V DD. to 7. max. to. V IN E, L, DI, RES. to 7. V IN OS. to V DD. V IN,,. to. V OUT OS. to V DD. V OUT, S to S8, OM to OM. to. I OUT S to S8 A I OUT OM to OM ma Pd max Ta 8 mw Operating temperature Topr to 8 Storage temperature Tstg to V V V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Allowable Operating Ranges at Ta to 8, V Supply voltage Parameter Symbol onditions Ratings min. typ. max. V DD V DD.7 6. When the display contrast adjustment circuit is used. When the display contrast adjustment circuit is not used Output voltage. V / Input voltage / V / Input high level voltage V IH E, L, DI, RES.8 V DD 6. V Input low level voltage V IL E, L, DI, RES. V DD V Recommended external resistance Recommended external capacitance Guaranteed oscillation range Rosc OS kω osc OS 7 pf fosc OS 6 khz Data setup time tds L, DI (Figure ) 6 ns Data hold time tdh L, DI (Figure ) 6 ns E wait time tcp E, L (Figure ) 6 ns E setup time tcs E, L (Figure ) 6 ns E hold time tch E, L (Figure ) 6 ns High level clock pulse width Low level clock pulse width t H L (Figure ) 6 ns t L L (Figure ) 6 ns Minimum reset pulse width twres RES (Figure ) s Unit V Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability.

4 L78E, L78T Electrical haracteristics for the Allowable Operating Ranges Parameter Symbol onditions Ratings min. typ. max. Hysteresis V H E, L, DI, RES.V DD V Input high level current I IH E, L, DI, RES: V I 6. V. A Input low level current I IL E, L, DI, RES: V I V. A Output high level voltage Output low level voltage Output middle level voltage V OH S to S8: I O A.6 V OH OM to OM: I O A.6 V OL S to S8: I O A.6 V OL OM to OM: I O A.6 V MID V MID V MID S to S8: I O A OM to OM: I O A OM to OM: I O A /.6 /.6 /.6 /.6 /.6 /.6 Oscillator frequency fosc OS: R OS k OS 7 pf 9 khz I DD V DD : Power saving mode I DD V DD : V DD 6. V Output open 7 f OS khz I LD : Power saving mode urrent drain I LD :. V Output open f OS khz 9 A When the display contrast adjustment circuit is used I LD :. V Output open f OS khz When the display contrast adjustment circuit is not used Note : Excluding the bias voltage generation divider resistors built into the,,,, and pins. (See figure.) Unit V V V ONTRAST ADJUSTER To the common and segment drivers Excluding these resistors Figure Product parametric performance is indicated in the Electrical haracteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical haracteristics if operated under different conditions.

5 When L is stopped at the low level E L78E/T VIH VIL L VIH % VIL tφh tφl tcp tcs tch DI VIH VIL tds tdh When L is stopped at the high level E VIH VIL L tφl tφh VIH % VIL tcp tcs tch DI VIH VIL tds tdh Figure Block Diagram S8/OM9 S79/OM S78 OMMON DRIVER SEGMENT DRIVER LATH INSTRUTION DEODER INSTRUTION REGISTER SROLL OUNTER GRAM 9 6 bits ADDRESS OUNTER GROM 9 bits DRAM 6 8 bits TIMING GENERATOR ADDRESS REGISTER LOK GENERATOR SHIFT REGISTER B INTERFAE OS DI L E OM OM8 S ALATH 8bits V DD ONTRAST ADJUSTER RES Page

6 L78E/T Pin Functions Pin Pin No. L78E L78T Function Active level I/O Handling when unused S to S78 S79/OM S8/OM9 to to Segment driver outputs The S79/OM and S8/OM9 pins can be used as common driver outputs under the set display technique instruction. O OPEN OM to OM8 9 to 8 88 to 8 ommon driver outputs O OPEN OS Oscillator connection. An oscillator circuit is formed by connecting an external resistor and capacitor at this pin. I/O VDD E 98 Serial data transfer inputs. These pins are connected to the H I L 99 microcontroller. E: hip enable I DI L: Synchronization clock DI: Transfer data I GND RES Reset signal input When RES is low ( ) Display off S to S78 = L ( ) S79/OM and S8/OM9 = L ( ) OM to OM8 = L ( ) Serial data transfer is disabled. L I GND The OS pin oscillator is stopped. When RES is high (V DD ) Display on after a display on/off control (display on state setting) instruction is executed. Serial data transfers are enabled. The OS pin oscillator operates. 9 9 LD drive / bias voltage (high level) supply pin. The level on this pin can be changed by the display contrast adjustment circuit. However, must be greater than or equal to. V. Also, O OPEN external power must not be applied to this pin since the pin circuit includes the display contrast adjustment circuit. 9 9 LD drive / bias voltage (middle level) supply pin. This pin can be used to supply the / voltage level externally. I OPEN 9 9 LD drive / bias voltage (middle level) supply pin. This pin can be used to supply the / voltage level externally. I OPEN 96 9 LD drive / bias voltage (middle level) supply pin. This pin can be used to supply the / voltage level externally. I OPEN V DD 9 89 Logic block power supply connection. Provide a voltage of between.7 and 6. V. 9 9 LD driver block power supply connection. Provide a voltage of between 7. and. V when the display contrast adjustment circuit is used and provide a voltage of between. and. V when the circuit is not used Power supply connection. onnect to ground. Page 6

7 L78E/T Block Functions A (Address counter) A is a counter that provides the DRAM address. The address is automatically modified internally, and the LD display state is retained. DRAM (Data control RAM) DRAM is the RAM that is used to store display data expressed as 8-bit character codes. (These character codes are converted to 7, 8, or 9 dot matrix character patterns using GROM or GRAM.) DRAM has a capacity of 6 8 bits, and can hold 6 characters. The table below lists the correspondence between the 6-bit DRAM address loaded into A and the display position on the LD panel. For a 6 digits line display structure (For a set display technique instruction with Z = and Z = ) When the DRAM address loaded into A is H DRAM address (hexadecimal) Display digit First line A B D E F D E F However, when the display smooth scrolling is performed, the DRAM address shifts as follows. DRAM address (hexadecimal) Display digit First line A B D E F D E F Shift to the left by character digit DRAM address (hexadecimal) Display digit First line F A B D E F B D E Shift to the right by character digit Note that the display area on the LD is display digits to 6 on the first line when a display technique is 7, 8, or 9 dots, and it is display digits to on the first line when a display technique is 6 7, 6 8, or 6 9 dots. For a digits lines display structure (For a set display technique instruction with Z = and Z = ) When the DRAM address loaded into A is H Display digit DRAM address First line A B D E F D E F (hexadecimal) Second line A B D E F D E F However, when the display smooth scrolling is performed, the DRAM address shifts as follows. Display digit Shift to the left DRAM address First line A B D E F D E F by character (hexadecimal) digit Second line A B D E F D E F Display digit Shift to the right DRAM address First line F A B D E F B D E by character (hexadecimal) digit Second line F A B D E F B D E Display digit Shift to the up or DRAM address First line A B D E F D E F down by (hexadecimal) character digit Second line A B D E F D E F Note that the display area on the LD is display digits to 6 on the first line when a display technique is 7, 8, or 9 dots, and it is display digits to on the first line when a display technique is 6 7, 6 8, or 6 9 dots. Page 7

8 L78E/T For a 6 digits lines display structure (For a set display technique instruction with Z = and Z = ) When the DRAM address loaded into A is H Display digit First line A B D E F Second line A B D E F DRAM address (hexadecimal) Third line A B D E F Fourth line A B D E F However, when the display smooth scrolling is performed, the DRAM address shifts as follows. DRAM address (hexadecimal) Display digit First line A B D E F Second line A B D E F Third line A B D E F Fourth line A B D E F Shift to the left by character digit Display digit First line F A B D E Shift to the right by Second line F A B D E DRAM address (hexadecimal) character digit Third line F A B D E Fourth line F A B D E Display digit First line A B D E F Second line A B D E F Shift to the up by character digit DRAM address (hexadecimal) Third line A B D E F Fourth line A B D E F Display digit First line A B D E F Second line A B D E F Shift to the down by character digit DRAM address (hexadecimal) Third line A B D E F Fourth line A B D E F Note that the display area on the LD is display digits to 6 on the first line when a display technique is 7, 8, or 9 dots, and it is display digits to on the first line when a display technique is 6 7, 6 8, or 6 9 dots. Note : The DRAM address is expressed in hexadecimal. Least significant bit Most significant bit LSB MSB DRAM address DA DA DA DA DA DA Hexadecimal Hexadecimal Example: When the DRAM address is EH DA DA DA DA DA DA Note : 7 dots 6-digit display 7 dots. 8 dots 6-digit display 8 dots. 9 dots 6-digit display 9 dots. 6 7 dots -digit display 6 7 dots. 6 8 dots -digit display 6 8 dots. 6 9 dots -digit display 6 9 dots. Page 8

9 L78E/T GROM (haracter generator ROM) GROM is the ROM that is used to generate the kinds of 7, 8, or 9 dot matrix character patterns from the 8-bit character codes. GROM has a capacity of bits. When a character code is written to DRAM, the character pattern stored in the GROM corresponding to the character code is displayed at the position on the LD corresponding to the DRAM address loaded into A. GRAM (haracter generator RAM) GRAM is the RAM to which user programs can freely write arbitrary character patterns. Up to 6 kinds of 7, 8, or 9 dot matrix character patterns can be stored. GRAM has a capacity of 6 bits. ALATH (Additional data latch) ALATH is the latch that is used to store the ADATA display data for the accessory display. ALATH has a capacity of 8 bits, and the stored display data is displayed directly without the use of GROM or GRAM. S (Scroll counter) S is the counter that is used to scroll the display in the left, right, up, or down directions in dot units. Since this function scrolls in dot units, it implements smooth scrolling. Reset Function The L78E and L78T are reset when a low level is applied to the RES pin at power on and, in normal mode. On a reset the L78E and L78T create a display with all LD panels turned off. However, after a reset applications must set the contents of DRAM, ALATH, and GRAM before turning on display with a display on/off control instruction since the contents of these memories are undefined. That is, applications must execute the following instructions. Set display technique DRAM data write ALATH data write (If ALATH is used.) GRAM data write (IF GRAM is used.) Set A and S addresses Set display contrast (If the display contrast adjustment circuit is used.) After executing the above instructions, applications must turn on the display with a display on/off control instruction. Note that when applications turn off in the normal mode, applications must turn off the display with a display on/off control instruction. (See the detailed instruction descriptions.) Serial Data Transfer Format When L is stopped at the low level E L DI D D B B B B A A A A D D D D D B address 8 bits Instruction data Up to bits When L is stopped at the high level E L DI B address: EH D D B B B B A A A A B address 8 bits D D D Instruction data Up to bits D D D to D: Instruction data The data is acquired on the rising edge of the L signal and latched on the falling edge of the E signal. When transferring instruction data from the microcontroller, applications must assure that the time from the transfer of one set of instruction data until the next instruction data transfer is significantly longer than the instruction execution time. Page 9

10 L78E/T Instruction Table Instruction D D D D6 D7 D79 D8 D8 D D D D D D6 D7 D8 D9 D D D D D D D6 D7 D8 D9 D D D D D D D6 D7 D8 D9 D Set display technique OZ OZ DW DT DT F Display on/off control DG DG DG DG DG DG6 DG7 DG8 DG9 DG DG DG DG DG DG DG6 M A S BU HS HS HS VS VS VS VS R/L D/U Set A and S addresses HA HA HA VA VA VA VA DA DA DA DA DA DA DRAM data write ( 7) A A A A A A A6 A7 DA DA DA DA DA DA IM IM ALATH data write AD AD AD AD AD6 AD6 AD7 AD8 AD9 AD6 AD6 AD6 AD6 AD6 AD6 AD66 AD67 AD68 AD69 AD7 AD7 AD7 AD7 AD7 AD7 AD76 AD77 AD78 AD79 AD8 GRAM data write ( 9) D D D D D D D6 D7 D8 D9 D D D D D D A A A A A A A6 A7 WM Set display contrast T T T T T Notes : The execution times listed here apply when fosc = khz. The execution times differ when the oscillator frequency fosc differs. Example: When fosc = khz 7 μs = 9 μs 6 μs = μs ti μs = ti. μs. μs = 8 μs : Note that when the power saving mode (BU = ) is set, the execution time is 7 µs (when fosc = khz). 6: The execution time must be seen as being 6 µs (when fosc = khz) if another display scroll instruction is executed immediately after a preceding display scroll instruction. 7, 8: Note that the data format differs when a DRAM data write instruction is executed in normal increment mode (IM =, IM = ) or super-increment mode (IM =, IM = ). Also note that the execution time is ti µs (when fosc = khz) if a DRAM data write instruction is executed in super-increment mode. (See detailed instruction descriptions.) 9, : Note that the data format differs when a GRAM data write instruction is executed in double write mode (WM = ). Also note that the execution time is. µs (when fosc = khz) if a GRAM data write instruction is executed in double write mode. (See detailed instruction descriptions.) D D D Execution time ( ) μs μs/7 μs ( ) 7 μs/6 μs ( 6) 7 μs 7 μs/ti μs ( 8) μs 7 μs/. μs ( ) μs : don t care Page

11 Detailed Instruction Descriptions Set display technique <Sets the display technique.> ode L78E/T D8 D9 D D D D D D D6 D7 D8 D9 D D D D OZ OZ DW DT DT F DT, DT: Set the display technique DT DT Display technique S8/OM9 Output pins S79/OM /8 duty, / bias drive S8 S79 /9 duty, / bias drive OM9 S79 / duty, / bias drive OM9 OM F: Set the frame frequency of the common and segment output waveforms :don t care : Sn (n = 79, 8): Segment output OMn (n = 9, ): ommon output F Frame frequency /8 duty, / bias drive f8[hz] /9 duty, / bias drive f9[hz] / duty, / bias drive f[hz] fosc fosc fosc fosc fosc fosc OZ, OZ: Set the display structure OZ OZ Display structure 6 digits line display structure digits lines display structure 6 digits lines display structure : See block functions (DRAM) DW: Set the dot font width DW Dot font width Number of display digits -dot font width 6 digits line ( 7 dots), digits line ( 8 or 9 dots) 6-dot font width digits line (6 7, 6 8, or 6 9 dots) : -dot font width ( 7, 8, or 9 dots) OM OM OM OM OM OM6 OM7 OM8 S8/OM9 S79/OM S S S S S S6 S7 S8 S9 S S7 S7 S7 S7 S7 S76 S77 S78 OM/S79 OM9/S8 6-dot font width (6 7, 6 8, or 6 9 dots) OM OM OM OM OM OM6 OM7 OM8 S8/OM9 S79/OM S S S S S S6 S7 S8 S9 S S S S67 S68 S69 S7 S7 S7 S7 S7 S7 S76 S77 S78 Page

12 Display on/off control <Turns the display on or off.> L78E/T ode D D D D D D D6 D7 D8 D9 D D D D D D D6 D7 D8 D9 D D D D DG DG DG DG DG DG6 DG7 DG8 DG9 DG DG DG DG DG DG DG 6 M A S BU M, A: Specifies the data to be turned on or off. M A Display operating state Both MDATA and ADATA are turned off. (The display is forcibly turned off, regardless of the DG to DG6 data.) Only ADATA is turned on. (The ADATA of display digits specified by the DG to DG6 data are turned on.) Only MDATA is turned on. (The MDATA of display digits specified by the DG to DG6 data are turned on.) Both MDATA and ADATA are turned on. (The MDATA and ADATA of display digits specified by the DG to DG6 data are turned on.) *: MDATA, ADATA 7 dot matrix 8 dot matrix 9 dot matrix ADATA ADATA ADATA MDATA MDATA MDATA 6 7 dot matrix 6 8 dot matrix 6 9 dot matrix ADATA ADATA ADATA MDATA MDATA MDATA DG to DG6: Specifies the display digit. Display digit Display digit data DG DG DG DG DG DG6 DG7 DG8 DG9 DG DG DG DG DG DG DG6 For example, if DG to DG8 are, and DG9 to DG6 are, then display digits to 8 will be turned on, and display digits 9 to 6 will be turned off (blanked). S: ontrols the common and segment output pins. S ommon and segment output pin states Output of LD drive waveforms Fixed at the level (all segments off) Note : When S is, the S to S8 and OM to OM output pins are set to the level, regardless of the M, A, and DG to DG6 data. BU: ontrols the normal mode and power saving mode. BU Mode Normal mode Power saving mode (In this mode, the OS pin oscillator is stopped, and the common and segment pins are set to the level. In this mode, instructions other than the display on/off control and set display contrast instructions cannot be executed. Thus applications must set the I to normal mode before executing any of the other instructions.) Page

13 L78E/T <Scrolls the display smoothly.> ode D D D D D D D6 D7 D8 D9 D D D D D D D6 D7 D8 D9 D D D D HS HS HS VS VS VS VS R/L D/U : don t care HS to HS: Set the amount of smooth scrolling to be applied to MDATA in the left/right direction. HS HS HS Amount of smooth scrolling to be applied to MDATA in the left/right direction No shift in either the left or right direction Shift dot to the left or right. (The shift direction (left or right) is specified with the R/L data.) Shift dots to the left or right. (The shift direction (left or right) is specified with the R/L data.) Shift dots to the left or right. (The shift direction (left or right) is specified with the R/L data.) Shift dots to the left or right. (The shift direction (left or right) is specified with the R/L data.) Shift dots to the left or right. (The shift direction (left or right) is specified with the R/L data.) Shift 6 dots to the left or right. (The shift direction (left or right) is specified with the R/L data.) VS to VS: Set the amount of smooth scrolling to be applied to MDATA in the up/down direction. VS VS VS VS Amount of smooth scrolling to be applied to MDATA in the up/down direction No shift in either the up or down direction Shift dot to the up or down. (The shift direction (up or down) is specified with the D/U data.) Shift dots to the up or down. (The shift direction (up or down) is specified with the D/U data.) Shift dots to the up or down. (The shift direction (up or down) is specified with the D/U data.) Shift dots to the up or down. (The shift direction (up or down) is specified with the D/U data.) Shift dots to the up or down. (The shift direction (up or down) is specified with the D/U data.) Shift 6 dots to the up or down. (The shift direction (up or down) is specified with the D/U data.) Shift 7 dots to the up or down. (The shift direction (up or down) is specified with the D/U data.) Shift 8 dots to the up or down. (The shift direction (up or down) is specified with the D/U data.) Shift 9 dots to the up or down. (The shift direction (up or down) is specified with the D/U data.) ( 6) Shift dots to the up or down. (The shift direction (up or down) is specified with the D/U data.) ( 7) Notes: 6: This shift cannot be used when MDATA is 7 or 6 7 dots. 7: This shift cannot be used when MDATA is 7, 8, 6 7 or 6 8 dots. R/L: Specifies the MDATA shift direction (left or right). D/U: Specifies the MDATA shift direction (up or down). R/L MDATA shift direction (left or right) D/U MDATA shift direction (up or down) Shift left Shift up Shift right Shift down 8 Example of the display scroll instruction execution Assume that a digits lines display structure (OZ =, OZ = ) has been set up with the set display technique instruction, and that the following data has been written to DRAM with the DRAM data write instruction. Display digit DRAM First line A B D E F G H I J K L M N O P Q R S T U V W Y Z < > z y x w data Second line a b c d e f g h i j k l m n o p q r s t u v Page

14 L78E/T Display state () With no shifting in any direction, left, right, up, or down. HS HS HS VS VS VS VS R/L D/U : don t care ( 7 dot matrix) (6 7 dot matrix) Display state () Shifted dots to the left relative to display state () HS HS HS VS VS VS VS R/L D/U ( 7 dot matrix) (6 7 dot matrix) Display state () Shifted 6 dots to the left relative to display state () Shifted dots to the left relative to display state () HS HS HS VS VS VS VS R/L D/U HS HS HS VS VS VS VS R/L D/U ( 7 dot matrix) (6 7 dot matrix) Page

15 Display state () Shifted dots to the up relative to display state () HS HS HS VS VS VS VS R/L D/U ( 7 dot matrix) L78E/T (6 7 dot matrix) Display state () Shifted 8 dots to the up relative to display state () Shifted dots to the up relative to display state () HS HS HS VS VS VS VS R/L D/U HS HS HS VS VS VS VS R/L D/U ( 7 dot matrix) (6 7 dot matrix) Display state (6) Shifted dots to the left and dots to the up relative to display state () HS HS HS VS VS VS VS R/L D/U ( 7 dot matrix) (6 7 dot matrix) Page

16 L78E/T Display state (7) Shifted 6 dots to the left and 8 dots to the up relative Shifted 8 dots to the up relative to display state () to display state () HS HS HS VS VS VS VS R/L D/U HS HS HS VS VS VS VS R/L D/U Shifted 6 dots to the left relative to display state () Shifted dots to the left and dots to the up relative to display state (6) HS HS HS VS VS VS VS R/L D/U HS HS HS VS VS VS VS R/L D/U ( 7 dot matrix) (6 7 dot matrix) Set A and S addresses <Specifies the DRAM address for A and the dot address of the dot matrix character pattern for S.> ode D D D D D6 D7 D8 D9 D D D D D D D6 D7 HA HA HA VA VA VA VA ode D8 D9 D D D D D D D6 D7 D8 D9 D D D D DA DA DA DA DA DA : don t care DA to DA: DRAM address DA DA DA DA DA DA LSB MSB Least Most significant bit significant bit HA to HA: Dot address in the horizontal direction for the dot matrix character pattern HA HA HA LSB MSB Least Most significant bit significant bit VA to VA: Dot address in the vertical direction for the dot matrix character pattern VA VA VA VA LSB Least significant bit MSB Most significant bit Page 6

17 L78E/T 9 The figure below lists the correspondence between the data HA to HA which is dot address in the horizontal direction and the dot matrix character pattern, and the correspondence between the data VA to VA which is dot address in the vertical direction and the dot matrix character pattern. -dot font width: 7, 8, or 9 dots Dot address in the horizontal direction HA to HA (HE) Dot address in the vertical direction VA to VA (HE) The area at HA to = H is allocated to the space at the right of the dot matrix character pattern. The area at VA to = 7H, for 7 dot characters, is allocated to the space at the bottom of the dot matrix character pattern. The area at VA to = 8H is illegal for 7 dot characters. For 8 dot characters, it is allocated to the space at the bottom of the dot matrix character pattern. The area at VA to = 9H is illegal for 7 or 8 dot characters. For 9 dot characters, it is allocated to the space at the bottom of the dot matrix character pattern. 6-dot font width: 6 7, 6 8, or 6 9 dots Dot address in the horizontal direction HA to HA (HE) Dot address in the vertical direction VA to VA (HE) The area at HA to = H is allocated to the space at the right of the dot matrix character pattern. The area at VA to = 7H, for 6 7 dot characters, is allocated to the space at the bottom of the dot matrix character pattern. The area at VA to = 8H is illegal for 6 7 dot characters. For 6 8 dot characters, it is allocated to the space at the bottom of the dot matrix character pattern. The area at VA to = 9H is illegal for 6 7 or 6 8 dot characters. For 6 9 dot characters, it is allocated to the space at the bottom of the dot matrix character pattern. : Example of the set A and S addresses instruction execution Assume that a digits lines display structure (OZ =, OZ = ) has been set up with the set display technique instruction, and that the following data has been written to DRAM with the DRAM data write instruction. DRAM data Display digit First line (DRAM address (hexadecimal)) Second line (DRAM address (hexadecimal)) A () () B () () () () D () () E () () F () () G (6) 6 (6) H (7) 7 (7) I (8) 8 (8) J (9) 9 (9) K (A) a (A) L (B) b (B) M () c () N (D) d (D) O (E) e (E) P (F) f (F) DRAM data Display digit First line (DRAM address (hexadecimal)) Second line (DRAM address (hexadecimal)) Q () g () R () h () S () i () T () j () U () k () V () l () W (6) m (6) (7) n (7) Y (8) o (8) Z (9) p (9) < (A) q (A) > (B) r (B) z () s () y (D) t (D) x (E) u (E) w (F) v (F) Page 7

18 L78E/T When DA to is set to 7H, HA to is set to H, and VA to is set to H. HA HA HA VA VA VA VA DA DA DA DA DA DA ( 7 dot matrix) (6 7 dot matrix) When DA to is set to 9H, HA to is set to H, and VA to is set to H. HA HA HA VA VA VA VA DA DA DA DA DA DA ( 7 dot matrix) (6 7 dot matrix) When DA to is set to FH, HA to is set to H, and VA to is set to H. HA HA HA VA VA VA VA DA DA DA DA DA DA ( 7 dot matrix) (6 7 dot matrix) Page 8

19 L78E/T When DA to is set to H, HA to is set to H, and VA to is set to H. HA HA HA VA VA VA VA DA DA DA DA DA DA ( 7 dot matrix) (6 7 dot matrix) When DA to is set to H, HA to is set to H, and VA to is set to 6H. HA HA HA VA VA VA VA DA DA DA DA DA DA ( 7 dot matrix) (6 7 dot matrix) DRAM data write <Specifies the DRAM address and stores data at that address.> ode D D D D D D D6 D7 D8 D9 D D D D D D D6 D7 D8 D9 D D D D A A A A A A A6 A7 DA DA DA DA DA DA IM IM : don t care DA to DA: DRAM address DA DA DA DA DA DA LSB MSB Least significant bit Most significant bit A to A7: DRAM data (character code) A A A A A A A6 A7 LSB Least significant bit MSB Most significant bit This instruction writes the 8 bits of data A to A7 to DRAM. This data is a character code, and is converted to a 7, 8, or 9 dot matrix display data using GROM or GRAM. Page 9

20 L78E/T IM and IM: Sets the method of writing data to DRAM IM IM DRAM data write method Normal DRAM data write (Specifies the DRAM address and writes the DRAM data.) Normal increment mode DRAM data write (Increments the DRAM address by + each time data is written to DRAM.) Super-increment mode DRAM data write (Writes to 6 characters of DRAM data in a single operation.) DRAM data write method when IM is and IM is. E B address B address B address B address DI () () () () bits bits bits bits DRAM Instruction execution time (7 µs) Instruction execution time (7 µs) DRAM data write finishes Instruction execution time (7 µs) DRAM data write finishes DRAM data write finishes Instruction execution time (7 µs) DRAM data write finishes DRAM data write method when IM is and IM is. (Instructions other than the DRAM data write instruction cannot be executed.) E B address B address B address B address B address B address DI DRAM () bits () () () 8 bits 8 bits 8 bits () () 8 bits 6 bits Instruction execution time (7 µs) Instruction execution time (7 µs) Instruction execution time (7 µs) Instruction execution time (7 µs) Instruction execution time (7 µs) Instruction execution time (7 µs) DRAM data write finishes DRAM data write finishes DRAM data write finishes DRAM data write finishes DRAM data write finishes DRAM data write finishes (Instructions other than the DRAM data write instruction cannot be executed.) DRAM data write method when IM is and IM is. E B address B address B address DI () () n bit n bit DRAM () n bit n ti =.μs ( 8 data.) For example Instruction execution time (ti μs) DRAM data write finishes Instruction execution time (ti μs) DRAM data write finishes Instruction execution time (ti μs) DRAM data write finishes -) (n = 8m + 6, m is an integer between and 6 that is the number of characters written as DRAM When n = bits (m = ): ti =. μs (when fosc = khz) When n = 8 bits (m = 8): ti =. μs (when fosc = khz) When n = bits (m = 6): ti = 9. μs (when fosc = khz) Note that the instruction execution time of 7 μs and ti values in µs apply when fosc = khz, and that these times will differ when the oscillator frequency fosc differs. Page

21 L78E/T Data format () ( bits) ode D D D D D D D6 D7 D8 D9 D D D D D D D6 D7 D8 D9 D D D D A A A A A A A6 A7 DA DA DA DA DA DA : don t care Data format () ( bits) ode D D D D D D D6 D7 D8 D9 D D D D D D D6 D7 D8 D9 D D D D A A A A A A A6 A7 DA DA DA DA DA DA Data format () (8 bits) ode D6 D7 D8 D9 D D D D A A A A A A A6 A7 : don t care Data format () (6 bits) ode D8 D9 D D D D D D D6 D7 D8 D9 D D D D A A A A A A A6 A7 :don t care Data format () (n bits) ode Dz Dz+ Dz+ Dz+ Dz+ Dz+ Dz+6 Dz+7 D D D D D6 D7 D8 D9 A A A A A A A6 A7 A m- A m- A m- A m- A m- A m- A6 m- A7 m- ode D D D D D D D6 D7 D8 D9 D D D D D D D6 D7 D8 D9 D D D D A m A m A m A m A m A m A6 m A7 m DA DA DA DA DA DA : don t care Here, n = 8m + 6, z = 8-8m (m is an integer between and 6 that is the number of characters written as DRAM data.) orrespondence between the DRAM address and the DRAM data DRAM address DRAM data DA to DA A to A7 (DA to DA ) + A to A7 (DA to DA ) + A to A7 (DA to DA ) + (m ) A m- to A7 m- (DA to DA ) + (m ) A m- to A7 m- (DA to DA ) + (m ) A m to A7 m Page

22 L78E/T Example : When n = bits (m = : characters DRAM data write operation) ode D D D D D6 D7 D8 D9 D D D D D D D6 D7 A A A A A A A6 A7 A A A A A A A6 A7 ode D8 D9 D D D D D D D6 D7 D8 D9 D D D D DA DA DA DA DA DA : don t care orrespondence between the DRAM address and the DRAM data DRAM address DRAM data DA to DA A to A7 (DA to DA ) + A to A7 Example : When n = 8 bits (m = 8: 8 characters DRAM data write operation) ode D6 D6 D66 D67 D68 D69 D7 D7 D7 D7 D7 D7 D76 D77 D78 D79 A A A A A A A6 A7 A A A A A A A6 A7 ode D8 D8 D8 D8 D8 D8 D86 D87 D88 D89 D9 D9 D9 D9 D9 D9 A A A A A A A6 A7 A A A A A A A6 A7 ode D96 D97 D98 D99 D D D D D D D6 D7 D8 D9 D D A A A A A A A6 A7 A 6 A 6 A 6 A 6 A 6 A 6 A6 6 A7 6 ode D D D D D6 D7 D8 D9 D D D D D D D6 D7 A 7 A 7 A 7 A 7 A 7 A 7 A6 7 A7 7 A 8 A 8 A 8 A 8 A 8 A 8 A6 8 A7 8 ode D8 D9 D D D D D D D6 D7 D8 D9 D D D D DA DA DA DA DA DA : don t care orrespondence between the DRAM address and the DRAM data DRAM address DRAM data DA to DA A to A7 (DA to DA ) + A to A7 (DA to DA ) + A to A7 (DA to DA ) + A to A7 (DA to DA ) + A to A7 (DA to DA ) + A 6 to A7 6 (DA to DA ) + 6 A 7 to A7 7 (DA to DA ) + 7 A 8 to A7 8 Page

23 L78E/T Example : When n = bits (m = 6: 6 characters DRAM data write operation) ode D D D D D D D6 D7 D8 D9 D D D D D D A A A A A A A6 A7 A A A A A A A6 A7 ode D6 D7 D8 D9 D D D D D D D6 D7 D8 D9 D D A A A A A A A6 A7 A A A A A A A6 A7 ode D D D D D6 D7 D8 D9 D D D D D D D6 D7 A A A A A A A6 A7 A 6 A 6 A 6 A 6 A 6 A 6 A6 6 A7 6 ode D8 D9 D D D D D D D6 D7 D8 D9 D6 D6 D6 D6 A 7 A 7 A 7 A 7 A 7 A 7 A6 7 A7 7 A 8 A 8 A 8 A 8 A 8 A 8 A6 8 A7 8 ode D6 D6 D66 D67 D68 D69 D7 D7 D7 D7 D7 D7 D76 D77 D78 D79 A 9 A 9 A 9 A 9 A 9 A 9 A6 9 A7 9 A A A A A A A6 A7 ode D8 D8 D8 D8 D8 D8 D86 D87 D88 D89 D9 D9 D9 D9 D9 D9 A A A A A A A6 A7 A A A A A A A6 A7 ode D96 D97 D98 D99 D D D D D D D6 D7 D8 D9 D D A A A A A A A6 A7 A A A A A A A6 A7 ode D D D D D6 D7 D8 D9 D D D D D D D6 D7 A A A A A A A6 A7 A 6 A 6 A 6 A 6 A 6 A 6 A6 6 A7 6 ode D8 D9 D D D D D D D6 D7 D8 D9 D D D D DA DA DA DA DA DA : don t care orrespondence between the DRAM address and the DRAM data DRAM address DRAM data DRAM address DRAM data DA to DA A to A7 (DA to DA ) + 8 A 9 to A7 9 (DA to DA ) + A to A7 (DA to DA ) + 9 A to A7 (DA to DA ) + A to A7 (DA to DA ) + A to A7 (DA to DA ) + A to A7 (DA to DA ) + A to A7 (DA to DA ) + A to A7 (DA to DA ) + A to A7 (DA to DA ) + A 6 to A7 6 (DA to DA ) + A to A7 (DA to DA ) + 6 A 7 to A7 7 (DA to DA ) + A to A7 (DA to DA ) + 7 A 8 to A7 8 (DA to DA ) + A 6 to A7 6 Page

24 L78E/T ALATH data write <Write data to the ALATH> ode D6 D7 D8 D9 D6 D6 D6 D6 D6 D6 D66 D67 D68 D69 D7 D7 AD AD AD AD AD AD6 AD7 AD8 AD9 AD AD AD AD AD AD AD6 ode D7 D7 D7 D7 D76 D77 D78 D79 D8 D8 D8 D8 D8 D8 D86 D87 AD7 AD8 AD9 AD AD AD AD AD AD AD6 AD7 AD8 AD9 AD AD AD ode D88 D89 D9 D9 D9 D9 D9 D9 D96 D97 D98 D99 D D D D AD AD AD AD6 AD7 AD8 AD9 AD AD AD AD AD AD AD6 AD7 AD8 ode D D D6 D7 D8 D9 D D D D D D D6 D7 D8 D9 AD9 AD AD AD AD AD AD AD6 AD7 AD8 AD9 AD6 AD6 AD6 AD6 AD6 ode D D D D D D D6 D7 D8 D9 D D D D D D AD6 AD66 AD67 AD68 AD69 AD7 AD7 AD7 AD7 AD7 AD7 AD76 AD77 AD78 AD79 AD8 ode D6 D7 D8 D9 D D D D : don t care AD to AD8: ADATA display data In addition to the 7, 8, 9, 6 7, 6 8, or 6 9 dot matrix display data (MDATA), the L78E/T also supports an accessory display of or 6 segments (ADATA) at each display digit, and allows arbitrary data to be displayed directly without going through GROM or GRAM. The figure below shows the correspondence between that data and the display. When ADn = (where n is an integer between and 8), the segment corresponding to that data will be turned on. -dot font width ( 7, 8, or 9 dots) OM AD AD AD AD AD AD6 AD7 AD8 AD9 AD AD7 AD7 AD7 AD7 AD7 AD76 AD77 AD78 AD79 AD8 OM OM OM OM OM6 OM7 OM8 S8/OM9 S79/OM S S S S S S6 S7 S8 S9 S S7 S7 S7 S7 S7 S76 S77 S78 OM/S79 OM9/S8 Page

25 L78E/T 6-dot font width (6 7, 6 8, or 6 9 dots) OM AD AD AD AD AD AD6 AD7 AD8 AD9 AD AD AD AD67 AD68 AD69 AD7 AD7 AD7 AD7 AD7 AD7 AD76 AD77 AD78 OM OM OM OM OM6 OM7 OM8 S8/OM9 S79/OM S S S S S S6 S7 S8 S9 S S S S67 S68 S69 S7 S7 S7 S7 S7 S7 S76 S77 S78 orrespondence between ADATA and the output pins ADATA orresponding output pin ADATA orresponding output pin ADATA orresponding output pin AD S AD S AD6 S6 AD S AD S AD6 S6 AD S AD S AD6 S6 AD S AD S AD6 S6 AD S AD S AD6 S6 AD6 S6 AD6 S6 AD66 S66 AD7 S7 AD7 S7 AD67 S67 AD8 S8 AD8 S8 AD68 S68 AD9 S9 AD9 S9 AD69 S69 AD S AD S AD7 S7 AD S AD S AD7 S7 AD S AD S AD7 S7 AD S AD S AD7 S7 AD S AD S AD7 S7 AD S AD S AD7 S7 AD6 S6 AD6 S6 AD76 S76 AD7 S7 AD7 S7 AD77 S77 AD8 S8 AD8 S8 AD78 S78 AD9 S9 AD9 S9 AD79 S79 AD S AD S AD8 S8 AD S AD S AD S AD S AD S AD S AD S AD S AD S AD S AD6 S6 AD6 S6 AD7 S7 AD7 S7 AD8 S8 AD8 S8 AD9 S9 AD9 S9 AD S AD6 S6 Page

26 L78E/T GRAM data write <Specifies the GRAM address and stores data at that address.> ode D8 D8 D8 D8 D8 D8 D86 D87 D88 D89 D9 D9 D9 D9 D9 D9 D D D D D D6 D7 D8 D9 D D D D D D D6 ode D96 D97 D98 D99 D D D D D D D6 D7 D8 D9 D D D7 D8 D9 D D D D D D D6 D7 D8 D9 D D D ode D D D D D6 D7 D8 D9 D D D D D D D6 D7 D D D D6 D7 D8 D9 D D D D D D ode D8 D9 D D D D D D D6 D7 D8 D9 D D D D A A A A A A A6 A7 WM :don t care A to A7: GRAM address A A A A A A A6 A7 LSB MSB Least significant bit Most significant bit D to D: GRAM data ( 7, 8, or 9 dot matrix display data) The bit Dn (where n is an integer between and ) corresponds to the 7, 8, or 9 dot matrix display data. The figure below shows that correspondence. When Dn is, the dots which correspond to that data will be turned on. D D D D D D6 D7 D8 D9 D D D D D D *: D to D: 7 dot matrix display data D to D: 8 dot matrix display data D to D: 9 dot matrix display data D6 D7 D8 D9 D D D D D D D6 D7 D8 D9 D D D D D D D6 D7 D8 D9 D D D D D D Page 6

27 L78E/T WM: Sets the method of writing data to GRAM. WM GRAM data write method Normal GRAM data write (Specifies a GRAM address and write a GRAM data.) Double write mode GRAM data write (Specifies two GRAM addresses and writes two GRAM data to those addresses.) : GRAM data write method when WM is. E B address B address B address B address DI (6) (6) (6) 6 bits 6 bits 6 bits GRAM (6) 6 bits Instruction execution time (7 µs) Instruction execution time (7 µs) GRAM data write finishes Instruction execution time (7 µs) GRAM data write finishes GRAM data write finishes Instruction execution time (7 µs) GRAM data write finishes GRAM data write method when WM is. E B address B address B address DI (7) (7) (7) bits bits bits GRAM Instruction execution time (.μs) GRAM data write finishes Instruction execution time (.μs) GRAM data write finishes Instruction execution time (.μs) GRAM data write finishes Note that the instruction execution times of 7 µs and. µs apply when fosc = khz, and that these times will differ when the oscillator frequency fosc differs. Data format (6) (6 bits) ode D8 D8 D8 D8 D8 D8 D86 D87 D88 D89 D9 D9 D9 D9 D9 D9 D D D D D D6 D7 D8 D9 D D D D D D D6 ode D96 D97 D98 D99 D D D D D D D6 D7 D8 D9 D D D7 D8 D9 D D D D D D D6 D7 D8 D9 D D D ode D D D D D6 D7 D8 D9 D D D D D D D6 D7 D D D D6 D7 D8 D9 D D D D D D ode D8 D9 D D D D D D D6 D7 D8 D9 D D D D A A A A A A A6 A7 : don t care Page 7

28 L78E/T Data format (7) ( bits) ode D D D6 D7 D8 D9 D D D D D D D6 D7 D8 D9 D D D D D D6 D7 D8 D9 D D D D D D D6 ode D D D D D D D6 D7 D8 D9 D D D D D D D7 D8 D9 D D D D D D D6 D7 D8 D9 D D D ode D6 D7 D8 D9 D6 D6 D6 D6 D6 D6 D66 D67 D68 D69 D7 D7 D D D D6 D7 D8 D9 D D D D D D ode D7 D7 D7 D7 D76 D77 D78 D79 D8 D8 D8 D8 D8 D8 D86 D87 A A A A A A A6 A7 D D D D D D6 D7 D8 ode D88 D89 D9 D9 D9 D9 D9 D9 D96 D97 D98 D99 D D D D D9 D D D D D D D6 D7 D8 D9 D D D D D ode D D D6 D7 D8 D9 D D D D D D D6 D7 D8 D9 D D6 D7 D8 D9 D D D D D D D6 D7 D8 D9 D ode D D D D D D D6 D7 D8 D9 D D D D D D D D D D D A A A A A A A6 A7 ode D6 D7 D8 D9 D D D D : don t care orrespondence between the GRAM address and the GRAM data GRAM address GRAM data A to A7 D to D A to A7 D to D Page 8

29 L78E/T Set display contrast <Sets the display contrast.> ode D8 D9 D D D D D D D6 D7 D8 D9 D D D D T T T T T :don t care T to T: Sets the display contrast ( steps) T T T T LD drive / bias voltage supply level.9 = -(. ).9 = -(. ).88 = -(. ).8 = -(. ).8 = -(. 6).79 = -(. 7).76 = -(. 8).7 = -(. 9).7 = -(. ).67 = -(. ).6 = -(. ) T: Sets the display contrast adjustment circuit state T Display contrast adjustment circuit state The display contrast adjustment circuit is disabled, and the pin level is forced to the level. The display contrast adjustment circuit operates, and the display contrast is adjusted. Note that although the display contrast can be adjusted by operating the built-in display contrast adjustment circuit, it is also possible to be adjusted by varying the voltage level on the LD driver block power supply pin. However, the level on must be greater than or equal to.v. Page 9

30 Notes on the Power On and Power Off Sequences L78E/T The following sequences must be observed when power is turned on and off. (See Figure.) At power on: Logic block power supply (V DD ) on LD driver block power supply ( ) on. At power off: LD driver block power supply ( ) off Logic block power supply (V DD ) off. However, if the logic and LD driver block use a shared power supply, then the power supplies can be turned on and off at the same time. t t t V DD twres RES V IL V IH Instruction execution Initial state settings Display state Display off Display on Display off Display on/off control Display on/off control instruction execution instruction execution (Turning the display on) (Turning the display off) Initial state setting t t > t (t > t) twres μs min Set display technique DRAM data write ALATH data write (If ALATH is used) GRAM data write (If GRAM is used) Set A and S addresses Set display contrast (If the display contrast adjustment circuit is used) Figure Page

31 L78E/T /8 Duty, / Bias Drive Technique OM OM OM8 LD driver output when all LD segments corresponding to OM to OM8 are turned off LD driver output when only LD segments corresponding to OM are turned on LD driver output when only LD segments corresponding to OM are turned on LD driver output when all LD segments corresponding to OM to OM8 are turned on T8 8 T8 T8 = f8 When a set display technique instruction with F = is executed: f8 = When a set display technique instruction with F = is executed: f8 = fosc 7 fosc 6 Page

32 L78E/T /9 Duty, / Bias Drive Technique OM OM OM9 LD driver output when all LD segments corresponding to OM to OM9 are turned off LD driver output when only LD segments corresponding to OM are turned on LD driver output when only LD segments corresponding to OM are turned on LD driver output when all LD segments corresponding to OM to OM9 are turned on T9 9 T9 T9= f9 When a set display technique instruction with F = is executed: f9 = When a set display technique instruction with F = is executed: f9 = fosc 6 fosc 78 Page

33 L78E/T / Duty, / Bias Drive Technique OM OM OM LD driver output when all LD segments corresponding to OM to OM are turned off LD driver output when only LD segments corresponding to OM are turned on LD driver output when only LD segments corresponding to OM are turned on LD driver output when all LD segments corresponding to OM to OM are turned on T T T = f When a set display technique instruction with F = is executed: f = When a set display technique instruction with F = is executed: f = fosc 8 fosc 9 Page

34 L78E/T Sample Application ircuit 7 dot matrix, /8 duty, / bias drive (for use with normal panels) LD panel + V V DD OM +8 V OPEN OM OM OM OM OM6 OM7 OM8.7 μf OS S S S S S S6 S7 S8 S9 S From the controller RES E L DI S76 S77 S78 OM/S79 OM9/S8 Sample Application ircuit 7 dot matrix, /8 duty, / bias drive (for use with large panels) LD panel + V V DD OM +8 V.7 μf kω R. kω R R R R OS OM OM OM OM OM6 OM7 OM8 S S S S S S6 S7 S8 S9 S From the controller RES E L DI S76 S77 S78 OM/S79 OM9/S8 Page

35 L78E/T Sample Application ircuit 8 dot matrix, /9 duty, / bias drive (for use with normal panels) LD panel + V V DD OM +8 V OPEN OM OM OM OM OM6 OM7 OM8 S8/OM9.7 μf OS S S S S S S6 S7 S8 S9 S From the controller RES E L DI S76 S77 S78 OM/S79 Sample Application ircuit 8 dot matrix, /9 duty, / bias drive (for use with large panels) LD panel + V V DD OM +8 V.7 μf kω R. kω R R R R OS OM OM OM OM OM6 OM7 OM8 S8/OM9 S S S S S S6 S7 S8 S9 S From the controller RES E L DI S76 S77 S78 OM/S79 Page

36 L78E/T Sample Application ircuit 9 dot matrix, / duty, / bias drive (for use with normal panels) LD panel + V V DD OM +8 V OPEN OM OM OM OM OM6 OM7 OM8 S8/OM9 S79/OM.7 μf OS S S S S S S6 S7 S8 S9 S From the controller RES E L DI S76 S77 S78 Sample Application ircuit 6 9 dot matrix, / duty, / bias drive (for use with large panels) LD panel + V V DD OM +8 V.7 μf kω R. kω R R R R OS OM OM OM OM OM6 OM7 OM8 S8/OM9 S79/OM S S S S S S6 S7 S8 S9 S From the controller RES E L DI S76 S77 S78 Page 6

37 L78E/T Sample Application ircuit dot matrix, /8 duty, / bias drive (for use with normal panels) LD panel + V V DD OM +8 V OPEN OM OM OM OM OM6 OM7 OM8.7 μf OS S S S S S S6 S7 S8 S9 S S S From the controller RES E L DI S7 S7 S7 S76 S77 S78 OM/S79 OM9/S8 OPEN Sample Application ircuit dot matrix, /8 duty, / bias drive (for use with large panels) LD panel + V V DD OM +8 V.7 μf kω R. kω R R R R OS OM OM OM OM OM6 OM7 OM8 S S S S S S6 S7 S8 S9 S S S From the controller RES E L DI S7 S7 S7 S76 S77 S78 OM/S79 OM9/S8 OPEN Page 7

38 L78E/T Sample Application ircuit dot matrix, /9 duty, / bias drive (for use with normal panels) LD panel + V V DD OM +8 V OPEN OM OM OM OM OM6 OM7 OM8 S8/OM9.7 μf OS S S S S S S6 S7 S8 S9 S S S From the controller RES E L DI S7 S7 S7 S76 S77 S78 OM/S79 OPEN Sample Application ircuit 6 8 dot matrix, /9 duty, / bias drive (for use with large panels) LD panel + V V DD OM +8 V.7 μf kω R. kω R R R R OS OM OM OM OM OM6 OM7 OM8 S8/OM9 S S S S S S6 S7 S8 S9 S S S From the controller RES E L DI S7 S7 S7 S76 S77 S78 OM/S79 OPEN Page 8

39 L78E/T Sample Application ircuit 6 9 dot matrix, / duty, / bias drive (for use with normal panels) LD panel + V V DD OM +8 V OPEN OM OM OM OM OM6 OM7 OM8 S8/OM9 S79/OM From the controller.7μf OS RES E L DI S S S S S S6 S7 S8 S9 S S S S7 S7 S7 S76 S77 S78 Sample Application ircuit 6 9 dot matrix, / duty, / bias drive (for use with large panels) LD panel + V V DD OM +8 V.7 μf kω R. kω From the controller R R R R OS RES E L DI OM OM OM OM OM6 OM7 OM8 S8/OM9 S79/OM S S S S S S6 S7 S8 S9 S S S S7 S7 S7 S76 S77 S78 Page 9

40 L78E/T No Sample showing the orrespondence between Instructions and the Display (Using the L78-87 with a 7 dots, 6 digits line display) LSB Instruction (hexadecimal) MSB D to D D6 to D9 D to D D to D7 D8 to D D to D D6 to D9 D to D Display Operation Power application (initialization with the RES pin) Initializes the I. The display is in the off state. Set display technique 8 Sets to the /8 duty / bias display technique, the digits lines display structure, and the -dot font width at each digit. DRAM data write (normal increment mode) Writes the display data S to DRAM address H. A DRAM data write (normal increment mode) Writes the display data A to DRAM address H. DRAM data write (normal increment mode) Writes the display data N to DRAM address H. E DRAM data write (normal increment mode) Writes the display data Y to DRAM address H. 9 DRAM data write (normal increment mode) Writes the display data O to DRAM address H. F DRAM data write (normal increment mode) Writes the display data to DRAM address H. DRAM data write (normal increment mode) Writes the display data I to DRAM address 6H. 9 DRAM data write (normal increment mode) Writes the display data to DRAM address 7H. DRAM data write (normal increment mode) Writes the display data to DRAM address 8H. DRAM data write (normal increment mode) Writes the display data L to DRAM address 9H. DRAM data write (normal increment mode) Writes the display data to DRAM address AH. DRAM data write (normal increment mode) Writes the display data 7 to DRAM address BH. 7 DRAM data write (normal increment mode) Writes the display data to DRAM address H. DRAM data write (normal increment mode) Writes the display data 8 to DRAM address DH. 8 DRAM data write (normal increment mode) Writes the display data to DRAM address EH. ontinued on next page. Page

41 L78E/T ontinued from perceding page. No. LSB Instruction (hexadecunal) D to D D6 to D9 D to D D to D7 D8 to D D to D D6 to D9 8 DRAM data write (normal increment mode) 9 DRAM data write (normal increment mode) DRAM data write (normal increment mode) DRAM data write (normal increment mode) DRAM data write (normal increment mode) DRAM data write (normal increment mode) DRAM data write (normal increment mode) DRAM data write (normal increment mode) 6 DRAM data write (normal increment mode) 9 7 DRAM data write (normal increment mode) 6 8 DRAM data write (normal increment mode) 9 DRAM data write (normal increment mode) DRAM data write (normal increment mode) DRAM data write (normal increment mode) DRAM data write (normal increment mode) DRAM data write (normal increment mode) DRAM data write (normal increment mode) MSB D to D Display Operation Writes the display data to DRAM address FH. Writes the display data to DRAM address H. Writes the display data L to DRAM address H. Writes the display data to DRAM address H. Writes the display data D to DRAM address H. Writes the display data to DRAM address H. Writes the display data D to DRAM address H. Writes the display data R to DRAM address 6H. Writes the display data I to DRAM address 7H. Writes the display data V to DRAM address 8H. Writes the display data E to DRAM address 9H. Writes the display data R to DRAM address AH. Writes the display data to DRAM address BH. Writes the display data to DRAM address H. Writes the display data to DRAM address DH. Writes the display data to DRAM address EH. Writes the display data to DRAM address FH. ontinued on next page. Page