RW CH Segment Driver

Transcription

1 Functions: Dot matrix LCD driver with two 40 channel outputs Bias voltage (V1 ~ V4) Input/output signals Input : Serial display data and control pulse from controller IC Output : 40 X 2 channels waveform for LCD driving Features: Power supply for logic : 2.7V ~ 5.5V Power supply for LCD voltage (V DD ~V EE ) : 3V ~ 7V Bare chip available Description: is a segment driver for dot matrix type LCD display. It features 80 channels with 40 X 2 bits bi-directional shift registers, data latches, LCD drivers and logic control circuits. It is fabricated by CMOS process with low current consumption. The can convert serial data received from a LCD controller, such as RW1063, into parallel data and send out LCD driving waveforms to the LCD panel. The is designed for general-purpose LCD drivers. It can drive both static and dynamic drive LCD. The LSI can be used as segment driver. The has pin function compatibility with the KS0063 that allows the user easily to replace it with a. 1

2 Revision History Version Date Description V /4/18 First Edition V /9/25 Modify Pin Description 2

3 Functional Block Diagram S1 S40 S41 S80 V1 V2 V3 V4 SEGMENT DRIVER SEGMENT DRIVER DATA LATCH (20 bits) DATA LATCH (20 bits) VDD VSS VEE BIDIRECTIONAL SHIFTER (20 bits) BIDIRECTIONAL SHIFTER (20 bits) M CL1 CL2 CONTROL DL1 SHL1 DR1 DL2 SHL2 DR2 3

4 Pad Arrangement Chip size: 3138um x 2178um Chip thickness: um PAD Pitch: 96 um ~ 138 um PAD Size: 88um X 88um 4

5 CHIP Layout 5

6 PAD Location Unit:mm PAD No. PIN NAME X Y PAD No. PIN NAME X Y 1 S[42] S[15] S[43] S[14] S[44] S[13] S[45] S[12] S[46] S[11] S[47] S[10] S[48] S[9] S[49] S[8] S[50] S[7] S[51] S[6] S[52] S[5] S[53] S[4] S[54] S[3] S[55] S[2] S[56] S[1] S[57] VEE S[58] V S[59] V S[60] V S[61] V S[62] VSS S[63] CL S[64] SHL S[65] SHL S[66] VDD S[67] CL S[68] DL S[69] DR S[70] DL S[71] DR S[72] M S[73] S[41] S[74] S[31] S[75] S[30] S[76] S[29] S[77] S[28] S[78] S[27] S[79] S[26] S[80] S[25] S[40] S[24] S[39] S[23] S[38] S[22] S[37] S[21] S[36] S[20] S[35] S[19] S[34] S[18] S[33] S[17] S[32] S[16]

7 Pin Description: Pin Name Purpose Description I/O VDD POWER for logic N/A VSS GROUND for logic N/A VEE LCD power for LCD driving voltage N/A V1 V2 LCD output used as select voltage level I V3 V4 LCD output used as non select voltage I S[1]-S[40] segment LCD driver output for part 1 O SHL1 direction direction control for part 1 segments I DL1, DR1 data in /out If SHL1 = 1 then DL1=out, DR1=in If SHL1 = 0 then DL1=in, DR1=out I/O S[41]-S[80] segment LCD driver output for part 2 O SHL2 direction direction control for part 2 segments I DL2, DR2 data in/out If SHL2 = 1 then DL2=out, DR2=in If SHL2 = 0 then DL2=in, DR2=out I/O M alternation Alternate the LCD driving waveform I CL1 latch clock latch the data after shift is completed I CL2 shift clock shift the data into the segments I 7

8 Functional Description: Shift Registers and Data I/O The supplies two sets of 40-bit shift register, which controls the shift direction by SHL1 & SHL2.The DL1, DR1, DL2 and DR2 are data input or output option function. Shift Direction of Channel 1 SHL1 Shift Direction DL1 DR1 0 S[1] S[40] IN OUT 1 S[40] S[1] OUT IN Shift Direction of Channel 2 SHL2 Shift Direction DL2 DR2 0 S[41] S[80] IN OUT 1 S[80] S[41] OUT IN Clock and Mode Selection The CL1 is the clock to latch data on the falling edge. It latches the data input from the bi-directional shift register at the falling edge of CL1 and transfers its outputs to the LCD driver circuit. The CL2 is the clock to shift data on the falling edge. It shifts the serial data at the falling of CL2 and transfers the output of each bit of the register to the latch circuit. 8

9 LCD Output Waveform Timing Characteristics CL2 V IH VIL T WCKL TWCKH TR TF T DH T SU Data in (DL1, DL2) (DR1, DR2) T D Data out (DL1, DL2) (DR1, DR2) V OH V OL T SL T LS TLS CL1 T WCKH T R T SU M 9

10 D.C Characteristics: Symbol Parameter Test Condition Min. Typ. Max. Unit Applicable pin VDD Operating Voltage V - V0 Driver Supply Voltage VDD-VEE 3-7 V - VIH Input High Voltage VDD VIL Input Low Voltage VDD V 0.3 VDD ILKG Input Leakage Current VIN = 0 ~ VDD -5-5 ua VOH Output High Voltage IOH = -0.4mA VDD -0.4 V - - V VOL Output Low Voltage IOL = +0.4mA V CL1,CL2,M, SHL1,SHL2 DL1,DL2,DR1,DR2 DL1,DL2,DR1,DR2 V1~V6, S[1]~S[80] IDD Operating Current FCL2 = 400KHZ ua VDD,VEE IV Leakage Current VIN = VDD ~ VEE ua V1 ~ V4 A.C Characteristics: Symbol Parameter Test Condition Min. Max. Unit Applicable pin FCL Data Shift Frequency KHZ CL2 TWCKH Clock High Level Width ns CL1,CL2 TWCKL Clock Low Level Width ns CL2 TSL Clock Set-up Time CL2 CL ns CL1,CL2 TLS Clock Set-up Time CL1 CL ns CL1,CL2 TR/TF Clock Rise/Fall Time ns CL1,CL2 TSU Data Set-up Time ns DL1,DL2,DR1,DR2 TDH Data Hold Time ns DL1,DL2,DR1,DR2 TD Data Delay Time CL = 15 PF ns DL1,DL2,DR1,DR2 Maximum Absolute Ratings: Symbol Parameters Min. Max. Unit VDD Supply Voltage V TOPR Operating Temperature TSTG Storage Temperature

11 Application Circuit 2Lines X 40 characters (RW1063*1+*2) 11