External Memory Interfaces in Arria V Devices

Transcription

1 External Memory Interfaces in Arria V evices AV-5 Subscribe The Arria V devices provide an efficient architecture that allows you to fit wide external memory interfaces to support a high level of system bandwidth within the small modular I/O bank structure. The I/Os are designed to provide high-performance support for existing and emerging external memory standards. Table -: Supported External Memory Standards in Arria V evices Memory Standard R3 SRAM R SRAM LPR SRAM RLRAM 3 RLRAM II R II+ SRAM R II SRAM Hard Memory Controller Arria V GX, GT, SX, and ST Full rate Full rate Soft Memory Controller Arria V GX, GT, SX, and ST Arria V GZ Half rate and quarter rate Half rate and quarter rate Half rate Full rate and half rate Half rate Half rate and quarter rate Half rate Full rate and half rate Half rate Full rate and half rate Half rate Full rate and half rate Related Information External Memory Interface Spec Estimator To estimate the external memory system performance specification, use Altera's External Memory Interface Spec Estimator tool. External Memory Interface Handbook Provides more information about the memory types supported, board design guidelines, timing analysis, simulation, and debugging information. Arria V evice Handbook: Known Issues Lists the planned updates to the Arria V evice Handbook chapters. 3. All rights reserved. ALTERA, ARRIA, CYCLONE, HARCOPY, MAX, MEGACORE, NIOS, UARTUS and STRATIX words and logos are trademarks of and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. ISO 9:8 Registered Innovation rive, San Jose, CA 9534

2 - External Memory Performance AV External Memory Performance Table -: External Memory Interface Performance in Arria V evices Interface Voltage (V) Hard Controller (MHz) Arria V GX, GT, SX, and ST Arria V GX, GT, SX, and ST Soft Controller (MHz) Arria V GZ R3 SRAM R SRAM LPR SRAM. 4 RLRAM RLRAM II R II+ SRAM R II SRAM R II+ SRAM HPS External Memory Performance Table -3: HPS External Memory Interface Performance The hard processor system (HPS) is available in Arria V SoC FPGA devices only. Interface Voltage (V) HPS Hard Controller (MHz) R3 SRAM R SRAM LPR SRAM. 333 Not available as Altera IP.

3 AV Memory Interface Support in Arria V evices -3 Memory Interface Support in Arria V evices In the Arria V devices, the memory interface circuitry is available in every I/O bank that does not support transceivers. The devices offer differential input buffers for differential read-data strobe and clock operations. The memory clock pins are generated with double data rate input/output (RIO) registers. Related Information Planning and FPGA Resources chapter, External Memory Interface Handbook Provides more information about which pins to use for memory clock pins and pin location requirements. Guideline: Using /S s The following list provides guidelines on using the /S pins: The devices support and S signals with bus modes of x4/x8/x9, x6/x8, or x3/x36. You can use the Sn or Cn pins that are not used for clocking as pins. If you do not use the /S pins for memory interfacing, you can use these pins as user I/Os. However, unused HPS /S pins on the Arria V SX and ST devices cannot be used as user I/Os. Some pins have multiple functions such as RZ or. If you need extra RZ pins, you can use some of the pins as RZ pins instead. Note: For the x8, x6/x8, or x3/x36 /S groups whose members are used as RZ pins, Altera recommends that you assign the and S pins manually. Otherwise, the uartus II software might not be able to place the and S pins, resulting in a no-fit error. Reading the Table For the maximum number of pins and the exact number per group for a particular Arria V device, refer to the relevant device pin table. In the pin tables, the S and Sn pins denote the differential data strobe/clock pin pairs, while the C and Cn pins denote the complementary echo clock signals. The pin table lists the parity, M, BWSn, NWSn, ECC, and VL pins as pins. Related Information Planning and FPGA Resources chapter, External Memory Interface Handbook Provides more information about read clock pins usage for R II and R II+ SRAM, and RLRAM II interfaces in Arria V GX, GT, SX, and ST devices Arria V evice -Out Files ownload the relevant pin tables from this web page.

4 -4 /S Bus Mode s for Arria V evices /S Bus Mode s for Arria V evices The following tables list the pin support per /S bus mode, including the S/C/Cn/K# and Sn pins. The maximum number of data pins per group listed in the tables may vary according to the following conditions: Single-ended S signalingthe maximum number of pins includes parity, data mask, and VL pins connected to the S bus network. ifferential or complementary S signalingthe maximum number of data pins per group decreases by one. This number may vary per /S group in a particular device. Check the pin table for the exact number per group. R3 and R interfacesthe maximum number of pins is further reduced for an interface larger than x8 because you require one S pin for each x8/x9 group to form the x6/x8 and x3/x36 groups. Table -4: /S Bus Mode s for Arria V GX, GT, SX, and ST evices AV Parity or ata Mask VL ata s per Group Mode Sn Support (Optional) (Optional) Typical Cn Support Maximum Notes x4/x8/x9 4, 8, or 9 The x4 mode uses x8/x9 groups. x6/x8 6 or 8 3 Two x8 /S groups are stitched to create a x6/x8 group, so there are 4 pins in this group. x3/x36 3 or 36 4 Four x8 /S groups are stitched to create a x3/x36 group, so there are 48 pins in this group. Table -5: /S Bus Mode s for Arria V GZ evices Parity or ata Mask VL ata s per Group Mode Sn Support (Optional) (Optional) Typical Cn Support Maximum Notes x4 4 5 If you do not use differential S and the group does not have additional signals, the data mask (M) pin is supported. x8/x9 8 or 9 Two x4 /S groups are stitched to create a x8/x9 group, so there are a total of pins in this group. x6/x8 6 or 8 3 Four x4 /S groups are stitched to create a x6/x8 group; so there are a total of 4 pins in this group. The VL pin is not used in the UniPHY megafunction.

5 AV /S Groups in Arria V GX -5 Parity or ata Mask VL ata s per Group Mode Sn Support (Optional) (Optional) Typical Cn Support Maximum Notes x3/x36 3 or 36 4 Eight x4 /S groups are stitched to create a x3/x36 group, so there are a total of 48 pins in this group. /S Groups in Arria V GX Table -6: Number of /S Groups Per Side in Arria V GX evices This table lists the /S groups for the soft memory controller. For the hard memory controller, you can get the /S groups from the pin table of the specific device. Member Code A A3 A5 Package Side x8/x9 x6/x8 x3/x pin FineLine BGA, Flip Chip 8 3 Right pin FineLine BGA, Flip Chip 3 Right pin FineLine BGA, Flip Chip 8 3 Right pin FineLine BGA, Flip Chip 3 Right 6 6-pin FineLine BGA, Flip Chip pin FineLine BGA, Flip Chip pin FineLine BGA, Flip Chip 8 8

6 -6 /S Groups in Arria V GX AV Member Code Package Side x8/x9 x6/x8 x3/x36 6-pin FineLine BGA, Flip Chip A 896-pin FineLine BGA, Flip Chip pin FineLine BGA, Flip Chip pin FineLine BGA, Flip Chip 5 5 B 5-pin FineLine BGA, Flip Chip pin FineLine BGA, Flip Chip pin FineLine BGA, Flip Chip 5 5 B3 5-pin FineLine BGA, Flip Chip pin FineLine BGA, Flip Chip 4 4 B5 5-pin FineLine BGA, Flip Chip 5-pin FineLine BGA, Flip Chip B 5-pin FineLine BGA, Flip Chip 5-pin FineLine BGA, Flip Chip Related Information Arria V evice -Out Files ownload the relevant pin tables from this web page.

7 AV /S Groups in Arria V GT Table -: Number of /S Groups Per Side in Arria V GT evices /S Groups in Arria V GT - This table lists the /S groups for the soft memory controller. For the hard memory controller, you can get the /S groups from the pin table of the specific device. Member Code C3 C 3 Package Side x8/x9 x6/x8 x3/x pin FineLine BGA, Flip Chip 8 3 Right pin FineLine BGA, Flip Chip 3 Right pin FineLine BGA, Flip Chip pin FineLine BGA, Flip Chip pin FineLine BGA, Flip Chip pin FineLine BGA, Flip Chip pin FineLine BGA, Flip Chip pin FineLine BGA, Flip Chip pin FineLine BGA, Flip Chip 4 4 Related Information Arria V evice -Out Files ownload the relevant pin tables from this web page.

8 -8 /S Groups in Arria V GZ /S Groups in Arria V GZ AV Table -8: Number of /S Groups Per Side in Arria V GZ evices Member Code Package Side x4 x8/x9 x6/x8 x3/x36 E 8-pin FineLine BGA, Flip Chip 5-pin FineLine BGA, Flip Chip E3 8-pin FineLine BGA, Flip Chip 5-pin FineLine BGA, Flip Chip E5 5-pin FineLine BGA, Flip Chip 5-pin FineLine BGA, Flip Chip E 5-pin FineLine BGA, Flip Chip 5-pin FineLine BGA, Flip Chip /S Groups in Arria V SX Table -9: Number of /S Groups Per Side in Arria V SX evices This table lists the /S groups for the soft memory controller. For the hard memory controller, you can get the /S groups from the pin table of the specific device. Member Code Package Side x8/x9 x6/x8 x3/x pin FineLine BGA, Flip Chip 6 3 B3 5-pin FineLine BGA, Flip Chip pin FineLine BGA, Flip Chip 5 4

9 AV /S Groups in Arria V ST -9 Member Code Package Side x8/x9 x6/x8 x3/x pin FineLine BGA, Flip Chip 6 3 B5 5-pin FineLine BGA, Flip Chip pin FineLine BGA, Flip Chip 5 4 Related Information Arria V evice -Out Files ownload the relevant pin tables from this web page. /S Groups in Arria V ST Table -: Number of /S Groups Per Side in Arria V ST evices This table lists the /S groups for the soft memory controller. For the hard memory controller, you can get the /S groups from the pin table of the specific device. Member Code Package Side x8/x9 x6/x8 x3/x pin FineLine BGA, Flip Chip pin FineLine BGA, Flip Chip pin FineLine BGA, Flip Chip pin FineLine BGA, Flip Chip pin FineLine BGA, Flip Chip pin FineLine BGA, Flip Chip 5 4 Related Information Arria V evice -Out Files ownload the relevant pin tables from this web page.

10 - External Memory Interface Features in Arria V evices AV External Memory Interface Features in Arria V evices UniPHY IP The Arria V I/O elements (IOE) provide built-in functionality required for a rapid and robust implementation of external memory interfacing. The following device features are available for external memory interfaces: S phase-shift circuitry PHY Clock (PHYCLK) networks S logic block ynamic on-chip termination (OCT) control IOE registers elay chains Hard memory controllers (Arria V GX, GT, SX, and ST only) Read- and write-leveling support (Arria V GZ only) The high-performance memory interface solution includes the self-calibrating UniPHY IP that is optimized to take advantage of the Arria V I/O structure and the uartus II software Timeuest Timing Analyzer. The UniPHY IP helps set up the physical interface (PHY) best suited for your system. This provides the total solution for the highest reliable frequency of operation across process, voltage, and temperature (PVT) variations. The UniPHY IP instantiates a to generate related clocks for the memory interface. The UniPHY IP can also dynamically choose the number of delay chains that are required for the system. The amount of delay is equal to the sum of the intrinsic delay of the delay element and the product of the number of delay steps and the value of the delay steps. The UniPHY IP and the Altera memory controller MegaCore functions can run at half the I/O interface frequency of the memory devices, allowing better timing management in high-speed memory interfaces. The Arria V devices contain built-in circuitry in the IOE to convert data from full rate (the I/O frequency) to half rate (the controller frequency) and vice versa. Related Information Reference Material volume, External Memory Interface Handbook Provides more information about the UniPHY IP. External Memory Interface atapath The following figures show overviews of the memory interface datapath that uses the Arria V I/O elements. In the figures, the /S read and write signals may be bidirectional or unidirectional, depending on the memory standard. If the signal is bidirectional, it is active during read and write operations.

11 AV External Memory Interface atapath Figure -: External Memory Interface atapath Overview for Arria V GX, GT, SX, and ST evices - FPGA S Postamble Circuitry Memory Postamble Clock Postamble Enable S Enable Control Circuit S elay Chain S Enable Circuit S (Read) 4n or n Read FIFO n R Input Registers n (Read) 4n Half ata Rate Output Registers n R Output and Output Enable Registers n (Write) Clock Management and Reset Full-Rate Clock Write Clock Half-Rate Clock S Write Clock 4 Half ata Rate Output Registers R Output and Output Enable Registers S (Write) Note: There are slight block differences for different memory interface standards. The shaded blocks are part of the I/O elements. Figure -: External Memory Interface atapath Overview for Arria V GZ evices FPGA Memory Postamble Clock Postamble Enable S Enable Control Circuit S Logic Block S Enable Circuit S (Read) 4n Read FIFO n R Input Registers n (Read) 4n Half ata Rate Output Registers n Alignment Registers n R Output and Output Enable Registers n (Write) Clock Management and Reset Write Clock Half-Rate Clock Alignment Clock S Write Clock 4 Half ata Rate Output Registers Alignment Registers R Output and Output Enable Registers S (Write) Note: There are slight block differences for different memory interface standards. The shaded blocks are part of the I/O elements.

12 - S Phase-Shift Circuitry S Phase-Shift Circuitry The Arria V provides phase shift to the S/C/Cn/K# pins on read transactions if the S/C/Cn/K# pins are acting as input clocks or strobes to the FPGA. The following figures show how the s are connected to the S/C/Cn/K# pins in the various Arria V variants. Figure -3: S/C/Cn/K# s and s in Arria VGX (A and A3) evices AV Reference Clock S/C/Cn/K# S/C/Cn/K# S Logic Blocks S/C/Cn/K# S/C/Cn/K# Reference Clock to IOE to IOE to IOE to IOE to IOE S Logic Blocks S/C/Cn/K# to IOE S/C/Cn/K# Transceiver Blocks to IOE S/C/Cn/K# to IOE S/C/Cn/K# to IOE to IOE to IOE to IOE Reference Clock S/C/Cn/K# S/C/Cn/K# S/C/Cn/K# S/C/Cn/K# Reference Clock

13 AV S Phase-Shift Circuitry Figure -4: S/C/Cn/K# s and s in Arria V GX (A5, A, B, B3, B5, and B), GT, and GZ evices -3 Reference Clock S/C/Cn/K# S/C/Cn/K# S Logic Blocks S/C/Cn/K# S/C/Cn/K# Reference Clock to IOE to IOE to IOE to IOE Transceiver Blocks Transceiver Blocks to IOE to IOE to IOE to IOE Reference Clock S/C/Cn/K# S/C/Cn/K# S/C/Cn/K# S/C/Cn/K# Reference Clock

14 -4 elay-locked Loop Figure -5: S/C/Cn/K# s and s in Arria V SX and ST evices AV Reference Clock S/C/Cn/K# S/C/Cn/K# to IOE to IOE HPS I/O S Logic Blocks HPS to IOE S Transceiver Blocks HPS Block to IOE Transceiver Blocks S to IOE to IOE to IOE to IOE Reference Clock S/C/Cn/K# S/C/Cn/K# S/C/Cn/K# S/C/Cn/K# Reference Clock elay-locked Loop The delay-locked loop () uses a frequency reference to dynamically generate control signals for the delay chains in each of the S/C/Cn/K# pins, allowing the delay to compensate for process, voltage, and temperature (PVT) variations. The S delay settings are gray-coded to reduce jitter if the updates the settings. There are a maximum of four s, located in each corner of the Arria V devices. You can clock each using different frequencies. Some of the s can access the two adjacent sides from its location in the device. You can have two different interfaces with the same frequency on the two sides adjacent to a, where the controls the S delay settings for both interfaces. I/O banks between two s have the flexibility to create multiple frequencies and multiple-type interfaces. These banks can use settings from either or both adjacent s. For example, SR can get its phase-shift settings from _TR, while SR can get its phase-shift settings from _BR. The reference clock for each may come from the output clocks or clock input pins.

15 AV Note: Reference Clock Input for Arria V evices If you have a dedicated that only generates the input reference clock, set the mode to No Compensation to achieve better performance (or the uartus II software automatically changes it). Because the does not use any other outputs, it does not have to compensate for any clock paths. -5 Reference Clock Input for Arria V evices Table -: Reference Clock Input from Counter Outputs for Arria V GX A and A3, and Arria V GT C3 evicespreliminary L L RC TC BC _T plldout[:] plldout[:] _T plldout[:] _B plldout[:] plldout[:] _B plldout[:] _R plldout[:] Table -: Reference Clock Input from Counter Outputs for Arria V GX A5, A, B, and B3, and Arria V GT C and 3 evicespreliminary TL TR BR BL TC BC _T plldout[:] plldout[:] _T plldout[:] plldout[:] _B plldout[:] plldout[:] _B plldout[:] plldout[:] Table -3: Reference Clock Input from Counter Outputs for Arria V GX B5 and B, and Arria V GT evicespreliminary L R R L TC BC _T plldout[:] plldout[:] _T plldout[:] plldout[:] _B plldout[:] plldout[:] _B plldout[:] plldout[:]

16 -6 Reference Clock Input for Arria V evices Table -4: Reference Clock Input for Arria V GZ E and E3 evices AV Center Corner Left CLKIN Center Right _TL CEN_X84_Y COR_X_Y8 CLKP CLK6P CEN_X84_Y68 COR_X_Y CLKP CLKP CLKP CLK8P CLK3P CLK9P _TR CEN_X84_Y CEN_X84_Y68 COR_X85_ Y8 COR_X85_ Y CLK6P CLKP CLK8P CLK9P CLKP CLK3P CLK4P CLK5P _BR CEN_X84_Y CEN_X84_Y COR_X85_ Y COR_X85_Y CLK4P CLK5P CLK6P CLK8P CLK9P CLKP CLKP CLKP _BL CEN_X84_Y COR_X_Y CLKP CLK4P CEN_X84_Y COR_X_Y CLKP CLK5P CLKP CLK6P CLK3P CLKP Table -5: Reference Clock Input for Arria V GZ E5 and E evices Center Corner Left CLKIN Center Right _TL CEN_X9_Y96 COR_X_Y CLKP CLK6P CEN_X9_Y8 COR_X_Y9 CLKP CLKP CLKP CLK8P CLK3P CLK9P _TR CEN_X9_Y96 CEN_X9_Y8 COR_X_ Y COR_X_ Y9 CLK6P CLKP CLK8P CLK9P CLKP CLK3P CLK4P CLK5P

17 AV Phase-Shift - Center Corner Left CLKIN Center Right _BR CEN_X9_Y CEN_X9_Y COR_X_ Y COR_X_Y CLK4P CLK5P CLK6P CLK8P CLK9P CLKP CLKP CLKP _BL CEN_X9_Y COR_X_Y CLKP CLK4P CEN_X9_Y COR_X_Y CLKP CLK5P CLKP CLK6P CLK3P CLKP Table -6: Reference Clock Input from Counter Outputs for Arria V SX B3 and B5, and Arria V ST 3 and 5 evicespreliminary L R L TC BC _T plldout[:] plldout[:] _B plldout[:] plldout[:] _B plldout[:] plldout[:] Phase-Shift The can shift the incoming S signals by or 9 by using two delay cells in the S logic block. The shifted S signal is then used as the clock for the IOE input registers. All S/C/Cn/K# pins, referenced to the same, can have their input signal phase shifted by a different degree amount but all must be referenced at one particular frequency. The -bit S delay settings from the vary with PVT to implement the phase-shift delay. For example, with a shift, the S/C/Cn/K# signal bypasses both the and S logic blocks. The uartus II software automatically sets the input delay chains, so that the skew between the and S/C/Cn/K# pins at the IOE registers is negligible if a shift is implemented. You can feed the S delay settings to the S logic block and logic array. The shifted S/C/Cn/K# signal goes to the S bus to clock the IOE input registers of the pins. The signal can also go into the logic array for resynchronization if you are not using IOE read FIFO for resynchronization. For Arria V SoC FPGAs, you can feed the hard processor system (HPS) S delay settings to the HPS S logic block only. The following figures show simple block diagrams of the in the Arria V devices. All features of the S phase-shift circuitry are accessible from the UniPHY megafunction in the uartus II software.

18 AV-5-8 Phase-Shift Figure -6: Simplified iagram of the S Phase-Shift Circuitry of the Arria V GX, GT, SX, and ST evices aload Input Reference Clock clk Phase Comparator upndnin upndninclkena Up/own Counter S delay settings can go to the logic array and S logic block This clock can come from a output clock or an input clock pin elay Chains delayctrlout [6:] S elay Settings dqsupdate Figure -: Simplified iagram of the S Phase-Shift Circuitry of the Arria V GZ evices addnsub Phase offset settings from the logic array (offset[6:]) Input Reference Clock This clock can come from a output clock or an input clock pin clk aload Phase Comparator upndnin upndninclkena elay Chains Up/own Counter offsetdelayctrlout[6:] offsetdelayctrlout[6:] delayctrlout[6:] dqsupdate offsetdelayctrlin[6:] S elay Settings Phase Offset Control A Phase offset settings to S pins (offsetctrlout[6:]) (dll_offset_ctrl_a) Phase offset addnsub settings can only Phase offset settings go to the S from the logic array( offset [6:] ) logic blocks Phase Offset Control Phase offset settings to S pin B (offsetctrlout[6:]) offsetdelayctrlin[6:] (dll_offset_ctrl_b) S delay settings can go to the logic array and S logic block The input reference clock goes into the to a chain of up to eight delay elements. The phase comparator compares the signal coming out of the end of the delay chain block to the input reference clock. The phase comparator then issues the upndn signal to the Gray-code counter. This signal increments or decrements a -bit delay setting (S delay settings) that increases or decreases the delay through the delay element chain to bring the input reference clock and the signals coming out of the delay element chain in phase. The can be reset from either the logic array or a user I/O pin. Each time the is reset, you must wait for,56 clock cycles for the to lock before you can capture the data properly. The phase comparator requires,56 clock cycles to lock and calculate the correct input clock period. For the frequency range of each frequency mode, refer to the device datasheet. Related Information Arria V evice atasheet

19 I/O Bank 5 Transceiver Banks PHYCLK Networks Center I/O Bank 6 AV PHY Clock (PHYCLK) Networks PHY Clock (PHYCLK) Networks -9 The PHYCLK network is a dedicated high-speed, low-skew balanced clock tree designed for a high-performance external memory interface. The top and bottom sides of the Arria V devices have up to four PHYCLK networks. There are up to two PHYCLK networks on the left and right side I/O banks. Each PHYCLK network spans across one I/O bank and is driven by one of the s located adjacent to the I/O bank. The following figures show the PHYCLK networks available in the Arria V devices. Figure -8: PHYCLK Networks in Arria V GX A and A3 evices I/O Bank 8 Center I/O Bank Left PHYCLK Networks FPGA evice Left PHYCLK Networks I/O Bank 3 Center I/O Bank 4

20 - PHY Clock (PHYCLK) Networks AV Figure -9: PHYCLK Networks in Arria V GX A5, A, B, B3, B5, and B evices, and Arria V GZ E, E3, E5, and E evices I/O Bank 8 Center I/O Bank Left PHYCLK Networks Right Transceiver Banks FPGA evice Transceiver Banks Left PHYCLK Networks Right I/O Bank 3 Center I/O Bank 4 Figure -: PHYCLK Networks in Arria V SX B3 and B5 evices, and Arria V ST 3 and 5 evices I/O Bank 8 Center I/O Bank Left PHYCLK Networks Transceiver Banks FPGA evice HPS HPS Block HPS PHYCLK Networks Transceiver Banks HPS I/O Left PHYCLK Networks Right I/O Bank 3 Center I/O Bank 4

21 AV S Logic Block Each S/C/Cn/K# pin is connected to a separate S logic block, which consists of the update enable circuitry, S delay chains, and S postamble circuitry. The following figure shows the S logic block. Figure -: S Logic Block in Arria V GX, GT, SX, and ST evices S Logic Block - The dqsenable signal can also come from the FPGA fabric Postamble Enable S Postamble Circuitry S/C/Cn/K# S Enable Control Circuit dqsenablein zerophaseclk (Postamble clock) dqsdisablen enaphasetransferreg dqsin levelingclk (Read-leveled postamble clock) S Enable PRE dqsenable dqsenableout <delay dqs enable> Applicable only if the S delay settings come from a side with two s Core Logic S delay settings from the S delay settings from the delayctrlin [6:] Bypass delayctrlin [6:] This clock can come from a output clock or an input clock pin S elay Chain dqsin dqsupdateen Input Reference Clock <dqs delay chain bypass> Update Enable Circuitry dqsbusout Figure -: S Logic Block in Arria V GZ evices Postamble Enable S/C or Cn The dqsenable signal can also come from the FPGA fabric S Postamble Circuit dqsenablein zerophaseclk dqsin PRE S Enable dqsenable enaphasetransferreg Postamble clock leveling clk <bypass_output_register> Read-leveled postamble clock S delay settings from the S phase-shift circuitry S elay Chain dqsin phasectrlin[..] <dqs_ctrl_latches_enable> offsetctrlin [6..] Phase offset Update dqsupdateen dqsenableout settings from the Enable S phase-shift Circuitry circuitry <dqs_offsetctrl_enable> delayctrlin [6..] Input Reference Clock <delay_dqs_enable_by_half_cycle> <use_alternate_input_for first_stage_delay_control> This clock can come from a output clock or an input clock pin dqsbusout Update Enable Circuitry The update enable circuitry enables the registers to allow enough time for the S delay settings to travel from the S phase-shift circuitry or core logic to all the S logic blocks before the next change.

22 - S elay Chain Both the S delay settings and the phase-offset settings pass through a register before going into the S delay chains. The registers are controlled by the update enable circuitry to allow enough time for any changes in the S delay setting bits to arrive at all the delay elements, which allows them to be adjusted at the same time. The circuitry uses the input reference clock or a user clock from the core to generate the update enable output. The UniPHY intellectual property (IP) uses this circuit by default. Figure -3: S Update Enable Waveform AV This figure shows an example waveform of the update enable circuitry output. Counter Update (Every 8 cycles) Counter Update (Every 8 cycles) System Clock S elay Settings Updated every 8 cycles Update Enable Circuitry Output bit S elay Chain S delay chains consist of a set of variable delay elements to allow the input S/C/Cn/K# signals to be shifted by the amount specified by the S phase-shift circuitry or the logic array. There are two delay elements in the S delay chain that have the same characteristics: elay elements in the S logic block elay elements in the The S/C/Cn/K# pin is shifted by the S delay settings. The number of delay chains required is transparent because the UniPHY IP automatically sets it when you choose the operating frequency. In Arria V GX, GT, and GZ devices, if you do not use the to control the S delay chains, you can input your own Gray-coded bit settings using the delayctrlin[6..] signals available in the UniPHY IP. In the Arria V SX and ST devices, the S delay chain is controlled by the S phase-shift circuitry only. S Postamble Circuitry There are preamble and postamble specifications for both read and write operations in R3 and R SRAM. The S postamble circuitry ensures that data is not lost if there is noise on the S line during the end of a read operation that occurs while S is in a postamble state. The Arria V devices contain dedicated postamble registers that you can control to ground the shifted S signal that is used to clock the input registers at the end of a read operation. This function ensures that any glitches on the S input signal during the end of a read operation and occurring while S is in a postamble state do not affect the IOE registers. For preamble state, the S is low, just after a high-impedance state. For postamble state, the S is low, just before it returns to a high-impedance state.

23 AV Half ata Rate Block For external memory interfaces that use a bidirectional read strobe (R3 and R SRAM), the S signal is low before going to or coming from a high-impedance state. -3 Half ata Rate Block The Arria V devices contain a half data rate (HR) block in the postamble enable circuitry. The HR block is clocked by the half-rate resynchronization clock, which is the output of the I/O clock divider circuit. There is an AN gate after the postamble register outputs to avoid postamble glitches from a previous read burst on a non-consecutive read burst. This scheme allows half-a-clock cycle latency for dqsenable assertion and zero latency for dqsenable deassertion. Using the HR block as the first stage capture register in the postamble enable circuitry block is optional. Altera recommends using these registers if the controller is running at half the frequency of the I/Os. Figure -4: Avoiding Glitch on a Non-Consecutive Read Burst Waveform This figure shows how to avoid postamble glitches using the HR block. Postamble glitch Postamble Preamble S Postamble Enable dqsenable elayed by /T logic Leveling Circuitry for Arria V GZ evices R3 SRAM unbuffered modules use a fly-by clock distribution topology for better signal integrity. This means that the CK/CK# signals arrive at each R3 SRAM device in the module at different times. The difference in arrival time between the first R3 SRAM device and the last device on the module can be as long as.6 ns. The following figure shows the clock topology in R3 SRAM unbuffered modules.

24 -4 Leveling Circuitry for Arria V GZ evices Figure -5: R3 SRAM Unbuffered Module Clock ology AV S/ S/ S/ S/ CK/CK# S/ S/ S/ S/ FPGA Because the data and read strobe signals are still point-to-point, take special care to ensure that the timing relationship between the CK/CK# and S signals (t SS, t SS, and t SH ) during a write is met at every device on the modules. In a similar way, read data coming back into the FPGA from the memory is also staggered. The Arria V GZ devices have leveling circuitry to address these two situations. There is one leveling circuit per I/O sub-bank (for example, I/O sub-bank A, B, and C each has one leveling circuitry). These delay chains are PVT-compensated by the same S delay settings as the and S delay chains. The uses eight delay chain taps, such that each delay chain tap generates a 45 delay. The generated clock phases are distributed to every S logic block that is available in the I/O sub-bank. The delay chain taps then feed a multiplexer controlled by the UniPHY megafunction to select which clock phases are to be used for that x4 or x 8 S group. Each group can use a different tap output from the read-leveling and write-leveling delay chains to compensate for the different CK/CK# delay going into each device on the module. Figure -6: Write-Leveling elay Chains and Multiplexers There is one leveling delay chain per I/O sub-bank (for example, I/O sub-banks A, B, and C). You can only have one memory interface in each I/O sub-bank when you use the leveling delay chain. Write clk (-9 ) Write-Leveled S Clock Write-Leveled Clock The 9 write clock of the UniPHY IP feeds the write-leveling circuitry to produce the clock to generate the S and signals. uring initialization, the UniPHY IP picks the correct write-leveled clock for the S and clocks for each /S group after sweeping all the available clocks in the write calibration process. The clock output is 9 phase-shifted compared to the S clock output. The UniPHY IP dynamically calibrates the alignment for read and write leveling during the initialization process.

25 AV ynamic OCT Control -5 Related Information Reference Material volume, External Memory Interface Handbook Provides more information about the UniPHY IP. R and R3 SRAM Board esign Guidelines chapter, External Memory Interface Handbook Provides layout guidelines for R3 SRAM interface. ynamic OCT Control The dynamic OCT control block includes all the registers that are required to dynamically turn the on-chip parallel termination (R T OCT) on during a read and turn R T OCT off during a write. Figure -: ynamic OCT Control Block for Arria V evices OCT Control Path OCT Control OCT Control OCT Enable OCT Half-Rate Clock Write Clock The full-rate write clock comes from the. The write clock and S write clock have a 9 offset between them Related Information I/O Features in Arria V evices Provides more information about dynamic OCT control. IOE Registers The IOE registers are expanded to allow source-synchronous systems to have faster register-to-fifo transfers and resynchronization. All top, bottom, and right IOEs have the same capability. Input Registers The input path consists of the R input registers and the read FIFO block. You can bypass each block of the input path. There are three registers in the R input registers block. Registers A and B capture data on the positive and negative edges of the clock while register C aligns the captured data. Register C uses the same clock as Register A. The read FIFO block resynchronizes the data to the system clock domain and lowers the data rate to half rate.

26 -6 Output Registers The following figure shows the registers available in the Arria V input path. For R3 and R SRAM interfaces, the S and Sn signals must be inverted. If you use Altera s memory interface IPs, the S and Sn signals are automatically inverted. Figure -8: IOE Input Registers for Arria V evices AV ouble ata Rate Input Registers datain [] dataout[3..] To core The input clock can be from the S logic block or from a global clock line. S/C Input Reg A Input Reg B Input Reg C datain [] wrclk Read FIFO rdclk This half-rate or full-rate read clock comes from a through the clock network Half-rate or full-rate clock Output Registers The Arria V output and output-enable path is divided into the HR block, and output and output-enable registers. The device can bypass each block of the output and output-enable path. The output path is designed to route combinatorial or registered single data rate (SR) outputs and full-rate or half-rate R outputs from the FPGA core. Half-rate data is converted to full-rate with the HR block, clocked by the half-rate clock from the. The output-enable path has a structure similar to the output pathensuring that the output-enable path goes through the same delay and latency as the output path.

27 AV Output Registers Figure -9: IOE Output and Output-Enable Path Registers for Arria V GX, GT, SX, and ST evices - The following figure shows the registers available in the Arria V GX, GT, SX, and ST output and output-enable paths. ata coming from the FPGA core are at half the frequency of the memory interface clock frequency in half-rate mode From Core From Core Half ata Rate to Single ata Rate Output-Enable Registers OE Reg A OE ouble ata Rate Output-Enable Registers OR OE Reg B OE From Core (wdata) Half ata Rate to Single ata Rate Output Registers ouble ata Rate Output Registers TRI or S From Core (wdata) OE Reg A O From Core (wdata3) From Core (wdata) OE Reg B O Half-Rate Clock from Write Clock The full-rate write clock can come from the. The write clock have a 9 offset to the S write clock.

28 -8 elay Chains Figure -: IOE Output and Output-Enable Path Registers for Arria V GZ evices AV The following figure shows the registers available in the Arria V GZ output and output-enable paths. You can bypass each register block of the output and output-enable paths. ata coming from the FPGA core are at half the frequency of the memory interface clock frequency in half-rate mode Used in R3 SRAM interfaces for write-leveling purposes From Core Half ata Rate to Single ata Rate Output-Enable Registers Alignment Registers dataout ouble ata Rate Output-Enable Registers From Core <add_output_cycle_delay> enaphasetransferreg enaoutputcycledelay[..] OE Reg A OE OR From Core (wdata) Half ata Rate to Single ata Rate Output Registers Alignment Registers dataout OE Reg B OE ouble ata Rate Output Registers TRI or S From Core (wdata) <add_output_cycle_delay> enaphasetransferreg enaoutputcycledelay[..] OE Reg A O From Core (wdata3) dataout From Core (wdata) <add_output_cycle_delay> enaphasetransferreg enaoutputcycledelay[..] OE Reg B O Half-Rate Clock From the Alignment Clock From write-leveling delay chains The write clock can come from either the or from the write-leveling delay chain. The write clock and S write clock have a 9 offset between them Write Clock elay Chains The Arria V devices contain run-time adjustable delay chains in the I/O blocks and the S logic blocks. You can control the delay chain setting through the I/O or the S configuration block output.

29 AV elay Chains -9 Every I/O block contains a delay chain between the following elements: The output registers and output buffer The input buffer and input register The output enable and output buffer The R T OCT enable-control register and output buffer Figure -: elay Chains in an I/O Block in the Arria V GX, GT, SX, and ST evices OCT Enable Output Enable 5 OCT delay chain 5 output-enable delay chain or S 5 elay delay chain elay delay chain Figure -: elay Chains in an I/O Block in Arria V GZ evices rtena oe octdelaysetting 5 OCT delay chain 5 outputenable delay chain outputdelaysetting octdelaysetting 6 OCT delay chain 6 outputenable delay chain outputdelaysetting 6 elay delay chain 5 elay delay chain elay delay chain Rise/Fall Balancing delay chain padtoinputregisterdelaysetting padtoinputregisterrisefalldelaysetting[5..]

30 -3 I/O and S Configuration Blocks Each S logic block contains a delay chain after the dqsbusout output and another delay chain before the dqsenable input. Figure -3: elay Chains in the S Input Path AV S S Enable dqsin dqsenable S delay chain 4 delay chain dqsbusout T delay chain S Enable Control I/O and S Configuration Blocks The I/O and S configuration blocks are shift registers that you can use to dynamically change the settings of various device configuration bits. The shift registers power-up low. Every I/O pin contains one I/O configuration register. Every S pin contains one S configuration block in addition to the I/O configuration register. Figure -4: Configuration Block (I/O and S) This figure shows the I/O configuration block and the S configuration block circuitry. MSB bit bit bit datain update ena rankselectread rankselectwrite dataout clk Related Information ALT_S Megafunction User Guide Provides details about the I/O and S configuration block bit sequence.

31 AV Hard Memory Controller -3 Hard Memory Controller The Arria V GX, GT, SX, and ST devices feature dedicated hard memory controllers. You can use the hard memory controllers for R and R3 SRAM interfaces. Compared to the memory controllers implemented using core logic, the hard memory controllers allow support for higher memory interface frequencies with shorter latency cycles. The hard memory controllers use dedicated I/O pins as data, address, command, control, clock, and ground pins for the SRAM interface. If you do not use the hard memory controllers, you can use these dedicated pins as regular I/O pins. Note: There is no hard memory controller in the Arria V GZ devices. Related Information Functional escriptionhpc II Controller chapter, External Memory Interface Handbook The hard memory controller is functionally similar to the High-Performance Controller II (HPC II). Functional escriptionhard Memory Interface chapter, External Memory Interface Handbook Provides detailed information about application of the hard memory interface. Features of the Hard Memory Controller Table -: Features of the Arria V Hard Memory Controller Feature escription Memory Interface ata Width Memory ensity Memory Burst Length Command and ata Reordering Starvation Control User-Configurable Priority Support Avalon -MM ata Slave Local Interface 8, 6, and 3 bit data 6 bit data + 8 bit ECC 3 bit data + 8bit ECC The controller supports up to four gigabits density parts and two chip selects. R3Burst length of 8 and burst chop of 4 RBurst lengths of 4 and 8 The controller increases efficiency through the support for out-of-order execution of RAM commandswith address collision detection-and in-order return of results. A starvation counter ensures that all requests are served after a predefined time-out period. This function ensures that data with low priority access are not left behind when reordering data for efficiency. When the controller detects a high priority request, it allows the request to bypass the current queuing request. This request is processed immediately and thus reduces latency. By default, the controller supports the Avalon Memory-Mapped protocol.

32 -3 Features of the Hard Memory Controller AV Feature Bank Management Streaming Reads and Writes Bank Interleaving Predictive Bank Management Multiport Interface Built-in Burst Adaptor Run-time Configuration of the Controller On-ie Termination User-Controlled Refresh Timing Low Power Modes Partial Array Self-Refresh ECC Additive Latency escription By default, the controller provides closed-page bank management on every access. The controller intelligently keeps a row open based on incoming traffic. This feature improves the efficiency of the controller especially for random traffic. The controller can issue reads or writes continuously to sequential addresses every clock cycle if the bank is open. This function allows for very high efficiencies with large amounts of data. The controller can issue reads or writes continuously to 'random' addresses. The controller can issue bank management commands early so that the correct row is open when the read or write occurs. This increases efficiency. The interface allows you to connect up to six data masters to access the memory controller through the local interface. You can update the multiport scheduling configuration without interrupting traffic on a port. The controller can accept bursts of arbitrary sizes on its local interface and map these bursts to efficient memory commands. This feature provides support for updates to the timing parameters without requiring reconfiguration of the FPGA, apart from the standard compile-time setting of the timing parameters. The controller controls the on-die termination (OT) in the memory, which improves signal integrity and simplifies your board design. You can optionally control when refreshes occurallowing the refreshes to avoid clashing of important reads or writes with the refresh lock-out time. You can optionally request the controller to put the memory into the self-refresh or deep power-down modes. You can select the region of memory to refresh during self-refresh through the mode register to save power. Standard Hamming single error correction, double error detection (SECE) error correction code (ECC) support: 3 bit data + 8 bit ECC 6 bit data + 8 bit ECC With additive latency, the controller can issue a REA/WRITE command after the ACTIVATE command to the bank prior to t RC to increase the command efficiency. Caution: Efficiency degradation may occur when using the additive latency feature with the hard memory controller for R3 SRAM interfaces at 533 MHz.

33 AV Multi-Port Front End -33 Feature Write Acknowledgment escription The controller supports write acknowledgment on the local interface. User Control of Memory Controller Initialization The controller supports initialization of the memory controller under the control of user logicfor example, through the software control in the user system if a processor is present. Controller Bonding Support You can bond two controllers to achieve wider data width for higher bandwidth applications. Multi-Port Front End The multi-port front end (MPFE) and its associated fabric interface provide up to six command ports, four read-data ports and four write-data ports, through which user logic can access the hard memory controller. Figure -5: Simplified iagram of the Arria V Hard Memory Interface This figure shows a simplified diagram of the Arria V hard memory interface with the MPFE. FPGA FPGA Core Logic MPFE Memory Controller PHY Memory Avalon-MM Interface AFI Bonding Support You can bond one port of any data width (64, 8, or 56 bits) from two hard memory controllers to support wider data widths. When you bond two hard memory controllers, the data going out of the controllers to the user logic is synchronized. However, the data going out of the controllers to the memory is not synchronized. The bonding controllers are not synchronized and remain independent with two separate address buses and two independent command buses. These buses are calibrated separately. If you require ECC support for a bonded interface, you must implement the ECC logic external to the hard memory controllers. Note: Only one bonding feature is available per package through the core fabric. A memory interface that uses the bonding feature has higher average latency.

34 -34 Bonding Support Figure -6: Hard Memory Controllers Bonding Support in Arria V GX A and A3 evices AV This figure shows the bonding of two opposite hard memory controllers through the core fabric. 6-bit Interface Bank 8 Bank Hard Memory Controller Bank 5 Bonding (Core Routing) Bank 6 Hard Memory Controller Bank 3 Bank 4 6-bit Interface

35 AV Bonding Support Figure -: Hard Memory Controllers Bonding Support in Arria V GX A5, A, B, B3, B5, and B evices, and Arria V GT 3 and evices This figure shows the bonding of opposite and same side hard memory controllers through the core fabric bit Interface 3-bit Interface Bank 8 Bank Hard Memory Controller Hard Memory Controller Bonding (Core Routing) Bonding (Core Routing) Core routing is enabled only for single hard memory controller bond out per side. This bonding is available only if you do not use the hard memory controllers in banks 4 and for bonding with other banks. Bonding (Core Routing) Bonding (Core Routing) Hard Memory Controller Hard Memory Controller Bank 3 3-bit Interface Bank 4 3-bit Interface

36 AV-5-36 Hard Memory Controller Width for Arria V GX Figure -8: Hard Memory Controllers in Arria V SX B3 and B5 evices, and Arria V ST 3 and 5 evices This figure shows the bonding of opposite and same side hard memory controllers through the core fabric. 3-bit R3 Interface Bank 8 HPS I/O Hard Memory Controller HPS Block No bonding support for the HPS hard memory controller. HPS Hard Memory Controller HPS I/O 3-bit R3 Interface Bonding (Core Routing) Enabled only for single hard memory controller bond out per side. This bonding is available only if you do not use the hard memory controllers in bank 3 for bonding with other banks. Bonding (Core Routing) Hard Memory Controller Hard Memory Controller Bank 3 3-bit R3 Interface Bank 4 3-bit R3 Interface Related Information Arria V GT and GX evice Family Connection Guidelines Provides more information about the dedicated pins. Hard Memory Controller Width for Arria V GX Table -8: Hard Memory Controller Width Per Side in Arria V GX A, A3, A5, and A evicespreliminary Member Code Package A A3 A5 A F F F

37 AV Hard Memory Controller Width for Arria V GT Table -9: Hard Memory Controller Width Per Side in Arria V GX B, B3, B5, and B evicespreliminary Member Code -3 Package B B3 B5 B F F F5 Hard Memory Controller Width for Arria V GT Table -: Hard Memory Controller Width Per Side in Arria V GT evicespreliminary Member Code Package C3 C 3 F6 6 6 F F F5 Hard Memory Controller Width for Arria V SX Table -: FPGA Hard Memory Controller Width Per Side in Arria V SX evicespreliminary Member Code Package B3 B5 F F F Table -: HPS Hard Memory Controller Width in Arria V SX evicespreliminary Package B3 Member Code B5 F F5 4 4

38 -38 Hard Memory Controller Width for Arria V ST AV Package B3 Member Code B5 F5 4 4 Hard Memory Controller Width for Arria V ST Table -3: FPGA Hard Memory Controller Width Per Side in Arria V ST evicespreliminary Member Code Package 3 5 F F F Table -4: HPS Hard Memory Controller Width in Arria V ST evicespreliminary Package 3 Member Code 5 F F5 4 4 F5 4 4 ocument Revision History ate May 3 Version Changes Moved all links to the Related Information section of respective topics for easy reference. Added link to the known document issues in the Knowledge Base. Updated the topic about Arria V GZ leveling circuitry. Removed the Arria V GZ phase offset control topic. Added the I/O and S configuration blocks topic. Updated the /S groups for Arria V GX. Added the /S groups for Arria V GT C3 and C. Added the reference clock input tables for all Arria V devices. Added the FPGA hard memory controller widths for Arria V GX, GT, SX, and ST. Added the HPS hard memory controller widths for Arria V SX and ST.

39 AV ocument Revision History -39 ate November June November May Version Changes Reorganized content and updated template. Added information for Arria V GZ, including a topic on the leveling circuitry. Added a list of supported external memory interface standards using the hard memory controller and soft memory controller. Added performance information for external memory interfaces and the HPS external memory interfaces. Separated the /S groups tables into separate topics for each device variant for easy reference. Moved the PHYCLK networks pin placement guideline to the Planning and FPGA Resources chapter of the External Memory Interface Handbook. Moved information from the "esign Considerations" section into relevant topics. Removed the "R SRAM Interface" and "R3 SRAM IMM" sections. Refer to the relevant sections in the External Memory Interface Handbook for the information. Updated the diagram for S/C/Cn/K# pins and s in Arria V GX A and A3 devices to add s on the right, top left, and bottom left, and update the connections to the pins. Updated the term "Multiport logic" to "multi-port front end" (MPFE). Updated for the uartus II software v. release: Restructured chapter. Updated esign Considerations, S Postamble Circuitry, and IOE Registers sections. Added SoC devices information. Added Figure 4, Figure 8, and Figure. Updated Table. Added PHY Clock (PHYCLK) Networks and UniPHY IP sections. Restructured chapter. Initial release.