STM32L0x Ultra Low Power - LCD - DMA - GPIO - RTC

Transcription

1 STM32L0x Ultra Low Power - LCD - DMA - GPIO - RTC MCD Application Team January-2014 V1.0

2 Analog Peripherals LCD GLASS CONTROLLER (LCD)

3 Main features 3 High Flexibility Frame Rates Drive up to 320 (8x40) or 176 (4x44) picture elements (pixels) Programmable duty and bias Duty: Static, 1/2, 1/3, 1/4, 1/8 Bias: Static, 1/2, 1/3, ¼ Low Power Waveform to reduce consumption Frame ~30 Hz to ~100 Hz Software selection between external and internal voltage source Double buffer memory LCD data RAM of up to 16 x 32-bit registers which contain pixel information (active/inactive) Start of frame interrupt to synchronize the software when updating the LCD data RAM. Contrast Control whatever power supply voltage source Blinking programmable pixels and frequency 1, 2, 3, 4, 8 or all pixels at programmable frequency Software adjustable blink frequency to achieve around 0.5 Hz, 1 Hz, 2 Hz or 4 Hz. LCD pins powered by either Step-up converter or VLCD Unused segments and common pins can be used as I/O Full support of Low power modes except Standby mode

4 The LCD Controller (LCDCLK) uses the same clock as RTCCLK. It can be: LSE, LSI, HSE_DIV divided by 1, 2, 4 or 8. The LCDCLK input clock must be in the range of 32 khz to 1MHz. The LCDCLK divided by 2PS[3:0] : ck_ps Frequency generator PCLK1 LSE/LSI/ HSE_Div1/2/4/8 LCD_FCR LCDCLK PS[3:0] 16-bits Prescaler Clock MUX 4 LCDCLK/65536 The ck_ps to be also divided by 16 to 31 to adjust the resolution rate: ck_div f ck_div f LCD flcdclk PS 2 (16 DIV) The frame frequency is obtained from the LCD frequency by dividing it by the number of active common terminals fframe flcd * duty DIV[3:0] ck_ps Divide by 16 to31 ck_div The frame frequency must be selected to be within a range of around ~30 Hz to ~100 Hz

5 Common/Segment driver(1/3) 5 Every common signal has identical waveforms but different phases The common has the maximum amplitude VLCD or VSS only in the corresponding phase of a frame cycle. During the other phases, the signal amplitude is 1/4 VLCD or 3/4 VLCD in case of 1/4 bias or 1/3 VLCD or 2/3 VLCD in case of 1/3 Bias and 1/2 VLCD in case of 1/2 Bias. The first frame generated is the odd one followed by an even one Five Duty ratios can be selected: Static Duty, 1/2 Duty, 1/3 Duty, 1/4 Duty or 1/8 Duty Three modes can be selected: 1/2 Bias, 1/3 Bias or ¼ Bias

6 SEGn COM3 COM2 COM1 COM0 Common/Segment driver(2/3) 6 The segment terminals are multiplexed and each of them controls four pixels V LCD 2/3 V LCD 1/3 V LCD Odd Frame Even Frame A pixel is active if the corresponding segment line gets a maximum voltage opposite to the common V SS V LCD 2/3 V LCD 1/3 V LCD V SS Common signals are phase inverted in order to reduce EMI To activate pixels[n] connected to COM0, SEGn needs to be inactive (V SS ) during phase 0 of an odd frame and active (V LCD ) during phase 0 of an even frame when COM0 is active To deactivate pixels[n+44] connected to COM1, SEGn needs to be active during the phase 1 of an odd frame and inactive during the phase 1 of an even frame when COM1 is active V LCD 2/3 V LCD 1/3 V LCD V SS V LCD 2/3 V LCD 1/3 V LCD V SS V LCD 2/3 V LCD 1/3 V LCD V SS Pixels[n] Pixels[n+44] Pixels[n+88] Pixels[n+132] Pixels[n] Pixels[n+44] Pixels[n+88] Pixels[n+132] RAM refresh RAM refresh LCD RAM LCD RAM Double Buffer Memory: LCD RAM AREA ALWAYS ACCESSIBLE

7 X Common/Segment driver(3/3) 7 Digit 16 Segment A F H G I J K B Example of Writing the character A on the Liquid crystal display first digit COM0 COM1 COM2 E L M N C COM3 D DP SEG0 SEG1 COM0 COM1 COM2 COM3 X F E D I J K N... SEG2 A B C DP COM7 SEG3 H G L M 0x 4 D 7 0 LCD RAM

8 COM0 LCD Contrast Control 8 The contrast can be adjusted using two different methods: 1- Methode1 using external voltage: contrast can be controlled by programming a dead time (up to 8 phase periods) between each couple of frames where the COM and SEG value is tied to Vss in the same time. Odd Frame Even Frame V LCD 2/3 V LCD 1/3 V LCD V SS phase0 phase1 phase2 phase3 3 phase dead time phase0 phase1 phase2 phase3 2- Method 2 when using the internal voltage: the software can adjust V LCD between 2.6 V to 3.3 V in 8 steps

9 Power Consumption 9 The LCD voltage levels can be generated : Internally using an internal booster or externally using V LCD voltage An internal resistor divider network which generates all V LCD intermediate voltages The R L and R H resistive networks are used to increase the current during transitions and to reduce consumption in static state. The nodes provide several intermediate voltage: One (Bias ½), two (Bias 1/3)or three (Bias ¼) The LCD remains active in LP RUN, Sleep, LP sleep, and STOP modes. The LCD is not active in STANDBY mode

10 LCD stabilizing capacitor 10 For MD+ some external capacitor can be used to stabilize intermediate VLCD voltage Signal shape and thus Vrms are improved without the use of High Drive

11 Quiz 11 What is the LCD operation frequency range? Which clock sources can be used to provide the LCD clock? Which values can be written on the LCD RAM registers to write the character F on the LCD first digit? How to adjust the contrast when using an external voltage source? How to adjust the contrast when using an external voltage source?

12 System Peripherals DIRECT MEMORY ACCESS (DMA)

13 DMA Features 7 independently configurable channels: hardware requests or software trigger on each channel. 13 Software programmable priorities: Very high, High, Medium or Low. (Hardware priority in case of equality). Programmable and Independent source and destination transfer data size: Byte, Halfword or Word. 3 event flags for each channel: DMA Half Transfer, DMA Transfer complete and DMA Transfer Error. Memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers and peripheral-to-peripheral transfers. Faulty channel is automatically hardware disabled in case of bus access error. Programmable number of data to be transferred: up to Support for circular buffer management.

14 DMA DMA Requests Mapping 14 Example of L1 MD: DMA controller provides access to 7 channels USART1_TX ADC1 USART3_TX USART3_RX TIM4_CH2 USART1_RX USART2_RX USART2_TX TIM2_CH3 TIM4_CH1 TIM2_UP TIM6_UP/ DAC1 TIM3_CH3 TIM3_CH4 SPI1_TX SPI1_RX TIM7_UP/D AC2 TIM3_UP SPI2_RX I2C2_TX I2C2_RX SPI2_TX TIM2_CH1 TIM3_CH1 TIM4_CH3 I2C1_TX TIM2_CH2 TIM4_UP TIM3_TRIG TIM2_CH4 I2C1_RX OR OR OR OR OR OR OR SW TRIGGER SW TRIGGER SW TRIGGER SW TRIGGER SW TRIGGER SW TRIGGER SW TRIGGER Channel1 Channel2 Channel3 Channel4 Channel5 Channel6 Channel7 High Priority Request Low Priority Request DMA REQUEST All STM32L DMA requests are full compatible with STM32F family

15 DMA Latency: 1 transfer 15 Request 1 Request 2 1 cycle 1 cycle 5 cycles 1 cycle Request1 sample & arbitration phase Address computation Bus access Acknowledgement phase Request2 sample & arbitration phase 8 cycles for each request (source and destination on AHB) If source or destination is a peripheral on APB, Bus access will include more cycles due to the AHB/APB bridge latency and APB transfer duration, depending on the AHB/APB ratio. APB:AHB = 1:1 -> + 2 cycles => total = 10 cycles APB:AHB = 1:2 -> cycles => total = cycles If the CPU is running, the DMA access (AHB or APB) may be delayed by 1 bus cycle on each of the buses For RAM access, any read after write access takes 1 extra cycle Example: APB:AHB = 1:1,DMA APB->AHB transfer and CPU is only accessing RAM (no APB access) The maximum latency between 2 DMA accesses will be 12 cycles 15

16 DMA Latency: 2 transfers 16 To improve the DMA performances, a new request can be served while the previous one is running : if a request is active and other ones are pending, the new request sample & arbitration phase is performed during AHB bus access of the current request. The winning request AHB bus access will start immediately after the end of the current request s AHB Bus access. HCLK Ch. 1 Request sample & arb. phase Addr. compu tation Bus access Ack. phase Request sample & arb. phase Addr. compu tation Bus access Ch. 2 Request sample & arb. phase Addr. compu tation Bus access Ack. phase if source or destination is on APB, the transfer takes more cycles (+ 2 cycles for APB:AHB = 1:1) 16

17 DMA and Bus occupation 17 Request, arbitration and acknowledgement operations are done outside AHB system bus, so the bus is not occupied during those phases One DMA access takes 2 cycles (on AHB): the system Bus can not be totally freeze by DMA as at least 3 cycles are left to the CPU during one DMA transaction. AHB Control Bus free for CPU Read Bus access Write Bus access Current DMA controller compared to others which permit burst transfer have nearly the same system bus occupation rate. However, it doesn t freeze the bus for many cycles consecutively as it is the case with the burst mode: better performance with many small data transfer without blocking the bus 17

18 Quiz 18 How many DMA Channels are available in the STM32L15x? List the peripherals which have a DMA interface? How many interrupts can be generated for each channel? Which Channel is able to perform Memory to Memory transfer? 18

19 System Peripherals GENERAL-PURPOSE I/OS (GPIO)

20 GPIO features Up to 51 multifunction bi-directional I/O ports available: 83% IO ratio Almost standard I/Os are 5V tolerant* 20 All Standard I/Os are shared in 6 ports (GPIOA..GPIOF) Atomic Bit Set and Bit Reset using BSRR register GPIO connected to AHB bus: max toggling frequency = f AHB /2 = 16 MHz Configurable Output Speed up to 40 MHz Ultralow leakage per I/O: 50 na max temperature) Up to 51 GPIOs can be set-up as external interrupt (up to 16 lines at time) able to wake-up the MCU from low power STOP mode. Three I/Os (PA0, PC13 and PE6) can be used as Wake-Up sources from STANDBY mode, and as Tamper Pin (PA0, PC13 and PE6) to reset back-up registers One I/O (PC13) can be set-up TimeStamp, RTC Alarm Output, RTC Wakeup Output or RTC Clock output 20

21 Bit Set/Reset Register Output Data Register Pull - Down I/O pin Input Data Register Pull - Up GPIO Configuration Modes 21 Analog MODER(i) [1:0] OTYPER(i) [1:0] PUPDR(i) [1:0] I/O configuration Alternate Function Input To On-chip Peripherals Output Push Pull 0 1 Output Push Pull with Pull-up 1 0 Output Push Pull with Pull-down 0 0 Output Open Drain 0 1 Output Open Drain with Pull-up 1 0 Output Open Drain with Pull-down Read 0 On Off Schmitt VDD VDD or VDD_FT (1) On/Off Alternate Function Push Pull 0 1 Alternate Function PP Pull-up 1 0 Alternate Function PP Pull-down Trigger Input Driver x 0 0 Alternate Function Open Drain 0 1 Alternate Function OD Pull-up 1 0 Alternate Function OD Pull-down 0 0 Input floating 0 1 Input with Pull-up 1 0 Input with Pull-down Write OUTPUT CONTROL VDD On/Off VSS VSS 11 x x Analog mode Read / Write From On-chip Peripherals Alternate Function Output Output Driver VSS Push-Pull Open Drain * In output mode, the I/O speed is configurable through OSPEEDR register: 400kHz, 2MHz, 10MHz or 40 MHz Analog (1) VDD_FT is a potential specific to five-volt tolerant I/Os and different from VDD. 21

22 Alternate Functions features Most of the I/O pins are shared with Alternate Functions pins (like USARTx_Tx, TIMx_CH2, I2Cx_SCL, SPIx_MISO, USBDM, EVENTOUT ) 22 Some Alternate function can be remapped in different pins allowing optimization of the pin out Alternate functions can be connected to onboard peripherals through a multiplexer that allows only one peripheral s alternate function to be connected to an I/O pin at a time. AF0 (system) AF1 (TIM2) AF2 (TIM3/TIM4) Pin x (0 15) AF15 (EVENTOUT) In this way, there can be no conflict between peripherals sharing the same I/O pin. Refer to the Alternate function input/output table in the STM32L15xxx datasheet for peripherals alternate function I/O pins mapping 22

23 GPIO Configuration procedure System function (JTAG/SWD, TAMPER, TIMESTAMP and CALIB, RTC_50Hz, MCO) you have to connect the I/O to AF0 (default) and configure it depending on the function used. 23 GPIO configure the desired I/O as output, input or analog in the GPIOx_MODER register. Peripheral s alternate function For the ADC and DAC, configure the desired I/O as analog in the GPIOx_MODER register. For other peripherals: Configure the desired I/O as an alternate function in the GPIOx_MODER register Select the type, pull-up/pull-down and output speed via the GPIOx_OTYPER, GPIOx_PUPDR and GPIOx_OSPEEDER registers, respectively Connect the I/O to the desired AFx in the GPIOx_AFRL or GPIOx_AFRH register EVENTOUT you can configure the I/O pin used to output the Cortex-M3 EVENTOUT signal by connecting it to AF15 23

24 STM32L0 System Peripherals Real-Time Clock (RTC)

25 RTC Features (1/2) 25 Calendar with Sub seconds, seconds, minutes, hours, week day, date, month, and year. Daylight saving compensation programmable by software Two programmable alarms with interrupt function. The alarms can be triggered by any combination of the calendar fields. A periodic flag triggering an automatic wakeup interrupt. This flag is issued by a 16-bit auto-reload timer with programmable resolution. This timer is also called wakeup timer. A second clock source (50 or 60Hz) can be used to update the calendar. Maskable interrupts/events: Alarm A, Alarm B, Wakeup interrupt, Time-stamp, 2 Tamper detection Digital calibration circuit (periodic counter correction) to achieve 0.95 ppm accuracy Time-stamp function for event saving with sub second precision (1 event) Up to 20 backup registers (80 bytes) which are reset when an tamper detection event occurs. Presentation Title 21/07/2014

26 Alternate function outputs: RTC Features (2/2) 26 RTC_CALIB: 512 Hz or 1Hz clock output (with an LSE frequency of khz). It is routed to the device RTC_OUT output. RTC_ALARM: Alarm A, B, wakeup flag output. It is routed to the device RTC_OUT output. Alternate function inputs: RTC_TAMP1: tamper1 event detection. RTC_TAMP2: tamper2 event detection. RTC_TS: timestamp event detection. RTC_REFIN: reference clock input. The RTC clock source could be any of the following three: LSE oscillator clock. LSI oscillator clock. HSE divided by 2, 4, 8 or 16 in clock controller. Presentation Title 21/07/2014

27 RTC overview (1/2) 27 STM32L0 Calendar in BCD Calendar Subseconds access Calendar synchronization on the fly Alarm on calendar YES YES Resolution down to RTCCLK YES 2 w/ subseconds Calendar Calibration Calib window : 8s/16s/32s Calibration step: 3.81ppm/1.91ppm/0.95 ppm Range [-480ppm +480ppm] Calendar Calibration on the fly YES

28 RTC overview (2/2) STM32L0 Synchronization on mains YES Periodic wakeup Timestamp Tamper YES YES Sec, Min, Hour, Date, Sub seconds YES 2 pins/ 2 events Level Detection with Configurable filtering 32-bit Backup registers 5

29 RTC Block Diagram RTC_TAMP1 RTC_TAMP2 Backup Registers and RTC Tamper Control registers Tamper Flag HSE / 2,4,8,16 RTC_TS RTC_REFIN LSE LSI Asynchronous 7bit Prescaler RTCSEL [1:0] RTCCLK Coarse Calibration Smooth Calibration Calendar ssr (binary format) Synchronous 15bit Prescaler PREDIV_A [6:0] PREDIV_S [14:0] 1 Hz Alarm B ssr, ss, mm, HH/date Calendar Day/date/month/year Alarm A ssr, ss, mm, HH/date HH:mm:ss (12/24 format) TimeStamp Registers = = TimeStamp Flag Alarm B Flag Alarm A Flag RTC_ALARM 512 Hz WUCKSEL [2:0] COSEL Wake-Up 16bit autoreload Timer RTC_CALIB Periodic wake up Flag

30 RTC registers write protection By default and after reset, the RTC registers are write protected to avoid possible parasitic write accesses. DBP bit must be set in PWR_CR to enable RTC write access A Key must be written in RTC_WPR register. To unlock write protection on all RTC registers 1. Write 0xCA into the RTC_WPR register 2. Write 0x53 into the RTC_WPR register * Except for the clear of Alarm and Wakeup timer interrupt flags Writing a wrong key reactivates the write protection.

31 RTC Clock Sources 31 The RTC has two clock sources: RTCCLK used for RTC timer/counter, can be either the HSE/2, 4, 8 or 16, LSE or LSI clocks. PCLK1 used for RTC register read/write access. Before to start using the RTC you have to program the clock controller : Configure and Enable the RTCCLK source in the RCC_BDCR register 31

32 RTC in Low Power Modes and in Reset 32 The RTC remains active what ever the low power mode Sleep, Low Power Run, Low Power Sleep, STOP, STANDBY When enabled, 7 events can exit the device from low power modes: Alarm A Alarm B Wakeup Tamper 1/ 2 / 3 TimeStamp The RTC remains active under Reset except at Power-on Reset The RTC configuration registers including prescaler programming are not affected by system Reset else than Power-on Reset. When clocked by LSE, the RTC clock is not stopped under Reset, except power-on reset. 32

33 RTC Calendar (1/4) The initialization or the reading of the calendar value is done through 3 shadow registers, SSR, TR and DR. The RTC TR and DR registers are in BCD format. 33 SSR register represents the RTC Sub seconds register Calendar Actual registers Date Day : Month : Date : Year 12h or 24h format Time HH : mm : ss : ssr Shadow registers DR TR SSR 33

34 RTC calendar (2/4) 34 RTC initialization : Enter in initialization phase mode by setting the INIT bit in ISR register This mode is confirmed with the INITF flag also in ISR register Program the prescaler register (PRER) according to the clock source to get 1Hz clock to the calendar. Load the initial date values in the 2 shadow registers (TR, DR). And other configuration registers like RTC_CR (hour format, ) Exit the initialization phase clearing INIT bit. The actual calendar register are then automatically loaded and the counting restarts after few RTCCLK clock periods. After reset the check of the INITS flag in ISR register indicates if the calendar is already initialized (year not at zero) or not (like after Power-on). To manage the daylight saving there are 3 bits in CR: SUB1H or ADD1H to subtract or add one hour to the calendar BCK to memorize above action 34

35 RTC calendar (3/4) 35 The shadow registers are automatically updated each time the RTCCLK clock is synchronized with System Clock. The calendar read can be done in 2 different modes : BYPSHAD=0 : Read shadow registers RSF flag in ISR register is used to ensure that the calendar value from shadow register is the up-to-date one. Update of DR is frozen after reading TR, and unfrozen when DR is read. Update of TR and DR is frozen after reading SSR, and unfrozen when DR is read. BYPSHAD=1 : Bypass shadow registers Reading calendar makes direct access to the calendar counters Software must read all calendar registers twice and compare the results to ensure that the data are coherent and correct. 35

36 RTC calendar (4/4) 36 Calendar can be synchronized up to 1s on the fly by adding/subtracting an offset with the sub second resolution. Allow synchronization to remote clock Reference Clock detection: A more precise second source clock (like mains 50 or 60 Hz) can be used to enhance the long-term precision of the calendar: The second source clock is automatically detected and used to update the calendar The LSE clock is automatically used to update the calendar whenever the second source clock becomes unavailable Timestamp : Calendar value (including sub-seconds) is saved in Timestamp registers on external I/O event 36

37 RTC Programmable Alarm 2 Full programmable Alarms 37 Able to exit the device from STOP/STANDBY modes. Alarms event can also be routed to the specific output pin RTC_OUT with configurable polarity. The Alarm flags are set if the calendar sub seconds, seconds, minutes, hours or date match the value programmed in the alarm registers ( ALRMASSR & ALRMAR, ALRMBSSR & ALRMBR). Calendar sub second, seconds, minutes, hours or date fields can be independently selected (maskable or not maskable). 37

38 WakeUp configuration (1/3) The periodic wakeup flag is generated by a 16-bit programmable binary auto-reload down counter (WUTR registers) 38 Able to exit the device from STANDBY modes. The wakeup clock source selection is done via WUCKSEL [2:0] bits in control register RTC_CR (to program these bits the auto wakeup must be deactivated, WUTE=0). 3 possible cases are possible: Case1 WUCKSEL = 0xx RTCCLK Asynchrone 4bit Prescaler Wake-Up WakeUpCLK WUCKSEL[2:0] ValueMax = div16 ValueMin = div2 WakeUpCLKmin = RTCCLK/(2 x (0x )) => 122µs WakeUpCLKmax = RTCCLK/(16 x (0xFFFF + 1)) => 32s 16bit autoreload Timer ValueMax = 0xFFFF ValueMin = 0x0000 Periodic wake up Flag RTCCLK = KHz Resolution min=2xrtcclk=61µs 38

39 Case2 WUCKSEL = 10x WakeUp configuration (2/3) 39 RTCCLK Asynchrone 7bit Prescaler ValueMax = div 2 7 = 128 (power-on reset value) ValueMin = 1 Synchrone 15bit Prescaler Wake-Up ValueMax = div 2 15 ValueMin = 1 Power-on reset value =256 ck_spre WakeUpCLK 16bit autoreload Timer ValueMax = 0xFFFF ValueMin = 0x0000 Periodic Wakeup Flag WakeUpCLKmin = RTCCLK/(1 x (0x )) WakeUpCLKmax = RTCCLK/(2 22 x (0xFFFF + 1)) If ck_spre is 1Hz (when used for calendar): 1s <= WakeUpCLK <= 18.2h (1s resolution) 39

40 WakeUp configuration (3/3) 40 Case3 WUCKSEL = 11x RTCCLK Asynchrone 7bit Prescaler ValueMax = div 2 7 ValueMin = 1 Synchrone 13bit Prescaler ValueMax = div 2 15 ValueMin = 1 ck_spre Wake-Up WakeUpCLK 16bit autoreload Timer ValueMax = 0xFFFF ValueMin = 0x0000 Periodic Wake-up Flag WakeUpCLKmin = RTCCLK/(1 x (0x )) WakeUpCLKmax = RTCCLK/(2 22 x (0x1FFFF + 1)) If ck_spre is 1Hz (when used for calendar): 18.2s <= WakeUpCLK <= 36.4h (1s resolution) 40

41 Smooth digital calibration 41 Consists in masking/adding N (configurable) 32KHz clock pulses, fairly well distributed in a configurable window. A 1Hz output is provided to measure the quartz frequency and the calibration result. Calibration value can be changed on the fly. Calibration window Accuracy Total range 8 s ±1.91 ppm [0 ±480ppm] 16s ±0.95 ppm [0 ±480ppm] 32s ±0.48 ppm [0 ±480ppm]

42 Coarse digital calibration Consists in masking/adding N (configurable) clock cycles at the output of the asynchronous prescaler. 42 The correction is made once per minute, during a programmed number of minutes is a 64-minutes window. The calibration value must be programmed when the RTC is in initialization mode, and cannot be changed when the RTC is running. Calibration window Accuracy 64 min ± 1ppm in positive calibration ± 2ppm in negative calibration Total range [-63ppm +126ppm]

43 Tamper detection 43 Tamper switch RTC_TAMPx STM32 3 tamper pins and events Configurable active level for each event Configurable use of I/Os pull-up resistors Capacitor is optional (filtering can be done by software) Biasing is done using the I/O s Pullup resistor Configurable pre-charging pulse to support different capacitance values 1, 2, 4 or 8 cycles Configurable filter: Sampling rate : 128Hz, 64Hz, 32Hz, 16Hz, 8Hz, 4Hz, 2Hz, 1Hz Number of consecutive identical events before issuing an interrupt to wake-up the MCU : 1, 2, 4, 8 Reset of backup registers when tamper event detected Tamper event can generate a timestamp event

44 Tamper detection - signals 44 Clock Floating input (Not connected) Switch opened Input voltage sampling is done here Voltage on Tamper Detect Input 1 cycle pre-charge 2 cycles pre-charge 4 cycles pre-charge (8 cycles not shown) Switch closed

45 Pin configuration and function RTC output pin RTC_AF1 (PC13) AFO_ALARM enabled AFO_CALIB enabled Tamper enabled Time-Stamp enabled EWUP2 enabled ALARMOUTTYPE AFO_ALRM configuration Alarm out output OD 1 0 Don t care Don t care Don t care 0 Alarm out output PP 1 0 Don t care Don t care Don t care 1 Calibration out output PP 0 1 Don t care Don t care Don t care Don t care TIMESTAMP input floating Don t care Don t care Tamper input floating Don t care Don t care 45 TIMESTAMP & Tamper input floating Wakeup Pin Don t care Don t care Don t care Standard GPIO Don t care 45

46 Quiz 46 What are the different RTC clock sources? What are the different RTC interrupts? What is the maximum RTC Sub second (RTC_SSR) resolution? How many RTC Backup Registers are available? Presentation Title 21/07/2014

47 Thank you