In this section, we are going to cover the Silicon Labs CP240x family features.

Transcription

1 In this section, we are going to cover the Silicon Labs CP240x family features. 1

2 We are going to look at the new CP240x devices in this module. We will first take a look at the high level block diagram and then dive into some of the new features of these devices that make them excellent choices for a wide range of applications. 2

3 The CP240x is a standalone, fixed-function LCD driver that generates the drive signals for any static or multiplexed l LCD. The CP240x has been designed d to interface directly to the C8051F91x/0x (or any other MCU) via a standard SPI or SMBus/I2C interface. The CP2400 & CP pin devices can control up to 128 LCD segments while the CP2402 & CP pin devices can control up to 64 LCD segments. Most importantly, the CP240x family has been designed with low power in mind when paired with the F91x/0x, the combined solution from Silicon Labs offers the industry s lowest power solution for LCD apps. Other CP240x features that customers may find valuable include: Integrated low drop out (LDO) voltage regulator to maintain ultra-low active current at all voltages 4 power modes that can be used to minimize overall power consumption (idle mode, ultra low power LCD mode, ultra low power smartclock mode, shut down mode) Low power blink capability 256 bytes of general purpose RAM that can expand the memory available to the host controller The CP240x family is supported by the CP2400 (SPI) and CP2401 (I2C) Development Kits. The development kit is a full featured tool designed to test the complete functionality of the device. Both kits include a 128-segment alpha-numeric LCD development board, a C8051F930 target board, quick start guide, evaluation version of Keil 8051 development tools, USB debug adaptor, power adaptor, USB cables, and AAA batteries. 3

4 In this training module we are going to cover the operation of Liquid Crystal Displays (LCD) and how to drive them. In particular, we will focus our attention on segmented LCDs. If you are already familiar with LCD operation you can skip the introductory section and learn about the Silicon Labs LCD controller solution. 4

5 First we will take a look at some terms related to LCDs. The most important terms to understand are the concept of segments and backplanes or commons. The segment is the actual element on the display that is visible to the operator of the end equipment. The segment makes up one electrode and is referenced to a backplane or common electrode. These two electrodes, when provided with a voltage potential, generate the electric field that causes the liquid crystals to change their orientation which in turn block the light. Take a few minutes to review the terms shown. 5

6 Now let s take a look at the construction of a typical segmented display. There are several layers that make up the display shown in the illustration. The first layer is a vertical polarizer that only allows a single axis of light to pass. Following the polarizer is the glass substrate with the ITO segments. The third layer is the actual liquid crystal material used to twist the light. The fourth layer is the glass substrate with an ITO film used as the common reference for the ITO segments. After the common there is another polarizer, this time oriented to allow only light waves in the horizontal plane to pass. This is 90 degrees out of phase with the first polarizer. Beyond the polarizer is the light source. This is either a reflective surface to bounce the incoming light through the display or it can be a backlight. All of the layers are transparent and serve a specific function in passing the light through the display. Next we will take a look at the different technologies involved in making the display work. 6

7 The fact that light is an electromagnetic wave that is visible to the eye is one basic principle that liquid crystal displays are based. Light sources emit the light waves in numerous directions or axis as represented by the series of arrows originating from the source shown above. Adding to that, each wave can be broken down to its orthogonal components meaning that each vector has a vertical and horizontal component to them. If you were to examine a wave completely aligned on the vertical axis its horizontal component would be 0. The reverse is also true regarding a wave aligned on the horizontal axis. Its vertical component is 0. Polarization relates to the orientation of the light waves and a polarizing filter allows only waves aligned on the specific axis to pass. In the diagram above we see the result of two polarizing filters oriented 90 degrees out of phase. Placing these in the path of the light source we see that the first filter passes only the light waves that have a vertical orientation. As these waves hit the second filter that only passes horizontal waves we will block the remaining light since that vertical waves have no horizontal component. 7

8 Indium Tin Oxide (ITO) is a transparent material that is also conductive. This material is used to create the electrodes to stimulate the liquid crystal material. The ITO is put on one layer of glass in any shape required by the application. Another layer of glass will have ITO used for the common reference. For example, in the picture provided each segment is a separate application of ITO. All of the segments combined make up the basis for the alphanumeric characters and how the segments are driven determines what letter or number we see. Some common segment shapes that might exist are an antenna found on a cell phone, or the strength indicator bars. A battery symbol is also common on many LCDs. 8

9 We now know that light is an electromagnetic wave and that we can use a polarizing filter to provide a single axis. How is that concept used in building a display? We haven t talked about the liquid crystal material yet, but this is where it becomes important. Liquid crystals will orient themselves based on how the material has been deposited on the glass surfaces that it is bounded by. If the surfaces provide a 90 degree twist then the crystals, in their steady state will twist 90 degrees as well. The crystals also allow the light to propagate through so the light wave orientation can twist as well. Now if we have the two polarizing filters that are oriented 90 degrees out of phase and we put the liquid crystal in between with a 90 degree twist we can get the horizontally polarized light to pass through the vertical filter. That is the steady state condition. When we generate an electric field using the ITO segments then the liquid crystal will align with the generated field. We no longer change the light waves orientation and the vertical filter now blocks the horizontally polarized light. At this point the segment has no light and appears dark. This is considered the on condition. 9

10 Now that we covered the theory behind how liquid crystal displays work we can focus on how we use them. There are different methods used to drive the ITO segments in order to generate the electric field across the liquid crystal material: static and multiplexed. The first method and the simplest to understand is the static drive mode which means each ITO segment of the display has only one connection to the controller. All segments are also referenced to a single common. This mode increases the pin count required to drive the display but it is simpler to create the drive waveforms. In the example shown above, we see a single alphanumeric character with the listed segment names, 8A, 8B etc. As each pin connected to these segments is active, in addition to the backplane/common reference, the field will be generated and the segment will turn ON. 10

11 Now that the segments are connected we have to generate the voltage to drive them. For the LCD to operate correctly and to preserve the life of the display the resulting voltage to the segment is AC with a 0V DC component. The LCD controller generates the waveforms used to drive the segments of the display. The output voltage is the difference between the common waveform and the intermediate segment waveform. In the example above, the ON condition is shown and is the result of subtracting the segment from the common as shown in the 0V DC biased waveform. 11

12 Silicon Labs devices (MCU and fixed function) integrate an LCD controller that generates the waveforms required by the display. The controller has its own ultralow power memory that is used to map the segments of the display. Each bit in the memory array represents a segment and backplane/common combination. The picture shown above to the left shows the ULP memory array. We mentioned that static mode uses a single common and is denoted as COM0 so only the bits that are referenced with COM0 get used. From the figure we see that these are bits 0 and 4 at each memory location. For example, if we want to turn on the segment connected to pin 21 of the device we would set bit 4 at address ULPMEM10. In the example above the actual display segment mapping is shown on the right. If pin 21 of the controller is connected to pin 21 of the display then segment 8A would be turned on. 12

13 In order to reduce pin counts of displays and the controllers used to drive them a multiplex scheme is used. Unlike the static mode, a multiplexed display connects multiple segments together as shown in the figure. Here we see that there are 4 segments connected together and is called 4-mux mode. In addition, a multiplexed mode display also has multiple common references and the number of commons is equal to the mux mode. In the figure we see that there are 4 commons. Each of the four segments that are connected to a single pin such as 8A, 8B, 8C, and DP8, is referenced to one of the four commons. In the figure DP8 is referenced to COM0 whereas 8C is referenced to COM1. 13

14 The output signaling for a multiplexed display is much more involved than that of the static display due to the shared relationship between the segments and the commons. We can no longer use the simple square wave output and need to generate a multi-level output signal that when combined with the common generates the 0V DC biased stair stepped AC signal. This stair stepped signal is a time division multiplexed signal with the number of intervals within the frame is 2 times the mux mode. In this example we show a 3 mux output and you can see there are 6 intervals within the frame. 14

15 In order to generate the voltage levels for the stair stepped signal the LCD controller needs to generate the intermediate voltages. On Silicon Labs devices this is generated from an integrated charge pump and a divider network. An equivalent circuit is shown in the diagram. 15

16 Here we see the ULP memory map again. In our static mode example we only had one common and therefore only used bit positions 0 and 4. With multiplexing, and in particular the 4 mux mode as shown, we can use all memory locations as each bit position is associated with one of the 4 commons. Bit position 0 is associated with COM0, bit position 1 is associated with COM1 and so on. Take a look at segment 8B in the display mapping in the figure on the right for example. This segment is referenced to COM2 and pin 21. Since we have set the LCD controller pin numbers to be the same as the display pin numbers for this example, segment 8B is mapped to bit position 6 at address ULPMEM10. Other multiplexing modes are available such as 3 mux. In this case COM3 bit positions would not be used. 16

17 When we write a 1 to a bit in the ULP memory array the segment connected to that pin will turn on. In this animation the black boxes represent a 1 and the red boxes denote a 0. As we write a 1 to the memory the associated segment generates the electric field aligning the liquid crystals and the polarizer blocks the light and we see the segment turn dark or on. 17

18 Now that we have learned the different aspects of how liquid crystal displays work and their use let s do a quick review. First, the firmware is running and needs to send the number 0 to the first alphanumeric character. The data is written to the ULP memory array that is associated with the segments that form the 0 (the A, B, C, D, E an F segments need to be written to a 1 denoted by the black box). In this example we are writing to ULPMEM00 which controls the outputs on pins LCD0 and LCD1. Next we have connected the LCD controllers outputs to the LCD itself. You can see from step three above that the schematic for this board connects LCD0 to pin 35 of the display and LCD1 to pin 1 of the display and the commons are also connected between the controller and the display. COM0 connects to COM0 and so on up through COM3. Each display manufacturer will provide a segment mapping with the pins and the commons. Step four shows how the segments were mapped on this particular display. Knowing LCD0 connects to pin 36 we can look at the segments listed and see that referencing COM0 drives the decimal point, referencing COM1 drives the C segment, COM2 drives the B segment and COM3 drives the A segment. Similarly, LCD1 connects to the D, E, F and apostrophe segments. Therefore, Writing the value 0x7E to the ULPMEM00 address will set all of the required segments on to have the number 0 displayed. 18

19 So how do we set up our firmware to write the characters to the display? Here we see one possible solution. First we can define where in the memory array the associated segment will be based on our pin connections and the actual display segment map as we have seen on the previous slide. In this particular example, the A segment will be controlled by the bit 4 position. Likewise, the B segment is controlled by the bit 5 position. All of these bit mappings are derived based on the way the LCD controller and the display are connected. To simplify generating the characters we can provide an array of the values to write to the memory that turns on all of the segments required to create the complete character. From our last example we created the number 0 which uses all of the outer segments A through F and when ORing these in this example provides the value 0xE070. We then write out the 0 index into the array to send the data representing the alphanumeric character 0. 19

20 The Silicon Labs integrated LCD controller contains an LCD segment driver and on-chip bias generation that supports static, 2-mux, 3- mux and 4-mux LCDs with 1/2 or 1/3 bias. The on-chip charge pump with programmable output voltage allows software contrast control which is independent of the VDD supply voltage. LCD timing is derived from the smartclock oscillator to allow precise control over the refresh rate. A low frequency clock present on the CLK pin may also be used as the LCD clock source. The CP240x contains on-chip ULP memory to store the enabled/disabled state of individual LCD segments. All LCD waveforms are generated on-chip and software only needs to access the ULP memory to change the information displayed on the LCD. An LCD blinking function is also supported. 20

21 Here we see the steps used to configure and use the LCD controller. We will cover each of these steps on the following slides. The first thing we have to do is set up the LCD controller mode. 21

22 To set the mode we use the LCD Control Register (LCD0CN). Here we can select the number of segments, the display mode for static ti or multiplexed l mode and the internal bias generation. 22

23 Contrast (or contrast ratio) of a liquid crystal display is the ratio of the light area of a display to the dark area and gives an indication of the ability to see each segment. Varying the bias voltage to the display will change the contrast and each application should provide the capability for adjustments to be made. 23

24 The bias generation for the Silicon Labs LCD controller is also integrated and is programmable in 60 mv steps. The intermediate voltages are also generated on chip which eliminates the need to provide the resistor string commonly found on other devices. We can change the contrast using the CNTRST bits in the CONTRAST register. 24

25 After writing a reserved value to the display we can then set the timing. As mentioned previously, the segment drive waveforms are AC and the frequency of these outputs affect display operation. The LCD controller provides the capability to vary the refresh rate and the rate at which the display can blink certain segments. 25

26 The timing of the segment driver outputs affect the overall appearance of the display and the life of the display in addition to affecting the system power consumption. A refresh rate too slow might make the display appear to flicker, whereas a rate too fast might cause it to not appear correctly. The display can be viewed as a capacitive load and its power consumption is then affected by the rate at which of the transitions of the segments similar to IC power consumption. A faster clock increases power consumption for an MCU for example and similarly running the refresh rate of the display too fast causes and unnecessary increase in supply current. All of the timing components required to drive the display are integrated into the IC. The LCD controller can be clocked from the smartclock oscillator or from an external source. Once the smartclock oscillator is set up the refresh rate is determined by the equation shown above. Note that the rate is always divided by 2 times the number of muxes. Remember from our discussion on the waveform outputs, there are always two cycles with the number of steps equal to the mux value to provide the 0V DC biased AC signal. The LCDDIV value is determined via configuration of two registers: LCD0DIVL and LCD0DIVH. 26

27 Blinking a display requires setting a fixed time interval and toggling the segment outputs of the associated blinked segments. Typically this was done with CPU overhead to set a time base and then using firmware to toggle the segment ON and OFF. That method has the disadvantage of requiring CPU overhead and increasing power consumption. The LCD controller in Silicon Labs devices provides the capability to blink segments via hardware greatly reducing the system power consumption. The rate at which segments blink is a function of the refresh rate and is set using the LCD0TOGR register. The equation for the toggle (blink) rate is shown above and is set using the lower 4 bits of the toggle register. The number of segments that can be blinked is dependent on the mode used. There is only one memory location that is used to set which segments blink, ULPMEM00, which represents at most 8 segments. Therefore, when in static mode two segments can blink since there are only two segments referenced to COM0 in ULPMEM00, bit 0 and bit 4. When using the 4 mux mode all bits in ULPMEM00 represent a segment so a total of 8 segments can be blinked. The LCD0BLINK register provides a mask to set the segments in the LCD0 and LCD1 ULP memory area that will blink. If a LCD0BLINK bit is set then the segment will blink at the rate specified in the TOGR bits. 27

28 Now that the LCD controller is configured we can now write the segment data to the ULP memory. As we covered previously each data bit in the memory map represents a segment on the display according to how the devices are connected together. 28

29 Once the data is written the LCD controller needs to be enabled. Enable the LCD controller by setting the LCDEN in the master control register (MSCN). 29

30 After setting LCDEN the segments should now be visible on the display as the controller is generating the required drive voltages and frequency to generate the electric fields required to excite the liquid crystal material. 30

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33 The clock system of the CP240x family is composed of three different sources. The internal oscillator is a 20 MHz source that us used by default out of reset. The smartclock oscillator can be used to wake the device periodically so that it can perform the display functions. Alternatively, an external clock source can be used to drive the device. 33

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35 The power modes above are achieved by disabling specific primary functions of the CP240x. The figure shows how power is distributed throughout the CP240x. Additional secondary functions may also be disabled to save power. Normal mode should be used whenever the host controller is communicating with the CP240x. In this mode, the device is fully functional and the host interface is capable of operating at full speed. In RAM Preservation Mode, the internal oscillator is disabled and the SmaRTClock oscillator provides the system clock. RAM Preservation Mode should be used when the CP240x needs to be active for a prolonged period of time in which communication with the host microcontroller is not required. In Ultra Low Power LCD Mode, the on-chip LDO is placed in a low power state and power is gated off from all digital logic residing outside the ULP block. The ULP block allows the device to refresh an LCD, maintain a real time clock, detect SmaRTClock Alarm, SmaRTClock Oscillator Fail, and ULP Port Match events. In Ultra Low Power SmaRTClock Mode, the on-chip LDO is placed in a low power state and power is gated off from all digital logic residing outside the ULP block and LCD functionality is disabled. The ULP block allows the device to maintain a real time clock and detect SmaRTClock Alarm, SmaRTClock Oscillator Fail, and ULP Port Match events. Shutdown mode is the lowest power mode for the CP240x. All device functionality is disabled in this mode and a reset is required to wake up the device. This mode is typically used when the device is not needed for prolonged periods of time. 35

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37 The SMBus and IIC bus are widely used interfaces for many peripheral devices. An example of an IIC device is a temperature sensor. The configuration and reading of the data is determined by a protocol that sends an address and read or write control and then transfers data. The interface is based on an open drain two wire network where there can be multiple masters and slaves. Each device on the bus must be able to release the bus when not in use. The master device always initiates the communications to the addressed slave device. 37

38 This is an illustration of what an IIC bus looks like. Essentially it is a multi-master bus with an underlying protocol. Data direction i outlined above is based on what the bus cycle is and who the master is. Once a master gets control of the bus then all other devices become slaves as there can be only one master. I2C is based on peripheral addresses. Once a device determines that the message is not for it then it stops activity. We will cover this later. There are arbitration schemes for collision detection which we will get into soon as well. An I2C master addresses the peripheral and provides the cycle type, whether it is a read or write. For a write the master then puts out the data on the bus for the slave to accept. For a read the slave then takes over the bus and drives the data. The master always drives the clock on the I2C bus. I2C is also provides a level of error checking. It communicates with an ACK/NACK protocol. If the master or slave did not receive the data correctly or for some reason cannot accept the data it can NACK the transfer. All of the ACK and NACK is based on the bit timing. The ACK/NACK is generated in the 9 th bit position. The start and stop bits are also based on timing. These bits are defined ed by the state at the point of transition t of the I2C clock. The legend shows who controls the bus and therefore data direction. 38

39 Typically, the data on SDA must be stable during the HIGH period of the clock. Data can change state only when SCL is low. There are two conditions (START and STOP) where these requirements are not met. A master node initiates a transfer by issuing a start condition on the bus as shown above and at the completion of the transfer it issues the stop condition. START and STOP conditions are always generated by the bus master. After a START condition the bus is considered to be busy. The bus becomes idle again after certain time following a STOP condition or after both the SCL and SDA lines remain high for more than the specified idle time. 39

40 The overall communications between the master and the slave device requires data sequences and acknowledgments throughout the cycle. The red lines indicate when the master device controls the bus and the blue lines indicate when the slave device is driving the bus. Once the master issues the start bit it then drives the address on the bus and then indicates the direction of the transfer (either a read or a write). At that point the addressed slave is required to generate an acknowledgment (drive the bus low) for a bit time. Once the handshake is complete the master either receives or transmits data from/to the slave. To complete the transfer another acknowledgment phase is generated by the receiving device and the master terminates with the stop bit. 40

41 There may exist a condition where the master device needs to switch from the write mode to the read mode for the same overall transfer. Let s look at the temperature example again. Assume we want to read the temperature value. In order to do so we would need to address the slave device and write the command to the device to tell it to set the internal address of the temperature register we want to read. Once the write cycle to write the command to the temperature sensor is complete we then read the data. The master does not have to generate the stop condition and can just generate a repeat start where it drives the SDA line low while SCL is high. 41

42 Arbitration on the SMBus is possible due to the open drain configuration of the drivers. If the output is to be a logic 1 then the output of the drivers are tri-stated and the external pullup resistor determines the logic level. If the output is to be a logic 0 then the output driver is ON and the output is driven to 0V. Therefore, when the output is high any driver on the bus can pull the output low. Let s assume two masters start transmitting at the same time. Whichever device drives the logic 0 bit when the other device wants to drive a logic 1 will win arbitration since the device driving the logic high will tri-state the bus and the other device will keep it driven low. 42

43 Some devices on the bus may not be able to operate at the set speed of the master. A way to slow the bus down to complete transfers successfully is to stretch the clock to allow more time to present the data. 43

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45 The SMBus interface of the CP240x family operates as a slave, and may function on a bus with multiple masters. The SMBus provides control of SDA (serial data), SCL (serial clock) generation and synchronization, arbitration logic, and START/STOP control and generation. The CP240x device is responsible for generating the ACK and NAK responses to the command that issued by the master. 45

46 CP2400/1/2/3 devices can have one of 2 possible 7-bit, left-justified slave addresses: 0x74 and 0x76. The least significant bit of the slave address is set by the SMBA0 pin. The remaining bits in the slave address are fixed. The bit following the least significant address bit is used to indicate whether the current transfer is a read or a write. 46

47 During a write sequence, an SMBus master writes data to a slave device. The slave in this transfer will be a receiver during the address byte, and a receiver during all data bytes and is responsible for generating the associated acknowledge cycles. 47

48 During a read sequence, an SMBus master reads data from a slave device. The slave in this transfer will be a receiver during the address byte, and a transmitter during all data bytes. The slave device is responsible for acknowledging the address and sending the required data bytes requested by the master. 48

49 Here we see the configuration register for the SMBus module. 49

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51 We are going to look the serial peripheral interface, or SPI, which is a synchronous serial communications interface. The SPI implementation consists of a shift register for the receive and transmit data directions. There are typically additional data registers for both the transmit and receive directions to provide double buffering to reduce the probability of data loss. As the device transmits the data the receive data stream is latched using the same clock source providing a full duplex operation (data transmit and receive are on separate pins). Some implementations may use a half duplex configuration where the data is transmitted and received on a single wire. The master node generates the clock for the interface and the slave device accepts the clock. Both devices are required to be configured for the same clock rates and phase. For example, if data was to be transmitted at 100kbps and the data is valid on the rising clock then the master needs to pass the data and have it stable when the clock rises and the slave has to be able to latch the data on the same edge of the clock. Looking at the signalling of the SPI interface we see some standard naming conventions. MOSI is the Master Out Slave In and is the data transmitted from the master device to a slave device. It is configured through the I/O as a push-pull output. The MISO signal is the Master In Slave Out and is the data received by the master. The I/O for these pins should be set as inputs. The SCK is the clock signal and the NSS is the slave select (or chip select) signal to enable the active slave device. 51

52 Parallel communications has a wide data bus typically 8 bits or more. The data bits are sent out together in conjunction with a clock and control signaling and the interfaces require high pin count depending on the width of the data bus. With serial data we are referring to transmitting each bit one after the other over a single wire. These interfaces require low pin counts since only one pin is required to transmit or receive data. The CP240x devices use a synchronous serial interface (clock is sourced with the data) called SPI. You can see from the diagram that the synchronous serial interface provides a clock with the data. The transmitter drives data out the pin on one edge of the clock and the receiver latches data on the following edge. 52

53 The CP240x device uses the configuration for the SPI interface shown. It will always be the slave device to the master SPI node. The CP240x uses a 4 wire connection scheme that includes the chip select signal as typically found in a single master multiple salve topology. In this configuration each slave device has its own chip select and when driven it is allowed to drive the MISO pins and all other inactive devices tri-state the pin. 53

54 In order for SPI devices to communicate it is required that they be configured to operate in the same manner. Since the master device drives the clock signal it will be placing valid data on the MOSI pin and expecting valid data on the MISO pin according to the configured parameters of the clock with respect to the rising and falling edges. In the first SCK example above we can see that the data is valid on the rising edge of the clock and the data is then changed to a new value on the falling edge. The slave device must latch the data from MOSI on the rising edge. These settings are configured through the its CKPOL for the polarity and CKPHA for the phase. CKPHA should be set to 0 on the master when communicating between with the Silicon Labs CP240x devices. 54

55 The CP240x devices use the clock phase and polarity shown. Any MCU that is going to connect to this device should set the clock phase and polarity to conform to this timing. 55

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57 The CP240x devices are configured through a serial interface to set the operating mode of the device. Configuration parameters include the LCD controller configuration as well as setting up the additional peripherals on the device. 57

58 The interface supports 6 commands which provide access to all internal registers and RAM. The six commands are listed in the table shown. 58

59 Here we see the data structure for the SPI communications to the CP240x device. The first byte transmitted from the master node is the command and can be one of the 6 illustrated on the previous slide. The next two bytes make up the address starting with the high byte and then the low byte followed by the data bytes. The read sequence also adds a wait byte that allows time to load the shift register with the requested data. 59

60 Here we see the data structure for the I2C communications to the CP240x device. All transfers begin with the Start bit followed by the address that is determined by the combination of the fixed bits and the SMB0 pin and the direction bit. The first byte transmitted from the master node is the command and can be one of the 6 illustrated on a previous slide. The CP240x device acknowledges the address if it matches the configured address. The next two bytes make up the internal register or memory address starting with the high byte and then the low byte. This is then followed by the data bytes. 60

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62 In interval timing applications, a timer is programmed to overflow at a regular interval and the event is used to synchronise the program to perform an action such as checking the state of inputs, changing the output of an I/O pin, initiating an ADC conversion etc. This can also be used to generate waveforms at set frequencies. The diagram show an interval timer set to count from 0x0000. In up counting mode as shown in the diagram, with each clock edge the counter will increment (0x0001, 0x0002 etc) until the final 16 bit value is reached (0xFFFF). At this point the counter rolls over to 0x0000 and starts counting again. This condition is called overflow. We can use the timer in this mode to generate a periodic event as shown in the example. 62

63 In order to change the period of the event we will need to modify the number of counts needed to reach the overflow condition. We can do this by modifying the start value of the timer. In the last example we were starting the timer at a value of 0x0000. In the diagram here, we can change the starting value to say 0x0FFF which reduces the number of counts till the overflow event. When the timer overflows it reloads this value into the timer register in order to start it at a value other than 0x0000. We call this value the Reload value. In the previous example we had cycles before the overflow event occurred because we started at 0x0000. In this example we have an overflow count of and a reload value of 4096, the difference of which is cycles to reach the overflow. 63

64 An add-on circuit to the timer is the capture/compare module. This provides the capability to store the timer value when an external event occurs when in a capture mode. In the compare mode, an output flag from the timer module identifies when a match occurs between a value stored in an SFR and the timer count value using a comparator. The value is typically the equal to operator. There are many different uses for these types of events, however, in the CP240x devices this method can be used to calibrate the smartclock oscillator with the system clock. In the examples provided we see that the capture event stores the value of the timer in the capture register and the compare event occurs when the timer value matches that of the value stored in the comparator. 64

65 The C8051F family has many timers integrated. Here we take a look at two of those timers. Timer 0 and Timer 1 are the standard timers from the legacy

66 This functional diagram shows the timer operating as a 16 bit timer. The timer operates in an up counting mode with the overflow value equal to 0xFFFF. When the timer overflows the interrupt is valid. The timer run control bit (TR0) is used to start the timer. Timer 0 is always clock by the system clock divided by

67 This functional diagram shows Timer 1 operating as a 16 bit timer with auto reload. The timer operates in an up counting mode with the overflow value equal to 0xFFFF. When the timer overflows the interrupt is valid. The timer run control bit (TR1) is used to start the timer and is set using the TMR1CN register at address 0x59. The Timer 1 Control register (TMR1CN) also determines the clock input that drives the timer which can be the system clock divided by 12 or the smartclock oscillator divided by 8. Timer 1 can also operate in a capture mode as a means to calibrate the smartclock oscillator with the selected system clock. 67

68 The programming sequence for Timers 0 and 1 is simple. For Timer 1 there is a clock source selection that has to be made and the initial setup should set the desired clock. Both of the timers operate in an up counting mode with auto-reload meaning that once the overflow condition is met the reload value is then loaded into the count registers. Therefore, the starting value in the timer count registers need to be initialized as well as the reload values. Once the register initialization is complete the timers can be started by setting the run control bits. 68

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71 Visit the Silicon Labs Education Resource Center to learn more about the MCU products. 71

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