Interfacing PCI2040 to TMS320VC5420 DSP

Size: px

Start display at page:

Download "Interfacing PCI2040 to TMS320VC5420 DSP"

Jade Hoover
5 years ago
Views:

1 Application Report SCPA00 - June 000 Interfacing PCI040 to TMS0V DSP Mike Campbell PCIBus Solutions ABSTRACT This application note describes how system designers can interface the TMS0V 6-bit HPI () to the PCI bus, using the TMS0C6x HPI (C6x) mode interface on the PCI040 PCI-to-DSP bridge. The note specifies two modes for mapping the to host memory, depending on the number of s. The note also describes both hardware and software considerations, provides an example schematic, and includes other illustrative figures. Contents Introduction Mapping to Host Memory Hardware Considerations C6x HPI Protocol to HPI-6 Protocol Switching Between Two DSP Cores Multiple HRST Handling Two HINT Interrupts From One DSP Software Considerations Writing From HPIA, HPIC, and HPID Registers Reading From HPIA, HPIC, and HPID Registers Using the Autoincrement Feature Summary Example Schematic List of Figures Memory Map Memory Map Two or Less s Behind PCI More Than Two s Behind PCI PCI Data During a Write to TMS0 HPI PCI Data During a Read From TMS0 HPI Schematic ( of ) Schematic ( of ) Schematic ( of ) Trademarks are the property of their respective owners..

2 SCPA00 Introduction PCI040 is a PCI-to-DSP bridge designed to interface to either the 8-bit TMS0C4x HPI port or the 6-bit TMS0C6x HPI (C6x) port. This application note describes a method for interfacing the TMS0V 6-bit HPI () to the PCI bus, using the 6-bit C6x mode interface on the PCI040. Mapping to Host Memory There are two different ways of mapping the into host or PC memory space, depending on the number of s. Use memory map 0 with two or less s. This method maps each subsystem or core of the c40 into a dedicated memory space. Figure illustrates memory map 0. Control Space offset HCSO HCS HCS HCS DSP0 (Core A) DSP0 (Core B) DSP (Core A) DSP (Core B) Figure. Memory Map h FFFh 000h FFFh 4000h FFFh 6000h 7FFFh Use memory map with more than two s. This method maps each DSP to a specific memory space, and each core or subsystem of the DSP shares the same memory space. Figure illustrates memory map. Control Space offset HCS0 HCS HCS DSP0 (Core A & B) DSP (Core A & B) DSP (Core A & B) 0000h FFFh 000h FFFh 4000h HCS DSP (Core A & B) Figure. Memory Map NOTE: The Control space offset is the offset from address represented in the control space base address register located at PCI offset 4h in the PCI040. FFFh 6000h 7FFFh Interfacing PCI040 to TMS0V DSP

3 SCPA00 Hardware Considerations The is a dual CPU device with two independent c4x subsystems capable of core-to-core communication. Although the PCI040 was not designed specifically to interface to a dual CPU device, it functions properly with such a device with special considerations: Converting a c60 HPI protocol to a c40 HPI-6 protocol Switching between the two DSP cores Handling multiple resets and interrupts. C6x HPI Protocol to HPI-6 Protocol The has two modes of operation for the HPI bus: Non-multiplexed mode (HMODE=): the HPI interface has a 8-bit address bus used to access all internal memory. Multiplexed mode (HMODE=0): the address and data are shared or multiplexed on the same pins. The PCI040 only implements multiplexed mode, so the HMODE pin on the must be tied or pulled down to. You must add additional logic for compatibility to use the PCI040 s 6-bit HPI to connect the to the PCI bus. The C6x HPI has an active low HRDY signal, and the has an active high HRDY signal, so you must use an inverter on all implemented s. Select a.v inverter like the SN74ALCV04 so VCC_H can be tied directly to VCC.. Switching Between Two DSP Cores Use the SELA/B pin on the to select which DSP subsystem to access through the HPI interface. Connect the PCI040 s GPIO like GPIO to the SELA/B pin. You can toggle this pin either low or high to select core A or core B.. Multiple HRST There are two methods for controlling the reset function of each subsystem. Holding A_RS and B_RS low while the HPIRS pin transitions from low to high keeps both cores in reset while allowing you to download application code into the DSP. After the download, you can drive A_RS and B_RS high to take the two subsystems out of reset. Holding A_RS and B_RS high while the HPIRS pins transitions from low to high holds both cores in reset while allowing you to download code in the DSP. You can take a specific subsystem out of reset by performing HPI write to address Fh to release that subsystem from reset. You can change the value of the SELA/B pin and write to the other subsystem to release that subsystem from reset. This method is recommended when using the PCI040. You can use power-on reset logic to reset each subsystem (A_RS and B_RS). Connect the HPIRS pin to the HRST pin on the PCI040. You must ensure that the poweron reset logic deasserts reset to each subsystem before host software deasserts HRST to the DSP. Remember to take each subsystem of the DSP out of reset by performing a HPI write to address Fh after the application is downloaded. Interfacing PCI040 to TMS0V DSP

4 SCPA00.4 Handling Two HINT Interrupts From One DSP Handling multiple interrupts depends on how many s are located behind the PCI040. If there are two or less s, you can connect HINT0 to and HINT to to the first. You can connect the second interrupts ( and ) to PCI040 s HINT and HINT, respectively (see Figure ). This method corresponds with memory map 0. U HINT0 HINT HINT HINT PCI U U Figure. Two or Less s Behind PCI040 If there are more than two s, you need to AND the two interrupts on the DSP together as illustrated in Figure 4. Each interrupt on the DSP shares the same interrupt line on the PCI040, so you have no way of knowing which subsystem asserted HINT, and you must write a to the HINT bit of the HPIC register for each subsystem. This method corresponds to memory map. UA 4 U U4 HINT0 HINT HINT HINT PCI UB UC U U U6 UD 4 Figure 4. More Than Two s Behind PCI040 4 Interfacing PCI040 to TMS0V DSP

5 4 Software Considerations SCPA00 The C6x has a 6-bit HPI, but it uses words that are bits wide, so all HPI transactions consist of two back to back HPI cycles. Since the PCI040 6-bit interface was designed to interface to C6x(s), the PCI040 will also do back-to-back HPI cycles. Unlike the C6x, the uses 6-bit words that require only one HPI cycle to complete a transaction. Programmers writing software to access a through the PCI040 need to be aware that reading and writing to the DSP require special access routines. 4. Writing From HPIA, HPIC, and HPID Registers When writing to the HPIA (HPI address) register, the HPIC (HPI control) register, and the HPID (HPI data) register (in non-autoincrement mode), remember that the PCI040 will do two back-to-back cycles to the HPI. Both cycles are to the same register, so the data written during the first cycle is over written during the second cycle. You should always transmit data written to these registers in bytes two and three on the PCI bus to ensure the correct data is written (see Figure ) Byte Byte 0 Don t Care Don t Care Figure. PCI Data During a Write to 4. Reading From HPIA, HPIC, and HPID Registers When reading to the HPIA register, the HPIC register, and the HPID register (in non-autoincrement mode), the PCI040 read these registers twice and returns the value in both the upper and lower half of the PCI doubleword (see Figure 6) Byte Byte 0 Byte Byte 0 4. Using the Autoincrement Feature Figure 6. PCI Data During a Read From To maximize the HPI performance, make all reads and writes to the HPID register using the autoincrement feature so the DSP increments the HPIA register between the first and second HPI cycle. This incrementation allows the transfer of two consecutive words to or from PCI space, enabling reading or writing -bits of data at a time, which effectively doubles the data transfer rate. Summary You can use the PCI040 C6x to interface to the with minimal external logic, but you must be aware of how the PCI040 passes data to and from the HPI interface. 6 Example Schematic Figure 7, Figure 8, and Figure 9 illustrate a schematic of an implementation of a single behind the PCI040. This schematic shows only the connections between the PCI040 and the and does not contain any detail of any implementation concerns. This example uses the memory map 0 method. Interfacing PCI040 to TMS0V DSP

6 SCPA00 P_AD[..0] PCIV PCIV VCCP C C C C4 C C6 C7 C8 C9 C0 C C.uF.uF.uF.uF.uF.uF.uF.uF.uF.uF.uF.uF P VCCP P_INTA# A A A A4 A A6 A7 A8 A9 A0 A TRST# +V TMS TDI INTA# INTC# V TCK TDO INTB# INTD# PRSNT# PRSNT# B B B B4 B B6 B7 B8 B9 B0 B.uF C.uF C4.uF C P_RST# P_PME# P_IDSEL P_FRAME# P_TRDY# P_STOP# P_PAR P_AD0 P_AD8 P_AD6 P_AD4 P_AD P_AD0 P_AD8 P_AD6 P_AD P_AD P_AD P_AD9 A4 A A6 A7 A8 A9 A0 A A A A4 A A6 A7 A8 A9 A0 A A A A4 A A6 A7 A8 A9 A40 A4 A4 A4 A44 A4 A46 A47 A48 A49 RST# GNT# AD[0] AD[8] AD[6] AD[4] IDSEL AD[] AD[0] AD[8] AD[6] FRAME# TRDY# STOP# SDONE SBO# PAR AD[] AD[] AD[] AD[09] CLK REQ# AD[] AD[9] AD[7] AD[] C/BE[]# AD[] AD[] AD[9] AD[7] C/BE[]# IRDY# DEVSEL# LOCK# PERR# SERR# C/BE[]# AD[4] AD[] AD[0] M66EN B4 B B6 B7 B8 B9 B0 B B B B4 B B6 B7 B8 B9 B0 B B B B4 B B6 B7 B8 B9 B40 B4 B4 B4 B44 B4 B46 B47 B48 B49 P_AD P_AD9 P_AD7 P_AD P_AD P_AD P_AD9 P_AD7 P_AD4 P_AD P_AD0 P_PCLK P_C/BE# P_C/BE# P_IRDY# P_DEVSEL# P_LOCK# P_PERR# P_SERR# P_C/BE# R 7 C6 pf P_PCLK P_C/BE0# P_AD6 P_AD4 P_AD P_AD0 A A A4 A A6 A7 A8 A9 A60 A6 A6 C/BE[0]# AD[06] AD[04] AD[0] AD[00] REQ64# AD[08] AD[07] AD[0 AD[0] AD[0] ACK64# B B B4 B B6 B7 B8 B9 B60 B6 B6 P_AD8 P_AD7 P_AD P_AD P_AD Solder Side Component Side PCI Connector Title PCI CONNECTOR Size Document Number Rev B <Doc> A Date: Wednesday, November 7, 999 Sheet of Figure 7. Schematic ( of ) 6 Interfacing PCI040 to TMS0V DSP

7 SCPA00 7 Interfacing PCI040 to TMS0V DSP P_AD6 GPINT# P_AD4 R 4K HRDY0# HINT0# EVMV P_C/BE# P_AD7 HD4 HD0 P_AD P_AD GPINT# P_STOP# P_TRDY# HD GPIO4 P_AD P_C/BE# P_INTA# P C I H P I GPIO Hot Swap Power/Gnd RSVD PCI040 GP BUS PCI040PGE U HCS0# HRDY0# HCS# HRST0# HCS# HRDY# HCS# HINT0# HRST# HRST# HINT# HRST# HAD0/GPD0 HINT# HINT# RSVD HRDY# HAD/GDP HRDY# RSVD HAD/GPD VCC0 HAD/GPD RSVD HAD4/GPD4 RSVD4 HAD/GPD 0 HAD6/GPD6 HAD7/GPD7 HAD8/GDP8 HAD9/GPD9 HAD0/GPD0 VCC HAD/GPD HAD/GPD HAD/GPD VCC HAD4/GPD4 HAD/GPD HCNTL0/GPA VCC HCNTL/GPA4 VCC4 PCI_PAR 4 VCC 6 VCC6 7 8 PCI_STOP# VCCP0 VCCP VCCH0 VCCH PCI_DEVSEL# IDSEL PCI_PERR# PCI_FRAME# PCI_PCLK PCI_SERR# PCI_IRDY# PCI_RST# PCI_TRDY# CBE0# AD0 CBE# CBE# AD CBE# AD AD AD4 AD AD6 AD7 AD8 AD9 AD0 AD AD AD AD4 AD AD6 AD7 AD8 AD9 AD0 AD AD AD AD4 AD AD6 AD7 AD8 AD9 AD0 AD PCI_INTA# PCI_LOCK# HBE0#/GPA0 HBE#/GPA HWIL/GPA HR/W#/GPA HRD#(HDS#)/GPCS# HSENUM# HSSWITCH HSLED GPIO0 GPIO GPIO GPIO GPIO4 GPIO G_RST# D_STAT# PME# VCC7 GPINT# GPRDY# GPRST# VCC8 VCC9 VCC0 9 P_C/BE0# P_AD[..0] HINT# HD R9 0K HRDY# P_AD HINT# EVMV P_IDSEL HD4 GPRDY# HD[..0] HD8 P_AD6 P_LOCK# HDS# P_AD0 GPIO HD GPIO0 R8 0K P_AD R6 0K R0 0K HD HSENUM# P_PME# P_AD0 GPIO R 0K VCCP HRST# HD GPIO4 HINT# R 0K P_C/BE# HINT# P_AD P_AD4 P_PAR P_PCLK P_AD8 GPIO R7 0K HCNTL HD <Doc> A PCI040 B Wednesday, November 7, 999 Title Size Document Number Rev Date: Sheet of HCNTL0 P_IRDY# P_PERR# HR/W# GPIO HCS0# P_AD0 R 0K P_AD8 P_AD9 HRST0# P_AD9 HRDY# P_AD HSSWITCH R6 4K R 0K P_AD P_AD R4 0K GPIO GPIO P_AD GPIO P_DEVSEL# HCS# HD7 P_PME# HSSWITCH 0 = CLOSED = OPEN R 0K GPIO0 P_FRAME# P_AD6 P_RST# HRDY# HD HRDY# P_AD P_AD7 HSENUM# EVMV P_SERR# P_AD0 HINT# P_AD7 P_AD4 R4 0K GPIO P_AD8 HD0 GPRDY# ONLY POPULATE IF PME# IS NOT IMPLEMENTED ON MOTHERBOARD. P_AD HD9 P_AD HD P_AD9 HD6 GPIO R 0K Figure 8. Schematic ( of )

8 SCPA00 EVMV R8 U4A.7K HINT0# HINT# HCNTL HCNTL0 GPIO HAS# A free HRST# HA0 4 HA 6 HA 66 HA HA4 HA 0 HA6 09 HA7 HA8 HA9 7 HA0 74 HA 77 HA 78 HA 08 HA4 07 HA 0 HA6 04 HA7 67 HCORE HD0 HD HD HD HD4 HD HD6 HD7 HD8 HD9 HD0 HD HD HD HD4 HD HCS HDS HDS HR/W HD0 HD HD HD HD4 HD HD6 HD7 HD8 HD9 HD0 HD HD HD HD4 HD HD[..0] HDS# HDS# HR/W# EVMV R9.7K could also be used to select the core. GPIO_A GPIO_B HRDY 9 00 HRDY UA HRDY0# UB _HOST_IF 74HCT4 HCS# 4 6 HCS# HCS0# UC EVMV R7 6 VDDA VCO CLKOUT_A CLKOUT_B HRST0# HRST# UA 0K VSSA CLKIN HPIRS RS_A RS_B XF_A XF_B GPIO_A0 GPIO_A GPIO_A 8 0 PWRON_RST# 4 INT_A0 7 INT_A 8 NMI_A GPIO_B0 GPIO_B GPIO_B INT_B0 INT_B NMI_B RSVD HMODE XIO TCK TMS TDI TRST TD0_A TD0_B 6 8 EMU0 EMU _CONTROL Title HPI Size Document Number Rev B <Doc> A Date: Wednesday, November 7, 999 Sheet of Figure 9. Schematic ( of ) 8 Interfacing PCI040 to TMS0V DSP

9 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright 000, Texas Instruments Incorporated

Using Boundary Scan on the TMS320VC5420

Application Report SPRA597 - November 1999 Using Boundary Scan on the TMS320VC5420 Clay Turner C5000 Applications Team ABSTRACT The Texas Instruments (TI ) TMS320VC5420 DSP implements limited boundary