Development and research of different architectures of I 2 C bus controller. E. Vasiliev, MIET

Transcription

1 Development and research of different architectures of I 2 C bus controller E. Vasiliev, MIET

2 I2C and its alternatives I²C (Inter-Integrated Circuit) is a multi-master serial computer bus invented by Philips that is used to attach low-speed peripherals to a motherboard, embedded system, or cellphone Name Description Advantages over I2C Disadvantages over I2C SPI Synchronous serial connection, 3 or 1 line for transmission, data is sent synchronized by the clock, transmission is based on push/pull technology Higher speed No addressing (many devices on one bus are not allowed) UART Universal Asynchronous Receiver/Transmitter. Fixed baudrate is used for transmission. Ability to serve as master and slave at the same time. Physical layer can be used, allowing to bridge larger distances No addressing (many devices on one bus are not allowed) CAN Complex protocol of CAN allows for data integrity check, device addressing, error recovery and several advanced features Physical layer can be used, allowing to bridge larger distances Complexity 1-Wire Just one wire plus ground are used (i.e. two wires). It is even possible to supply power to connected components over these two wires. Physical layer can be used, allowing to bridge larger distances Strict time keeping on both, master and slave side, lower speed

3 Designer benefits Functional blocks on the block diagram correspond with the actual ICs; designs proceed rapidly from block diagram to final schematic No need to design bus interfaces because the I2C-bus interface is already integrated on-chip Integrated addressing and data-transfer protocol allow systems to be completely software-defined The same IC types can often be used in many different applications Design-time reduces as designers quickly become familiar with the frequently used functional blocks represented by I2C-bus compatible IC ICs can be added to or removed from a system without affecting any other circuits on the bus Fault diagnosis and debugging are simple; malfunctions can be immediately traced Software development time can be reduced by assembling a library of reusable software modules

4 Manufacturer benefits The simple 2-wire serial I2C-bus minimizes interconnections so ICs have fewer pinsand there are not so many PCB tracks; result smaller and less expensive PCBs The completely integrated I2C-bus protocol eliminates the need for address decoders and other glue logic The multi-master capability of the I2C-bus allows rapid testing and alignment of end-user equipment via external connections to an assembly-line

5 Example of I 2 C bus applications I 2 C A/D or D/A Converters I 2 C General Purpose I/O Expanders I 2 C LED Controllers I 2 C DIP Switches I 2 C V CC4 V CC5 I 2 C Repeaters/ Hubs/Extenders V CC0 I 2 C Multiplexers and Switches V CC2 PCA9541 I 2 C Master Selector/ Demux V CC1 I 2 C Port via HW or Bit Banging I 2 C Bus Controllers MCUs MCUs I 2 C Serial EEPROMs LCD Drivers (with I 2 C) I 2 C Real Time Clock/ Calendars I 2 C Sensors V CC3 Bridges (with I 2 C) SPI UART USB

6 Example of an I2C-bus configuration using two microcontrollers MICRO - CONTROLLER A LCD DRIVER STATIC RAM OR EEPROM SDA SCL GATE ARRAY ADC MICRO - CONTROLLER B

7 Applicability of I2C-bus protocol features Feature Configuration Single master Multi-master Slave START condition M M M STOP condition M M M Acknowledge M M M Synchronization n/a M n/a Arbitration n/a M n/a Clock stretching О О О 7-bit slave address M M M 10-bit slave address О О О General Call address О О О Software Reset О О О START byte n/a О n/a Device ID n/a n/a О M = mandatory; O = optional; n/a = not applicable.

8 Devices with a variety of supply voltages sharing the same bus V DD1 = 5 В ± 10% V DD2 V DD3 R p R p CMOS CMOS NMOS BIPOLAR V DD2 and V DD3 are device dependent (e.g., 12 V).

9 Bit transfer on the I2C-bus SDA SCL data line stable; data valid change of data allowed

10 START and STOP conditions SDA SDA SCL S P SCL START condition STOP condition

11 Data transfer on the I2C-bus SDA MSB acknowledgement acknowledgement signal from slave signal from receiver P Sr SCL S or Sr to 8 9 Sr or P START or ACK ACK STOP or repeated START byte complete, clock line held LOW repeated START condition interrupt within slave while interrupts are serviced condition

12 Clock synchronization during the arbitration procedure wait state start counting HIGH period CLK 1 CLK 2 counter reset SCL

13 Arbitration procedure of two masters DATA 1 master 1 loses arbitration DATA 1 SDA DATA 2 SDA SCL S

14 A complete data transfer SDA SCL S P START ADDRESS R/W ACK DATA ACK DATA ACK STOP condition condition

15 A master-transmitter addressing a slave receiver with a 7-bit address (the transfer direction is not changed) S SLAVE ADDRESS R/W A DATA A DATA A/A P '0' (write) data transferred (n bytes + acknowledge) from master to slave from slave to master A = acknowledge (SDA LOW) A = not acknowledge (SDA HIGH) S = START condition P = STOP condition

16 A master reads a slave immediately after the first byte 1 S SLAVE ADDRESS R/W A DATA A DATA A P (read) data transferred (n bytes + acknowledge)

17 Combined format S SLAVE ADDRESS R/W A DATA A/A Sr SLAVE ADDRESS R/W A DATA A/A P *not shaded because transfer direction of data and acknowledge bits depends on R/W bits. read or write (n bytes (n bytes + ack.)* + ack.)* read or write Sr = repeated START condition direction of transfer may change at this point.

18 Bus speeds Standard-mode (Sm), with a bit rate up to 100 kbit/s Fast-mode (Fm), with a bit rate up to 400 kbit/s Fast-mode Plus (Fm+), with a bit rate up to 1 Mbit/s High-speed mode (Hs-mode), with a bit rate up to 3.4 Mbit/s.

19 I2C applications I²C is appropriate for peripherals where simplicity and low manufacturing cost are more important than speed. Common applications of the I²C bus are: Reading configuration data from SPD EEPROMs on SDRAM, DDR SDRAM, DDR2 SDRAM memory sticks (DIMM) and other stacked PC boards Supporting systems management for PCI cards, through an SMBus 2.0 connection. Accessing NVRAM chips that keep user settings. Accessing low speed DACs and ADCs. Changing contrast, hue, and color balance settings in monitors (Display Data Channel). Changing sound volume in intelligent speakers. Controlling OLED/LCD displays, like in a cellphone. Reading hardware monitors and diagnostic sensors, like a CPU thermostat and fan speed. Reading real time clocks. Turning on and turning off the power supply of system components.

20 Architectures of I 2 C bus controller State machine architecture Demultiplexer/Multiplexer chains architecture Two shift registers architecture

21 Mealy state machine for slave I 2 C bus contoller SCL _/ Waiting for START SCL _/, START flag = 1 Receiving address, R / W bit WaitSTART GetARW SCL _/, BC* = 0 SCL _/, STOP flag = 1 SCL _/, START flag = 1 SCL _/ Transmitting acknowledge SendA1 SCL _/ R / W = 1 R / W = 0 SCL _/ SendDB Transmitting data bit SCL _/, BC = 0 SCL _/ Receiving data bit SCL _/, BC = 0 GetDB GetAnA Receiving acknowledge (not acknowledge) bit Transmitting acknowledge SCL _/ SendA2 SCL _/, SDA = 1 (NACK) *BC - Bit Counter (reverse)

22 Demultiplexer/Multiplexer chains architecture of slave I2C bus controller from SDA bus D1 A D1- data, received from bus D2- data, transmitted on bus A slave address A.L. additional logic D C address/data signal SCL _/ 1 M M A. L. D-tr. D D2 to SDA bus M SCL \ _ R /W R / W additional signals & addr/data signal D dmux D-tr. control D-triggers М mux С comparator

23 Two shift registers architecture of slave I 2 C bus controller Comparing with address, transmitting on output SDA A. L. BE DO DO DO DO DO DO DO DO [7] [6] [5] [4] [3] [2] [1] [0] M DI [7] DI [6] DI [5] DI [4] DI [3] DI [2] DI [1] DI [0] A.L. to SDA bus from SDA bus 0 R / W & addr./data signal Data from input A.L. neg. edge of SCL

24 Symbol of slave I2C bus controller IN [7:0] R_W CLK FIFO_FULL OUT [7:0] DATA_VALID READY I2CInterface controller SCL SDA R

25 Verification of slave I2C bus controller Memory mem_m1 Master 1 (m1) Slave 1 (s1) Memory mem_s1 Data comparing SDA SCL Master 2 (m2) Memory mem_m2 M to S tests (one addressing, permanent addressing, addressing and data transmission with NACK, transmission of different numbers of bytes) S to M tests (one addressing, permanent addressing, transmission of different numbers of bytes) Arbitration tests (with permanent addressing)

26 Comparative characteristics of I2C bus architectures Architecture name Area of noncombinational elements (triggers), μm Area of combinational elements, μm Number of cells Whole-time addressing Number of nets State machine architecture 2031,6 3108,9 194 No 216 Multiplexer/ demultiplexer chains architecture Two shift registers architecture 2056,2 1990,7 144 No ,1 1445,9 102 Yes 127

27 Area of architectures (data are based on cell areas) State machine architecture Demultiplexer/ multiplexer chains architecture Two shift registers architecture 0 Device area, square μm

28 Power of architectures (data are based on cell powers) State machine architecture Multiplexer/demul tiplexer chains architecture Two shift registers architecture 68 Consumed power, μw