Cardsharp. Single Board Computer with HPC FMC IO Site V0.8 03/09/16

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1 Single Board Computer with HPC FMC IO Site V0.8 03/09/16 FEATURES Combines an Zynq Z7045 SoC with FMC IO module in a compact, stand alone design Powerful, dual, floating-point ARM A9 CPU performance Rugged, XMC form factor: 149 x 74 mm Self-bootable, stand-alone operation Able to operate diskless and headless Runs Linux applications Configurable IO uses standard HPC FMC IO module. Add anything from RF receivers to industrial control modules. IO site (VITA 57) deliver up to 6 GB/s to PL memory, 2 GB/s to PS memory Optional timing and triggering support for IO includes IEEE-1588 or GPS-disciplined clock Supports Innovative FMC IO module features for private data channels, triggering and timing features USB 2.0, 1 Gb Ethernet, emmc, SPI, RS232 ports Boots Linux from on-board emmc device 12V +/- 5% DC operation APPLICATIONS Embedded instrumentation Remote, autonomous IO Mobile instrumentation Distributed data acquisition SOFTWARE Linux compatible Runs standard desktop applications Eclipse C++ Developers Kit supporting IO integration and customization Device drivers, example software and support applets supplied for all peripherals DESCRIPTION Cardsharp is a user-customizable, turnkey embedded instrument that includes two A9 CPU cores. Linux runs in core 0 to provide Ethernet, USB and disk connectivity while core 1 runs real-time stand-alone applications. Cardsharp is compatible with Innovative's wide assortment of ultimate-performance FMC modules. With its modular IO, scalable performance and easy to use CPU core architecture, the Cardsharp reduces time-to-market while providing the performance you need. Distributed Data Acquisition Put the Cardsharp at the data source and reduce system errors and complexity. Available IEEE-1588 network or GPS-synchronized timing, triggering and sample control is available for remote IO. Limitless expansion via multiple nodes. Uniquely customizable An HPC FMC site for IO, userprogrammable FPGA for IO interfaces, on-board GbE and USB. Stand-alone, autonomous operation with precision-timed sampling on FMC data. Rugged Runs from flash in a compact, rugged footprint that is ready for embedded operation. 12V +/- 5% DC-Only Operation - Perfect for portable or automotive data loggers or waveform generators. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Innovative Integration products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. 04/25/16 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Innovative Integration standard warranty. Production processing does not necessarily include testing of all parameters. Innovative Integration phone fax

2 This electronics assembly can be damaged by ESD. Innovative Integration recommends that all electronic assemblies and components circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION Note: Please consult the Carsharp Production Selection Flowchart here to best understand the configuration options for this product. Product Part Number Description Cardsharp L0 Cardsharp - with Zynq Z7Z045 SoC with dual A9 CPU, active heat sink and fan, 2.5 GB DDR2, 32MB Flash, 32 GB emmc, 2x USB 2.0, 10/100/1000 GbE, 1x RS232, 12V +/- 5% DC power supply, approx 12W consumption. Aluminum chassis Sturdy aluminum chassis with feet for Cardsharp+FMC module. Fan/heatsink Heatsink and fan assembly mounted to top of aluminum chassis. Recommended for use in environments > 40C. SBC-Nano embedded PC/XMC carrier L0 A Windows/Linux Embedded Single Board Computer with XMC IO Site and 1 Gb Ethernet link, 2 msata drive ports. Innovative Integration phone fax of 17

3 Figure 1. Cardsharp Block Diagram Innovative Integration phone fax of 17

4 Figure 2. Zync SoC block diagram Innovative Integration phone fax of 17

5 Cardsharp Front and rear views (left to right) of Cardsharp within aluminum chassis sans optional fansink. Power, USB and ethernet connections exposed. Front view of Cardsharp within aluminum chassis plus optional SBC-Nano embedded PC and expansion board. FMC module installed. Front view of Cardsharp within transparent chassis plus optional fansink. Power, USB and ethernet connections exposed. Front and rear views of Cardsharp within optional chassis, within SBC-Nano embedded PC and msata expansion board. Rear view of Cardsharp within transparent chassis plus optional fansink. FMC module cover installed. Front view of Cardsharp outside of optional chassis, XMC J15 and J16 connectors exposed. FPGA heat spreader cover removed. Innovative Integration phone fax of 17

6 Cardsharp Bottom of Cardsharp SBC showing XMC connectors J15 and J16 and Zynq Z7045 SoC FPGA Top of Cardsharp SBC showing HPC FMC connector and communications ports Innovative Integration phone fax of 17

7 Standard Features Z7045 SoC CPU Cache DDR2 Memory Logic Cells Block Ram Dual ARM Cortex-A9 MPCore. NEON & Single / Double Precision Floating Point for each processor L1: 512KB, L2: 256KB 2x 512 MBx16 for PS (CPU) 3x 512 Mbx16 for for PL (Logic) 444K KB DSP Slices 2020 Tranceivers 16 IO Ports USB UART 1x, USB 2.0, Type A rear panel port 1x RS232 emmc FLASH Drive Capacity Type Use 32 GB Embedded Flash Boot drive or data storage Timing and Triggering Support Features Sample Clock Sources GPS disciplined clock accuracy IEEE-1588 disciplined clock accuracy Trigger Modes External, FMC site +/-100 ns RMS from UTS +/-50 ns RMS from grand master source Software, GPS/IEEE synchronized, GPS/IEEE-1588 Time, external input GPIO QSFP Ethernet FMC Sites Module Sites 1 Standards 8 bits, direction is bit-programmable 1x Aurora, 40 Gbps (bidirectional) 1x 10/100/1000 Mbps VITA 57.1 FMC VITA 20 Conduction cooling Trigger Outputs Trigger Inputs Clock input Module Synchronization FMC site (FMC module type dependent) 1 SSMC on FMC site Use as sample clock or FMC Reference; SSMC on FMC site. Simultaneously across mesh via PPS/matched reference clocks Size CPU Connections 69 x 76.5 mm, 10mm mezzanine height FMC Site 0: HPC Innovative Integration phone fax of 17

8 Customization Features Power Management FPGA Xilinx Zynq 7045 SoC FPGA Controls triggering and has 34 pin connections to FMC Mezzanine Memory-mapped Interface to A9 CPU cores FrameWork Logic available for FPGA in VHDL Power States Temperature Monitors Alarms Low power states supported including wake features from CPU and LAN 2 total : Zync SoC and Cardsharp assembly each have a temperature sensor Software programmable warning and failure levels GPS Option Over-temp Monitor Disables power supplies Type Position Accuracy 12 satellite, parallel tracking 3m CEP Time to first fix (TTFF) Cold <60s Warm <32s Obscuration recovery <1s Conductive Cooling Fans Conduction cooling supported for Cardsharp assembly includes heat conduction bars on each edge and VITA57 pattern for FMC module Single integrated fan controller Maker Interface Symmetricom GPS-500 Serial interface to FPGA Physicals Form Factor XMC VITA49: 149 x74 mm, ~20 mm height Power Requirements Weight 1500g (est.) Input 12V +/- 5% DC Hazardous Materials Lead-free and RoHS compliant Consumption Varies according to FMC module requirements 8W: Cardsharp with no FMC MTBF ~42,000 Hours Innovative Integration phone fax of 17

9 ABSOLUTE MAXIMUM RATINGS!Exposure to conditions exceeding these ratings may cause damage! Parameter Min Max Units Conditions Supply Voltage V Operating Temperature 0 60 C Non-condensing, forced air cooling required Storage Temperature C ESD Rating - 1k V Human Body Model Vibration - 5 g Hz, Class 3.3 per ETSI EN V2.1.2 ( ) Shock - 40 g peak Class 3.3 per ETSI EN V2.1.2 ( ) Innovative Integration phone fax of 17

10 Architecture and Features The Cardsharp combines dual ARM A9 CPU cores with an HPC FMC IO module and high-speec connectivity peripherals to create a customizable instrument for a variety of applications. Embedded CPU cores The Zynq Z045 SoC is a dual A9 CPU core combined with user extensible FPGA fabric that provides a real-time computing engine, suitable for high-speed signal processing while consuming minimal footprint and power. Embedded CPU #0 boots into Linux, which provides sophisticated, mature drivers to high performance connectivity peripherals such as the 1 GbE ethernet port, QSFP port, emmc flash memory and USB port. USB storage devices are supported, to support data logging at rates to 480 Mb/s to each device. Embedded CPU core #1 boots a user-written standalone application to perform real-time I/O via the FMC module. This provides optimal, minimal latency interaction with the FMC peripherals and resources, without inducing OS or stack latencies of any kind. The best of both worlds: highperformance connectivity via CPU 0, determinicity and speed via CPU 1. Each A9 CPU core is mapped directly to the FMC module. The CPU bus tightly couples the CPU to the FMC modules and the SoC DMA engines may be used to accelerate I/O, outperforming Innovative's previous generation SBC systems by 2 to 4 times. Bidirectional data transfer rates between logic memory and FMC resources occur at full memory bus rates: 6000 MB/s. The Cardsharp provides familiar core interfaces for expansion and connectivity: Gigabit Ethernet, USB ports, and emmc disk, as well as numerous connectivity interfaces such as RS232 and SPI. Innovative Integration phone fax of 17

11 XMC Connectors (P15, P16) P15 is the XMC PCI Express connector to the host. Column Row A B C D E F 1 XMC_P15_TX0_P XMC_P15_TX0_N NC XMC_P15_TX1_P XMC_P15_TX1_N 12P0V_XMC 2 DGND DGND XMC_JTRST_N DGND DGND XMC_MRSTI_N 3 XMC_P15_TX2_P XMC_P15_TX2_N NC XMC_P15_TX3_P XMC_P15_TX3_N 12P0V_XMC 4 DGND DGND XMC_JTCK DGND DGND NC 5 XMC_P15_TX4_P XMC_P15_TX4_N NC XMC_P15_TX5_P XMC_P15_TX5_N 12P0V_XMC 6 DGND DGND XMC_JTMS DGND DGND NC 7 XMC_P15_TX6_P XMC_P15_TX6_N NC XMC_P15_TX7_P XMC_P15_TX7_N 12P0V_XMC 8 DGND DGND XMC_JTDI DGND DGND NC 9 NC NC NC NC NC 12P0V_XMC 10 DGND DGND XMC_JTDO DGND DGND NC 11 P15_RX_0_P P15_RX_0_N NC P15_RX_1_P P15_RX_1_N 12P0V_XMC 12 DGND DGND NC DGND DGND DGND 13 P15_RX_2_P P15_RX_2_N NC P15_RX_3_P P15_RX_3_N 12P0V_XMC 14 DGND DGND NC DGND DGND NC 15 P15_RX_4_P P15_RX_4_N NC P15_RX_5_P P15_RX_5_N 12P0V_XMC 16 DGND DGND NC DGND DGND NC 17 P15_RX_6_P P15_RX_6_N NC P15_RX_7_P P15_RX_7_N XMC_RFU12 18 DGND DGND NC DGND DGND NC 19 PEX_REFCLK0_P PEX_REFCLK0_N NC NC NC NC Table 1: P15 Signals Innovative Integration phone fax of 17

12 Signal Name Description 1 NC No Connect. Do not connect any signals (including ground) to these pins 2 DGND Board Ground 3 12P0V_XMC Carrier +12V power input. If this power is present, Cardsharp onboard power input (J5) must be left unconnected; otherwise the board might be damaged. 4 XMC_P15_TX0_P/XMC_P15_TX0_N to XMC_P15_TX7_P/XMC_P15_TX7_N 5 XMC_P15_RX0_P/XMC_P15_RX0_N to XMC_P15_RX7_P/XMC_P15_RX7_N High-speed transmitter differential pairs. Typically used for PCIe bus (up to 8 lanes) connection, carrier being the host. Signal direction is from the module (module drives these signals). Can be also used in a QSFP high-speed port. High-speed receiver differential pairs. Typically used for PCIe bus (up to 8 lanes) connection, carrier being the host. Signal direction is to the module (module receives these signals). Can be also used in a QSFP high-speed port. 6 PEX_REFCLK0_P/PEX_REFCLK0_N PCIe Reference Clock (differential) from the carrier board. 7 XMC_MRSTI_N PCIe reset signal. 8 XMC_JTRST_N JTAG Reset signal from the carrier. Used as a board master reset on Cardsharp. 9 XMC_JTCK JTAG Clock signal from the carrier. 10 XMC_JTMS JTAG Mode Select signal from the carrier. 11 XMC_JTDI JTAG Data Input signal from the carrier (module input). 12 XMC_JTDO JTAG Data Output signal from the module (module output). 13 XMC_RFU12 Not used, reserved for future use. Table 2: P15 Signal Description Notes: 1. JTAG signals are also available on J4 and J8 connectors (J8 is available on Cardsharp rev B and later; it is not present on rev A board). 2. JTAG signals are 3.3V LVCMOS. 3. QSFP functionality is available only with a special carrier. 4. P15 JTAG signal functionality is available on Cardsharp rev B and later; it is not available on rev A board. Innovative Integration phone fax of 17

13 P16 is the XMC secondary connector to the host and is used for digital IO, and QSFP functions. Column Row A B C D E F 1 NC NC P16_DIO_0_P NC NC P16_DIO_1_P 2 DGND DGND P16_DIO_0_N DGND DGND P16_DIO_1_N 3 NC NC P16_DIO_2_P NC NC P16_DIO_3_P 4 DGND DGND P16_DIO_2_N DGND DGND P16_DIO_3_N 5 NC NC P16_DIO_4_P NC NC P16_DIO_5_P 6 DGND DGND P16_DIO_4_N DGND DGND P16_DIO_5_N 7 NC NC P16_DIO_6_P NC NC QSFP_XL_SCL 8 DGND DGND P16_DIO_6_N DGND DGND QSFP_XL_SDA 9 NC NC TRACE_CLK NC NC TRACE_D_0 10 DGND DGND TRACE_CTL DGND DGND TRACE_D_1 11 NC NC QSFP0_CLK_P NC NC QSFP1_CLK_P 12 DGND DGND QSFP0_CLK_N DGND DGND QSFP1_CLK_N 13 NC NC QSFP0_MODPRES_N NC NC QSFP1_MODPRES_N 14 DGND DGND QSFP0_INT_N DGND DGND QSFP1_INT_N 15 NC NC QSFP0_LPMODE NC NC QSFP1_LPMODE 16 DGND DGND QSFP0_MODESEL_N DGND DGND QSFP1_MODESEL_N 17 NC NC QSFP0_RESET_N NC NC QSFP1_RESET_N 18 DGND DGND QSFP0_SCL DGND DGND QSFP1_SCL 19 NC NC QSFP0_SDA NC NC QSFP1_SDA Table 3: P16 Signals Innovative Integration phone fax of 17

14 Signal Name Description 1 NC No Connect. Do not connect any signals (including ground) to these pins 2 DGND Board Ground 3 P16_DIO_0_P/P16_DIO_0_N to P16_DIO_6_P/P16_DIO_6_N 4 TRACE_CLK, TRACE_CTL, TRACE_D_0, TRACE_D_1 5 QSFP0_CLK_P, QSFP0_CLK_N, QSFP0_MODPRES_N, QSFP0_INT_N, QSFP0_LPMODE, QSFP0_MODESEL_N, QSFP0_RESET_N, QSFP0_SCL, QSFP0_SDA 6 QSFP1_CLK_P, QSFP1_CLK_N, QSFP1_MODPRES_N, QSFP1_INT_N, QSFP1_LPMODE, QSFP1_MODESEL_N, QSFP1_RESET_N, QSFP1_SCL, QSFP1_SDA High Speed Generic DIO signals. Can be programmed to be either differential or single-ended. Originated on the Zynq bank 12, which is powered by VADJ. Typically VADJ is between 1.8V and 2.5V, so single-ended signals are 1.8V to 2.5V LVCMOS. Alternatively can be programmed to be differential pairs with common LVDT levels. Zynq Trace signals. Can be used for Zynq debugging. GSFP0 port control signals. Note that QSFP functionality is available only with a special carrier. Leave unconnected if not used. GSFP1 port control signals. Note that QSFP functionality is available only with a special carrier. Leave unconnected if not used. 7 QSFP_XL_SCL, QSFP_XL_SDA Serial interface signals for QSFP reference clock control. Leave unconnected if not used. Table 4: P16 Signal Description Innovative Integration phone fax of 17

15 FMC IO Site A single HPC FMC IO module site enables the Cardsharp to be configured with a wide variety of IO personalities. The FMC site is for FPGA mezzanine cards conforming to VITA 57.1 standard, which are 69 x 75 mm modules. The module site is designed to support conduction cooling, but also supports use of a cooling fan mounted directly under the module, to support conve ction-cooled installations at lower cost. Innovative offers FMC IO offering a range of analog performance mated to the high performance FPGA computing cores within the Zynq SoC. Innovative's Velocia architecture data packet system allows these modules to stream data continuously to system memory at rates limited only by the memory subsystem making the Cardsharp well suited for data logging and playback functions. Data may be streamed to a 10 Gb Ethernet device at 1000 MB/s. When configured with a two USB RAID0 array, sustained storage to local USB storage devices at 500Mb/s are achievable. Special features supporting all Innovative FMC module are provided in the Cardsharp for simultaneously sampling, triggering and controls. System triggers and matched clocks from an externally-supplied clock or reference provide simultaneously sampling for the two modules. The FMC module site has 66 differential connections plus eight 12.5 Gbps SERDES links to the on-board FPGA, providing ample bandwidth for even the fastest FMC modules. Triggering and Sample Clocks The Cardsharp has unique clocking and triggering features for the FMC module. The site receives two triggers from the application FPGA and two clock inputs through its connector. Innovative modules can use these to support simultaneous sampling and unique trigger scenarios using the application FPGA. Sample clocks for the FMC site can be synchronized using an optional GPS or IEEE-1588 reference or from an external clock input. FMC module PLLs can use either the external clock input or the disciplined clock as a reference. The disciplined clock allows multiple, remote instruments to sample simultaneously and act cooperatively. Position and time data is also available from the GPS when installed. Remote Operation Cardsharp can be operated using Ethernet as a remote computer or embedded instrument. For pure embedded operation, the Cardsharp can operate headless without monitor, keyboard or mouse. The system boots from an onboard QSPI and emmc FLASH, providing reliable operation even in a rugged environment. Application FPGA XMC Modules for IO - Flexible, modular IO - Industry-standard VITA 57 - Up to 6000 MB/s transfer rates - Industry-standard, multi-vendor The Zynq Z7045 provides a large, user-programmable on-chip FPGA which allows the Cardsharp to be customized for many IO functions, such as triggering and control features. This FPGA is memory-mapped peripheral to the Zync SoC CPUs. New functions can added to the system by adding them to the FPGA design. FPGA logic is provided in the FrameWork Logic tools, which includes the standard functionality that can be modified or used as an example. Development using Xilinx USB cable is supported on-board circuitry drives the JTAG scan path (when used with SBC- Nano). Innovative Integration phone fax of 17

16 Software Tools Software development tools for the Cardsharp provide comprehensive support application development including device drivers, peripheral configuration and control, and utilities that allow developers to be productive from the start. Software classes provide C++ developers a powerful, high-level interface to the system devices that makes system integration and achieving real-time, high speed data acquisition easier. Software for data logging and analysis are provided with every Innovative FMC module. Data can be logged to system memory at full rate or to disk drives at rates supported by the drive and controller. Triggering and sample rate controls are provided to support data acquisition applications without writing code. Innovative software applets include Binview which provides data viewing, analysis and import to MATLAB for large data files. Support for Eclipse C++ is provided. The PetaLinux OS is supported. For more information, the software tools User Guide and on-line help may be downloaded. Logic Tools Customized IO interfaces, triggering and other unique features may be added to the Cardsharp by modifying the FPGA logic. The FrameWork Logic tools provide support for VHDL/Verilog developments. Application logic can be modified by building upon the Innovative components for hardware interfaces and system functions. Each design is provided as a Xilinx Vivado project with VHDL source for top level logic with a modeling test-bench illustrating logic functionality. FMC Modules Plug FMC modules into the Cardsharp to build your custom, turnkey embedded instrument. Innovative Integration offers an array of ultra-performance, CPU FMC modules to create your solution. Innovative FMC module families feature analog and digital IO with FPGA computing cores on high performance CPU modules. The FrameWork Logic development tools allow you to design in MATLAB and VHDL and rapidly implement high speed signal processing on the FMC. See the full list of Innovative FMC modules here. Innovative Integration phone fax of 17

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