Product Specification

Transcription

1 A Building,HuiXin industrial park,no 31, YongHe road, Fuyong town, Bao'an District,Shenzhen City, CHINA TEL: FAX: Website: Product Specification IEEE b/g/n 2.4GHz 1T1R WiFi with Bluetooth v2.1+edr/bluetooth 3.0/3.0+HS/4.0 (Single Antenna) Project Name Realtek RTL8723BS Combo Module Model NO F23BDSM33-W3 Customer Customer s Part NO Approved: William Tan Checked: Jim Hu Drafted: Neal Yu Feedback of customer s Confirmation We accept the specification after Confirmed. Customer Customer signature Approved Date

2 CONTENTS 0 REVESION HISTORY INTRODUCTIONS OVERVEIW PRODUCT FEATURES BLOCK DIAGRAM GENERAL SPECIFICATION ELECTRICAL CHARACTERISTICS POWER SUPPLY DC CHARACTERISTICS DIGITAL I/O PIN DC CHARACTERISTICS SDIO INTERFACE AC CHARACTERISTICS SDIO INTERFACE POWER-ON SEQUENCE UART INTERFACE POWER-ON SEQUENCE PIN DEFINITION MECHANICAL SPECIFICATION OUTLINE DRAWING RECOMMENDED REFLOW PROFILE NOTICE PACKAGE Page2/17

3 0. Revision History REV NO Date Modifications Draft Approved Rev First Released Neal Yu William Tan Rev Add the remark of Pin Assignment, showing the voltage of I/O port. Neal Yu William Tan Page3/17

4 1. Introduction 1.1 Overview F23BDSM33-W3 is a small size and low profile WiFi + BT Combo module, The siize is 12mm*16mm. It can be easily manufactured on SMT process and highly suitable for tablet PC, ultra book, mobile device and consumer products. It provides SDIO interface for WiFi to connect with host processor and high speed UART interface for BT. It also has a PCM interface for audio data transmission with direct link to external audio codec via BT controller. The WiFi throughput can go up to 150Mbps in theory by using 1x n b/g/n MIMO technology and Bluetooth can support BT2.1+EDR/BT3.0 and BT4.0. F23BDSM33-W3 uses Realtek RTL8723BS. It is a highly integrated b/g/n 1T1R WLAN, an integrated Bluetooth 2.1/3.0/4.0 module. It combines a WLAN MAC, a 1T1R capable WLAN baseband, BT protocol Stack(LM, LL, and LE), BT baseband, modem, and WLAN/BT RF in the module. The NFH23B01 provides a complete solution for a high throughput performance integrated wireless LAN and Bluetooth controller. 1.2 Product Features General 12mm*16mm b/g/n 1T1R WLAN and Bluetooth module Host Interface Complies with SDIO 1.1/2.0/3.0 for WLAN with clock rate up to 100MHz (DDR50) Complies with HS-UART with configurable baud rate for Bluetooth WLAN Features CMOS MAC, Baseband PHY, and RF in a single chip for b/g/n compatible WLAN Complete n solution for 2.4GHz band One Transmit and one Receive path (1T1R) Short Guard Interval (400ns) Maximum data rate 54Mbps in g; and 150Mbps in n i (WPA, WPA2). Open, shared key, and pair-wise key authentication services BT Features Compatible with Bluetooth v2.1+edr and v3.0+hs Systems Supports Bluetooth 4.0 Low Energy(BLE) Integrated MCU to execute Bluetooth protocol stack PCM interface for audio data transmission via Bluetooth controller Supports AFH to dynamically detect channel quality to improve transmission quality Page4/17

5 1.3 Block diagram The general block diagram for the module is shown in Figure 1 Figure 1 Page5/17

6 2. General specification General features Main Chipset Host Interface WiFi Standards Realtek RTL8723BS-VD SDIO for WLAN UART for BT b/g/n BT Standards Bluetooth 2.1/3.0/4.0 Dimension Operating conditions Operating Voltage Operating Temperature Storage Temperature RF features Operating Frequency Channels L16.0mm*W12.0mm*H1.7mm 3.3±10% Vdc 0 C to +70 C -40 C to +80 C 2.400~2.4835GHz WiFi: USA/Canada: channel 1~11; Europe/China/Australia: channel 1~13; Japan: channel 1~14 BT: Channel 0~78 Modulation WiFi: b(DSSS): CCK(11, 5.5Mbps), DQPSK(2Mbps), DBPSK(1Mbps); g(OFDM): BPSK(9,6Mbps), QPSK(18,12Mbps), 16QAM(36,24Mbps), 64QAM(54,48Mbps); n(OFDM): BPSK, QPSK, 16QAM, 64QAM(150Mbps) BT: PHY Data rates Output Power WiFi: b: 11,5.5,2,1 Mbps g: 54,48,36,24,18,12,9,6 Mbps n: up to 150Mbps BT: 1 Mbps for Basic Rate 2,3 Mbps for Enhanced Data Rate 6,9,12,18,24,36,48,54 Mbps for High Speed WiFi: b 16±2dBm g 15±2dBm n 14±2dBm BT: Max +10dBm Page6/17

7 EVM b EVM 35% g EVM -25dB n EVM -28dB WiFi: PER 1Mbps -88dBm 2Mbps -87dBm 5.5Mbps -85dBm 11Mbps -82dBm Sensitivity PER 6Mbps -86dBm 9Mbps -85dBm 12Mbps -84dBm 18Mbps -82dBm 24Mbps -80dBm 36Mbps -77dBm 48Mbps -73dBm 54Mbps -71dBm PER MCS 0-83dBm MCS 1-82dBm MCS 2-80dBm MCS 3-78dBm MCS 4-75dBm MCS 5-71dBm MCS 6-69dBm MCS 7-67dBm BT: 1Mbps 2Mbps 3Mbps Other features Antenna Network Architecture Security OS Supported External Antenna (Single Antenna) WiFi: Ad-hoc mode (Peer-to-Peer ) Infrastructure mode Software AP WiFi Direct BT: Pico Net, Scatter Net WiFi: WPA, WPA-PSK, WPA2, WPA2-PSK, WEP 64bit & 128bit, IEEE x, IEEE i BT: Simple Paring Android /Linux/ Win CE /XP/WIN7/iOS Page7/17

8 3. Electrical Characteristics 3.1 Power Supply DC Characteristics Symbol Parameter Minimum Typical Maximum Unit VIN33 3.3V Supply Voltage V 1.8V DC supply for digital I/O V 3.2 Digital I/O Pin DC Characteristics Symbol Parameter Minimum Typical Maximum Unit VIH Input high voltage V VIL Input low voltage V VOH Output high voltage V VOL Output low voltage V 3.3 SDIO/GSPI Interface AC Characteristics Figure 2. SDIO Interface Timing SDIO Interface Timing Parameters NO Parameter Mode MIN MAX Unit fpp TWL TWH TISU TIH TODLY Clock Frequency Default 0 25 MHz HS 0 50 MHz Clock Low Time DEF 10 - ns HS 7 - ns Clock High Time DEF 10 - ns HS 7 - ns Input Setup Time DEF 5 - ns HS 6 - ns Input Hold Time DEF 5 - ns HS 2 - ns Output Delay Time DEF - 14 ns HS - 14 ns Page8/17

9 3.4 SDIO Interface Power-On Sequence After power-on, the SDIO interface is selected by the RTL8723BS automatically when a valid SDIO command is received. To attain better SDIO host compatibility, the following power-on sequence is Recommended. Figure 3. SDIO Interface Power-On Sequence SDIO Interface Power-On Sequence Symbol Description T33ramp 3.3V Power Pre-Charge Ramp Up Duration Before Formal Power Up. We recommend that a 3.3V power-on and then power-off sequence is executed by the host controller before the formal power on sequence. This procedure can eliminate host card detection issues when power ramp up duration is too long, or when a system warm reboot fails. Toff The duration 3.3V is cut off before formal power up. T33ramp The 3.3V main power ramp up duration. T12ramp The internal 1.2V ramp up duration. TPOR The duration from when the power-on reset releases and the power management unit executes power on tasks. A power on reset will detect both 3.3V and 1.2V power ramp up after a predetermined duration. Tnon_rdy SDIO Not Ready Duration. In this state, the RTL8723BS-VD may respond to commands without the ready bit being set. After the ready bit is set, the host will initiate complete card detection procedure. We recommend that the card detection procedures are divided into two phases: A 3.3V power pre-charge phase and a formal power-up phase. During the 3.3V power pre-charge phase, the power ramp up duration is not limited. The 3.3V power is cut off and is turned on after the Toff period. The ramp up time is specified in the T33ramp duration. After main 3.3V ramp up and 1.2V ramp up, the power management unit is enabled by the power ready detection circuit. The power management unit enables the SDIO block. efuse is then autoloaded to SDIO circuits during the Tnon_rdy duration. After the autoload has completed, the SDIO sets the ready bit. After CMD5/5/3/7 procedures, card detection is executed. When the driver has loaded, normal CMD52 and CMD53 are used. Page9/17

10 SDIO Interface Power-On Timing Parameters Symbol MIN Typical MAX Unit T33ramp - - No Limit ms Toff ms T33ramp ms T12ramp ms TPOR ms Tnon_rdy ms 3.5 UART Interface Power-On Sequence Figure 4. UART Power On Sequence With Hardware Flow Control UART Interface Power-On Sequence Symbol Description T33ramp 3.3V Power Pre-Charge Ramp Up Duration Before Formal Power Up. We recommend that a 3.3V power-on and then power-off sequence is executed by the host controller before the formal power on sequence. This procedure can eliminate host card detection issues when power ramp up duration is too long, or when a system warm reboot fails. Toff The duration 3.3V is cut off before formal power up. T33ramp The 3.3V main power ramp up duration. T12ramp The internal 1.2V ramp up duration. TPOR The duration from when the power-on reset releases and the power management unit executes power on tasks. A power on reset will detect both 3.3V and 1.2V power ramp up after a predetermined duration. Tnon_rdy UART Not Ready Duration. In this state, the RTL8723BS-VD will not respond to any commands. We recommend that the card detection procedures are divided into two phases: A 3.3V power pre-charge phase and a formal power-up phase. During the 3.3V power pre-charge phase, the power ramp up duration is not limited. The 3.3V power is cut off and is turned on after the Toff period. The ramp up time is specified in the T33ramp duration. After main 3.3V ramp up and 1.2V ramp up, the power management unit is enabled by the power ready detection circuit. The power management unit enables the Bluetooth block. The Bluetooth firmware theninitializes all circuits, included the UART. In addition to wait the Tnon_rdy time, if the host supports Page10/17

11 UART hardware flow control it can detect RTS signals and follow the formal UART flow control handshake. UART Interface Power On Timing Parameters Symbol MIN Typical MAX Unit T33ramp - - No Limit ms Toff ms T33ramp ms T12ramp ms TPOR ms Tnon_rdy ms 4. Pin Definition(Top View) Pin Assignment Pin# Name Description Remark 1 Reserved_1 NC (Not Connected) 2 Reserved_2 NC (Not Connected) 3 Reserved_3 NC (Not Connected) 4 3.3V_4 3.3V Power Supply Typical voltage: 3.3V 5 3.3V_5 3.3V Power Supply Typical voltage: 3.3V 6 GND Ground 7 Reserved_7 NC (Not Connected) 8 ALERT NC (Not Connected) 9 I2C CLK NC (Not Connected) Page11/17

12 10 I2C DATA NC (Not Connected) 11 GPIO15/COEX1 General Purpose Input/Output Pin High level: 1.8V 12 COEX2 NC (Not Connected) 13 COEX3 NC (Not Connected) 14 Reserved_14 NC (Not Connected) 15 Reserved_15 NC (Not Connected) 16 Reserved_16 NC (Not Connected) 17 GND Ground 18 Reserved_18 NC (Not Connected) 19 Reserved_19 NC (Not Connected) 20 GND Ground 21 Reserved_21 NC (Not Connected) 22 Reserved_22 NC (Not Connected) 23 GND Ground 24 HST_WAKE_BT Host wake up BT, active high High level: 1.8V 25 CHIP_EN Enable the module, active high High level: 1.8V 26 GND Ground 27 SUSCLK_IN External sleep clock input(32.768khz) 28 W_DISABLE#1 GPIO, Default high. Require pulled up High level: 3.3V 29 PEWake# NC (Not Connected) 30 CLKREQ# NC (Not Connected) 31 PERST# NC (Not Connected) 32 GND Ground 33 REFCLKN0 NC (Not Connected) 34 REFCLKP0 NC (Not Connected) 35 GND Ground 36 PETn0 NC (Not Connected) 37 PETp0 NC (Not Connected) 38 GND Ground 39 PERn0 NC (Not Connected) 40 PERp0 NC (Not Connected) 41 GND Ground 42 Reserved_42 NC (Not Connected) 43 Reserved_43 NC (Not Connected) 44 Reserved_44 NC (Not Connected) 45 SDIO Reset SDIO reset the WIFI function, active low, require pulled up High level: 1.8V 46 SDIO Wake WLAN wake up host, active high High level: 1.8V 47 SDIO DAT3 SDIO Data Line 3 High level: 1.8V 48 SD_D2 SDIO Data Line 2 High level: 1.8V 49 SD_D1 SDIO Data Line 1 High level: 1.8V 50 SD_D0 SDIO Data Line 0 High level: 1.8V 51 SD_CMD SDIO Command Line 52 SD_CLK SDIO Clock Input 53 UART WAKE BT wake up the host, active low High level: 1.8V Page12/17

13 54 UART CTS High-Speed UART CTS 55 UART Tx High-Speed UART Data Out High level: 1.8V 56 UART Rx High-Speed UART Data In High level: 1.8V 57 UART RTS Ground 58 PCM_SYNC PCM Synchronization control 59 PCM_IN PCM data Input High level: 1.8V 60 PCM_OUT PCM data Output High level: 1.8V 61 PCM_CLK PCM Clock 62 GND Ground 63 W_DISABLE#2 Externally shut down BT, active low. Require pulled up High level: 1.8V 64 LED#2 BT LED, active low High level: 1.8V 65 LED#1 WLAN LED, active low High level: 1.8V 66 Reserved_66 NC (Not Connected) 67 HST_WAKE_BT Host wake up BT, active high High level: 1.8V 68 GND Ground 69 USB_D- NC (Not Connected) 70 USB_D+ NC (Not Connected) 71 GND Ground V 3.3V Power Supply Typical voltage: 3.3V V 3.3V Power Supply Typical voltage: 3.3V 74~96 GND Ground G1~G12 GND Ground Page13/17

14 5. Mechanical Specification 5.1 Outline Drawing(Unit: mm) (Top Side) (Bottom Side) Top View (DEV ±0.15mm) Page14/17

15 Page15/17

16 5.2 Recommended Reflow Profile Referred to IPC/JEDEC standard. Peak Temperature : <250 C Number of Times : 2 times 5.3 Patch WIFI modules installed before the notice: WIFI module installed note: 1. Please press 1 : 1 and then expand outward proportion to 0.7 mm, 0.12 mm thickness When open a stencil 2. Take and use the WIFI module, please insure the electrostatic protective measures. 3. Reflow soldering temperature should be according to the customer the main size of the products, such as the temperature set at for the MID motherboard. About the module packaging, storage and use of matters needing attention are as follows: 1. The module of the reel and storage life of vacuum packing: 1). Shelf life: 8 months, storage environment conditions: temperature in: < 40, relative humidity: < 90% r.h. 2. The module vacuum packing once opened, time limit of the assembly: Card: 1) check the humidity display value should be less than 30% (in blue), such as: 30% ~ 40% (pink), or greater than 40% (red) the module have been moisture absorption. 2.) factory environmental temperature humidity control: 30, 60% r.h.. 3). Once opened, the workshop the preservation of life for 168 hours. 3. Once opened, such as when not used up within 168 hours: 1). The module must be again to remove the module moisture absorption. 2). The baking temperature: 125, 8 hours. 3.) After baking, put the right amount of desiccant to seal packages. Page16/17

17 6. Package 6.1 Reel Packaging 2000pcs/reel Page17/17