CS 152 Computer Architecture and Engineering

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1 CS 52 Computer Architecture and Engineering Lecture 26 Mid-Term II Review John Lazzaro ( TAs: Udam Saini and Jue Sun www-inst.eecs.berkeley.edu/~cs52/ CS 52 L26: Mid-Term II Review UC Regents Fall 26 UCB

2 CS 52: What s left... Today: HKN, Mid-term II Review. Homework II due in class. Tuesday 2/5: Mid-term II, 6:-9: PM, 36 Soda. No class -2:3 that day. No electronic devices, no notes, leave backpacks in front of class... Thursday 2/7: Final presentations. slides to cs52-staff@cory by :5 PM. CS 52 L26: Mid-Term II Review UC Regents Fall 26 UCB 2

3 Mid-Term Review Session Homework II solutions Solution PDF will be on website soon after class. Study guide for Mid-Term II CS 52 L26: Mid-Term II Review UC Regents Fall 26 UCB 3

4 Q: Multithreading and Forwarding Multithreading (2 points) In class, we showed a 4-way static multithreading architecture. Below we show a variant of this architecture, that supports 2 threads instead of 4 (note the thread select line is only bit wide). The architecture uses load delay and branch delay slots; branch comparison is done in the ID stage, so that control hazards do not occur. To prevent RAW data hazards in this datapath, it is necessary to add forwarding paths. Thus, we have added the two muxes labelled Fwd. Draw in all NECESSARY forwarding paths to the FWD muxes to handle data hazards. ONLY draw in the necessary forwarding paths; DO NOT draw in forwarding paths that are not needed to prevent RAW data hazards. Points will be taken off for each unnecessary forwarding path drawn. CS 52 L26: Mid-Term II Review UC Regents Fall 26 UCB 4

5 Draw only NECESSARY inputs to Fwd muxes Instr Mem IF IR ID (Decode) IR EX IR MEM IR WB Addr Data PC T PC T2 T h d rs rs2 ws wd rs rs2 ws wd RegFile T rd rd2 WE RegFile T2 WE rd rd2 T h d T h d F w d F w d A M op A L U 32 Y M Data Memory Addr Dout Din WE MemToReg R Ext B bit Thread Select 5

6 Q2. Write-back, no write on allocate cache L: LRU bit. L indicates left set (as drawn on page) has been read or written most recently. L indicates right set has been read or written most recently. Setting V does not update L. 2 Cache Tag (28 bits) x Left most recent (L) x2 Index (2 bits) Ex: x 2 6 x x x2 x CS 52 L7: Advanced Processors I Left Right x x2 word 28 bits Writes that miss cache DO 28 bits word NOT allocate cache lines Addr Value Addr Value Addr Value x 2 x 2 x2 2 x4 24 x4 6 x24 6 x8 5 x8 3 x28 7 xc 4 xc 3 x2c 5 Main Memory Addr in hex, values in decimal 7 3 UC Regents Fall 25 UCB 6

7 Instr : SW R 6(R) L: LRU bit. L indicates left set (as drawn on page) has been read or written most recently. L indicates right set has been read or written most recently. Setting V does not update L. 2 Cache Tag (28 bits) x Left most recent (L) x2 Index (2 bits) Ex: x 2 6 x x x2 x CS 52 L7: Advanced Processors I Left Right x x2 word 28 bits Writes that miss cache DO 28 bits word NOT allocate cache lines Addr Value Addr Value Addr Value x 2 x 2 x2 2 x4 24 x4 6 x24 6 x8 5 x8 3 x28 7 xc 4 xc 3 x2c 5 Main Memory Addr in hex, values in decimal 7 3 UC Regents Fall 25 UCB 7

8 Instr : SW R 6(R) L: LRU bit. L indicates left set (as drawn on page) has been read or written most recently. L indicates right set has been read or written most recently. Setting V does not update L. Cache Tag (28 bits) x Left most recent (L) x2 Index (2 bits) Ex: x 2 6 x x x2 x CS 52 L7: Advanced Processors I Left Right x x2 word 28 bits Writes that miss cache DO 28 bits word NOT allocate cache lines Addr Value Addr Value Addr Value x 2 x 2 x2 2 x4 24 x4 6 x24 6 x8 5 x8 3 x28 7 xc 4 xc 3 x2c 5 Main Memory Addr in hex, values in decimal 7 3 UC Regents Fall 25 UCB 8

9 Instr 2: LW R2 2(R) L: LRU bit. L indicates left set (as drawn on page) has been read or written most recently. L indicates right set has been read or written most recently. Setting V does not update L. Cache Tag (28 bits) x Left most recent (L) x2 Index (2 bits) Ex: x 2 6 x x x2 x CS 52 L7: Advanced Processors I Left Right x x2 word 28 bits Writes that miss cache DO 28 bits word NOT allocate cache lines Addr Value Addr Value Addr Value x 2 x 2 x2 2 x4 24 x4 6 x24 6 x8 5 x8 3 x28 7 xc 4 xc 3 x2c 5 Main Memory Addr in hex, values in decimal 7 3 UC Regents Fall 25 UCB 9

10 Instr 2: LW R2 2(R) [no state change] L: LRU bit. L indicates left set (as drawn on page) has been read or written most recently. L indicates right set has been read or written most recently. Setting V does not update L. Cache Tag (28 bits) x Left most recent (L) x2 Index (2 bits) Ex: x 2 6 x x x2 x CS 52 L7: Advanced Processors I Left Right x x2 word 28 bits Writes that miss cache DO 28 bits word NOT allocate cache lines Addr Value Addr Value Addr Value x 2 x 2 x2 2 x4 24 x4 6 x24 6 x8 5 x8 3 x28 7 xc 4 xc 3 x2c 5 Main Memory Addr in hex, values in decimal 7 3 UC Regents Fall 25 UCB

11 Instr 3: LW R2 24(R) L: LRU bit. L indicates left set (as drawn on page) has been read or written most recently. L indicates right set has been read or written most recently. Setting V does not update L. Cache Tag (28 bits) x Left most recent (L) x2 Index (2 bits) Ex: x 2 6 x x x2 x CS 52 L7: Advanced Processors I Left Right x x2 word 28 bits Writes that miss cache DO 28 bits word NOT allocate cache lines Addr Value Addr Value Addr Value x 2 x 2 x2 2 x4 24 x4 6 x24 6 x8 5 x8 3 x28 7 xc 4 xc 3 x2c 5 Main Memory Addr in hex, values in decimal 7 3 UC Regents Fall 25 UCB

12 Instr 3: LW R2 24(R) L: LRU bit. L indicates left set (as drawn on page) has been read or written most recently. L indicates right set has been read or written most recently. Setting V does not update L. Cache Tag (28 bits) x Left most recent (L) x2 Index (2 bits) Ex: x 2 6 x x x2 x CS 52 L7: Advanced Processors I Left Right x x2 word 28 bits Writes that miss cache DO 28 bits word NOT allocate cache lines Addr Value Addr Value Addr Value x 2 x 2 x2 2 x4 24 x4 6 x24 6 x8 7 x8 3 x28 7 xc 4 xc 3 x2c 5 Main Memory Addr in hex, values in decimal 3 3 UC Regents Fall 25 UCB 2

13 Instr 4: LW R22 2(R) L: LRU bit. L indicates left set (as drawn on page) has been read or written most recently. L indicates right set has been read or written most recently. Setting V does not update L. Cache Tag (28 bits) x Left most recent (L) x2 Index (2 bits) Ex: x 2 6 x x x2 x CS 52 L7: Advanced Processors I Left Right x x2 word 28 bits Writes that miss cache DO 28 bits word NOT allocate cache lines Addr Value Addr Value Addr Value x 2 x 2 x2 2 x4 24 x4 6 x24 6 x8 7 x8 3 x28 7 xc 4 xc 3 x2c 5 Main Memory Addr in hex, values in decimal 3 3 UC Regents Fall 25 UCB 3

14 Instr 4: LW R22 2(R) L: LRU bit. L indicates left set (as drawn on page) has been read or written most recently. L indicates right set has been read or written most recently. Setting V does not update L. Cache Tag (28 bits) x Left most recent (L) x2 Index (2 bits) Ex: x 2 6 x x x2 x CS 52 L7: Advanced Processors I Left Right x x2 word 28 bits Writes that miss cache DO 28 bits word NOT allocate cache lines Addr Value Addr Value Addr Value x 2 x 2 x2 2 x4 24 x4 6 x24 6 x8 7 x8 3 x28 7 xc 4 xc 3 x2c 5 Main Memory Addr in hex, values in decimal 3 3 UC Regents Fall 25 UCB 4

15 Instr 5: SW R (R) L: LRU bit. L indicates left set (as drawn on page) has been read or written most recently. L indicates right set has been read or written most recently. Setting V does not update L. Cache Tag (28 bits) x Left most recent (L) x2 Index (2 bits) Ex: x 2 6 x x x2 x CS 52 L7: Advanced Processors I Left Right x x2 word 28 bits Writes that miss cache DO 28 bits word NOT allocate cache lines Addr Value Addr Value Addr Value x 2 x 2 x2 2 x4 24 x4 6 x24 6 x8 7 x8 3 x28 7 xc 4 xc 3 x2c 5 Main Memory Addr in hex, values in decimal 3 3 UC Regents Fall 25 UCB 5

16 Instr 5: SW R (R) L: LRU bit. L indicates left set (as drawn on page) has been read or written most recently. L indicates right set has been read or written most recently. Setting V does not update L. Cache Tag (28 bits) x Left most recent (L) x2 Index (2 bits) Ex: x 2 6 x x x2 x CS 52 L7: Advanced Processors I Left Right x x2 word 28 bits Writes that miss cache DO 28 bits word NOT allocate cache lines Addr Value Addr Value Addr Value x x 2 x2 2 x4 24 x4 6 x24 6 x8 7 x8 3 x28 7 xc 4 xc 3 x2c 5 Main Memory Addr in hex, values in decimal 3 3 UC Regents Fall 25 UCB 6

17 Q2. Answer (red numbers from last slide) L: LRU bit. L indicates left set (as drawn on page) has been read or written most recently. L indicates right set has been read or written most recently. Setting V does not update L. Cache Tag (28 bits) Left most recent (L) Index (2 bits) Ex: x 4 x CS 52 L7: Advanced Processors I Left Right x 3 word 28 bits Writes that miss cache DO 28 bits word NOT allocate cache lines Addr Value Addr Value Addr Value x x x2 x4 x4 x24 x8 7 x8 x28 Main Memory Addr in hex, values in decimal xc xc x2c UC Regents Fall 25 UCB 7

18 Q3: Finish specifying this Hamming Code data bits 4 parity bits DD9D8D7D6D5D4D₃D₂D₁D₀ P3P₂P₁P₀ Use this word bit arrangement C3C₂C₁C₀ D D9 D8 D7 D6 D5 D4 P3 D₃ D₂ D₁ P₂ D₀ P₁ P₀ signals the flipped bit position. P3 Fill in the equations for P, P2, P3 P₂ P₁ P₀ D xor D8 xor D6 xor D4 xor D₃ xor D₁ xor D₀ 8

19 Q3 Answer: Done by analysis of C3C₂C₁C₀ data bits 4 parity bits DD9D8D7D6D5D4D₃D₂D₁D₀ P3P₂P₁P₀ Use this word bit arrangement D D9 D8 D7 D6 D5 D4 P3 D₃ D₂ D₁ P₂ D₀ P₁ P₀ C3C₂C₁C₀ signals the flipped bit position. Fill in the equations for P, P2, P3 P3 D xor D9 xor D8 xor D7 xor D6 xor D5 xor D4 P2 D xor D9 xor D8 xor D7 xor D3 xor D2 xor D P D xor D9 xor D6 xor D5 xor D3 xor D2 xor D P₀ D xor D8 xor D6 xor D4 xor D₃ xor D₁ xor D₀ 9

20 line index b b b b Q4: Simple branch predictor Address of BNEZ instruction b[...] BNEZ R Loop target address 2 bits Branch Target Buffer (BTB) 28-bit address tag 28 bits b[...] PC Loop Branch History Table (BHT) N L Update BHT once taken/ not taken status is known CS 52 L7: Advanced Processors I On a miss, replace BTB for the line with the new branch tag & target. Next slide defines initial BHT N and L. UC Regents Fall 25 UCB 2

21 Simple ( 2-bit ) Branch History State N bit Prediction for Next branch ( take, not take) L bit Was Last prediction correct? ( yes, no) D Q D Q N L old N old L branch new N new L not taken taken not taken taken not taken taken not taken taken When replacing the tag value for a line, initialize branch history state to (N, L ) (for taken branches) or to (N, L ) (for not taken branches). 2

22 Branch predictor state before first inst. in trace executes 28-bit address tag x x 3 x 5 x 7 target address PC Lab PC Lab4 PC Lab6 PC Lab8 N L line index b b b b x BEQ R R2 Lab Taken x PC Lab b x 3 PC Lab4 b x 5 PC Lab6 b x 7 PC Lab8 b 22

23 x PC Lab b x 3 PC Lab4 b x 5 PC Lab6 b x 7 PC Lab8 b 2 x 34 BEQ R7 R8 Lab4 Not Taken x PC Lab b x 3 PC Lab4 b x 5 PC Lab6 b x 7 PC Lab8 b 23

24 x PC Lab b x 3 PC Lab4 b x 5 PC Lab6 b x 7 PC Lab8 b 3 x 6C BEQ R3 R4 Lab7 Not Taken x PC Lab b x 3 PC Lab4 b x 5 PC Lab6 b x 6 PC Lab7 b 24

25 x PC Lab b x 3 PC Lab4 b x 5 PC Lab6 b x 6 PC Lab7 b 4 x 58 BEQ R R2 Lab6 Taken x PC Lab b x 3 PC Lab4 b x 5 PC Lab6 b x 6 PC Lab7 b 25

26 x PC Lab b x 3 PC Lab4 b x 5 PC Lab6 b x 6 PC Lab7 b 5 x 2 BNE R5 R6 Lab3 Taken x 2 PC Lab3 b x 3 PC Lab4 b x 5 PC Lab6 b x 6 PC Lab7 b 26

27 x 2 PC Lab3 b x 3 PC Lab4 b x 5 PC Lab6 b x 6 PC Lab7 b 6 x 34 BEQ R7 R8 Lab4 Taken x 2 PC Lab3 b x 3 PC Lab4 b x 5 PC Lab6 b x 6 PC Lab7 b 27

28 x 2 PC Lab3 b x 3 PC Lab4 b x 5 PC Lab6 b x 6 PC Lab7 b 7 x 6C BEQ R3 R4 Lab7 Not Taken Q4 Answer: Branch predictor state after 7 branches complete x 2 x 3 x 5 x 6 PC Lab3 PC Lab4 PC Lab6 PC Lab7 b b b b 28

29 Q5. Router switch arbitration... Line Line Engine Inputs A B C Switch Outputs A B C Line Line Engine Line D D Line A pipelined arbitration system decides how to connect up the switch. The connections for the transfer at epoch N are computer in epochs N-3, N-2 and N-, using dedicated switch allocation wires. CS 52 L22: Routers UC Regents Fall 25 UCB 29

30 How traditional port allocation works Input Ports (A, B, C, D) Output Ports (A, B, C, D) A B C D A B C D A codes that an input has a packet ready to send to an output. Note an input may have several packets ready. Allocator returns a matrix with at most one in each row and column to set switches. Algorithm should be fair, so no port always loses... should also scale to run large matrices fast. CS 52 L22: Routers A B C D A B C D UC Regents Fall 25 UCB 3

31 Q5: Unusual Switch Fabric Port Allocation Switch Input Ports A B C D E Switch Output Ports A B C D E A 2 B 2 C D 2 2 E 2 2 A B C D E Fill in the allocation with the most highpriority packet transfers A 2 codes that an input has a high-priority packet ready to send to an output. A codes that an input has a low-priority packet ready to send to an output. A codes no packet to send. A B C D E A B C D E Fill in the allocation that transfers the most packets of any priority No need to fill in s, just show s (at most, one per row, one per column). 3

Q5 Answers: Port Allocations Switch Input Ports Switch Output

the allocation with the most highpriority packet transfers A 2

32 Q5 Answers: Port Allocations Switch Input Ports Switch Output Ports A B C D E A 2 B 2 C D 2 2 E 2 2 A B C D E A B C D E Fill in the allocation with the most highpriority packet transfers A 2 codes that an input has a high-priority packet ready to send to an output. A codes that an input has a low-priority packet ready to send to an output. A codes no packet to send. A B C D E A B C D E Fill in the allocation that transfers the most packets of any priority No need to fill in s, just show s (at most, one per row, one per column). 32

33 Tail of List Q6. Reorder Buffer: Initial Values... 7: ADD R3 R R2 8: SUB R3 R3 R 9: ADD R4 R2 R3 : SUB R5 R3 R4 : SUB R5 R3 R5 Head of List Next inst in program goes here. Question 6a (3 points). By examining the issue logic setup, fill in the values of the architected registers below, at the moment BEFORE instruction 7 executes: R R2 R R2 2 Inst # Op U E # #2 #d P P2 Pd P value Physical register numbers bits for values P2 value Pd value 7 ADD SUB ADD SUB Physical register values (in decimal) 33

34 Tail of List Q6b. Trace through instructions... Head of List Next inst in program goes here. 7: ADD R3 R R2 8: SUB R3 R3 R 9: ADD R4 R2 R3 : SUB R5 R3 R4 : SUB R5 R3 R5 Inst # Op U E # #2 #d P P2 Pd P value Physical register numbers bits for values P2 value Pd value 7 ADD SUB ADD SUB Physical register values (in decimal) 34

35 Tail of List Q6b. Trace through instructions... Head of List Next inst in program goes here. 7: ADD R3 R R2 8: SUB R3 R3 R 9: ADD R4 R2 R3 : SUB R5 R3 R4 : SUB R5 R3 R5 Inst # Op U E # #2 #d P P2 Pd P value Physical register numbers bits for values P2 value Pd value 7 ADD SUB ADD SUB Physical register values (in decimal) 35

36 Tail of List Q6b. Trace through instructions... Head of List Next inst in program goes here. 7: ADD R3 R R2 8: SUB R3 R3 R 9: ADD R4 R2 R3 : SUB R5 R3 R4 : SUB R5 R3 R5 Inst # Op U E # #2 #d P P2 Pd P value Physical register numbers bits for values P2 value Pd value 7 ADD SUB ADD SUB Physical register values (in decimal) 36

37 Tail of List Q6b. Trace through instructions... Head of List Next inst in program goes here. 7: ADD R3 R R2 8: SUB R3 R3 R 9: ADD R4 R2 R3 : SUB R5 R3 R4 : SUB R5 R3 R5 Inst # Op U E # #2 #d P P2 Pd P value Physical register numbers bits for values P2 value Pd value 7 ADD SUB ADD SUB Physical register values (in decimal) 37

38 Tail of List Q6c: Add Inst # line for: SUB R5 R3 R5 Head of List Next inst in program goes here. 7: ADD R3 R R2 8: SUB R3 R3 R 9: ADD R4 R2 R3 : SUB R5 R3 R4 : SUB R5 R3 R5 Inst # Op U E # #2 #d P P2 Pd P value P2 value Pd value 7 ADD SUB ADD SUB SUB Physical register numbers bits for values Physical register values (in decimal) 38

39 Name: CS52 Midterm 2 December 5th, 26 # Points of problems, points per problem subject to change! SSID: All the work is my own. I have no prior knowledge of the exam contents, aside from guidance from class staff. I will not share the contents with others in CS52 who have not taken it yet. Signature: Please write clearly, and put your name on each page. Please abide by word limits. Good luck! Udam Saini Jue Sun John Lazzaro Tot 39

40 Mid-Term II Facts... Eight problems But we might drop a few. Shorter problems Goal is a -page test. More Fill in the blank Fewer partial credit chances. Easier than Mid-term I Expect a mix of easier and harder problems. CS 52 L26: Mid-Term II Review # Points Tot UC Regents Fall 26 UCB 4

41 Part I: Cache and TLB Design Typical Topics Simulate a cache or a TLB by hand (like HW). Design a part of a cache to meet a specification. Design a part of a TLB to meet a specification. # Points Tot CS 52 L: Midterm I Review UC Regents Fall 26 UCB 4

42 Part II: ECC math and applications Typical Topics Hamming Code Math Parity Code Math Checksum Math Apply this math to one of a topics. # Points Tot CS 52 L: Midterm I Review UC Regents Fall 26 UCB 42

Part III: Advanced Processors Typical Topics Pipelining Memory Interleaving Superpipelining Pipelining ALUs Superscalar Dynamic Scheduling

43 Part III: Advanced Processors Typical Topics Pipelining Memory Interleaving Superpipelining Pipelining ALUs Superscalar Dynamic Scheduling Out of Order Execution Exceptions Multithreading Multicore CS 52 L: Midterm I Review # Points Tot UC Regents Fall 26 UCB 43

44 Part IV: Synchronization, Multiprocessors # Points Typical Topics 2 5 Sequential Consistency Critical Sections Cache Coherency Clusters Tot CS 52 L: Midterm I Review UC Regents Fall 26 UCB 44

45 Administrivia: Mid-term I... Starts at 6PM in 36 Soda. No class on Tuesday Assigned seating: Look for your namecard on the desk. Put all electronic devices (cell phones, caclulators, PDAs, computers) at the front of the room. Put bookbags and other personal belongings at the front of the room. CS 52 L: Midterm I Review UC Regents Fall 26 UCB 45

46 Administrivia: Mid-term I... Starts at 6PM in 36 Soda. No class on Tuesday Just writing implements at your desk (pencils, pens, erasers, etc). Test problems include useful information for the problems so, no one sheet of paper allowed for this test. You won t be able to bring one to job interviews either... CS 52 L: Midterm I Review UC Regents Fall 26 UCB 46

47 CS 52: Good luck on the mid-term! Today: HKN, Mid-term II Review. Homework II due in class. Tuesday 2/5: Mid-term II, 6:-9: PM, 36 Soda. No class -2:3 that day. No electronic devices, no notes, leave backpacks in front of class... Thursday 2/7: Final presentations. slides to by :5 PM. CS 52 L26: Mid-Term II Review UC Regents Fall 26 UCB 47

CS 152 Computer Architecture and Engineering

CS 152 Computer Architecture and Engineering Lecture 7 Pipelining I 2005-9-20 John Lazzaro (www.cs.berkeley.edu/~lazzaro) TAs: David Marquardt and Udam Saini www-inst.eecs.berkeley.edu/~cs152/ Office Hours