PoC of Structure agnostic Radio over Ethernet. Peter K. Cho, A. Kim, J. Choi Actus Networks/HFR, Inc

Transcription

1 PoC of Structure agnostic Radio over Ethernet Peter K. Cho, A. Kim, J. Choi Actus Networks/HFR, Inc

2 Compliance with IEEE Standards Policies and Procedures Subclause of the IEEE-SA Standards Board Bylaws states, "While participating in IEEE standards development activities, all participants...shall act in accordance with all applicable laws (nation-based and international), the IEEE Code of Ethics, and with IEEE Standards policies and procedures." The contributor acknowledges and accepts that this contribution is subject to The IEEE Standards copyright policy as stated in the IEEE-SA Standards Board Bylaws, section 7, and the IEEE- SA Standards Board Operations Manual, section 6.1, The IEEE Standards patent policy as stated in the IEEE-SA Standards Board Bylaws, section 6, and the IEEE-SA Standards Board Operations Manual, section 6.3, 2

3 IEEE 1914 Next Generation Fronthaul Interface Jingri Huang, Feasibility of RoE Date: : Author(s): Name Affiliation Phone [optional] [optional] Ajung Kim Sejong University akim@sejong.ac.kr Peter Cho Actus Networks/HFR Inc. choho@actusnetworks. com Jin Seek Choi Hanyang University jinseek@hanyang.ac.kr

4 Contents 1. measurement for RoE with clock from 1588v2 master 2. for RoE with 10G synce clock from CPRI 3. Estimation with RoE switch chips 4. Conclusion 4

5 RoE Presentation Time = ingress time Networking delay(transit time) processing / buffering delay 5

6 1. RoE with clock from 1588v2 master Exp. Overview Demonstration of a RoE system for feasibility Structure agonistic RoE mappers interfacing with CPRI Timing issue (experiment with no buffer management) Clock distribution mechanism 10MHz clock and 1PPS provided by 1588v2 hybrid 1588 (clock from 10G synce and 1PPS from 1588v2) frequency accuracy, jitter 6

7 Configuration Measurements with a CPRI TRx port1: RoE #1 >#2 (downlink) port2: RoE #1< #2 (uplink) ; down/uplinks are symmetric TX Clock Source : Received(slave) CPRI Link (2457.6Mbps) Pattern type :PRBS15 The same signals are fed to both ports 7

8 measurement on performance Check the CPRI alarm and CV (Code Violation) during the transmission of CPRI frames Measure the delay for various sizes of RoE payload paylord size = 48/64 CPRI Basic frames intrinsic delay = ns(16byte) x 48 frame = us (for 48 frames) = us (for 64 frames) exp. senario No. Test Case Clock distritution Remark Case #1 10G interface board loopback ( single RoE mapper board) w/o TSN 10MHz clock, 1PPS by 1588v2 single mapper board without TSN switches with inputs of 10MHz clock & 1 PPS provided by 1588v2 Case #2 Mapper2mapper (w/o TSN Switch) w/ dual CPRI ports 10MHz clock, 1PPS by 1588v2 a mapper pair without TSN switches with inputs of 10MHz clock & 1 PPS provided by 1588v2 slave (OC) of TSN switch Case #3 RoE2RoE (a mapper with a TSN switch) 10MHz clock, 1PPS by 1588v2 RoE consisting of a mapper a TSN switch with inputs of 10MHz clock & 1 PPS provided by 1588v2 slave (OC) of TSN switch Case #4 Mapper2mapper with direct 1588v2 clock direct clock fed by 1588 master a mapper pair w/o TSN sw. with direct clock fed by 1588v2 grand master 1588v2 Master accuracy issue 8

9 General Configuration : case #3. RoE to RoE RoE consisting of a mapper a TSN switch with inputs of 10MHz clock & 1 PPS provided by 1588v2 BBU GPS 1588v2 Receiver Grand Master RoE Mapper 10MHz 1PPS 1588v2 OC TSN Switch PTP Packet PSN 1588v2 OC TSN Switch 10MHz 1PPS FMC- XM10 5 FMC- XM10 5 RoE Mapper SF P RRH RoE #1(DP1) RoE#2(DP2) Port#1 CPRI Tester (slave) Port#2 CPRI Tester (slave) downlink uplink 9

10 Result Measure ingress/presentation time and delay after at least 300 counts (300sec) Check the CPRI alarm and LCV (Line Code Violation) during the transmission of CPRI signals ; no errors, LOS, LOF, LSS and alarms(rai) for RoE packets of both 48 and 64 CPRI BF frames BER<10-12 <result for PDU size of 64 CPRI frames> Case (for 64 frame ) Max RoE #1(DP1) ->#2(DP2) -> #1(DP1)[for case1] Min Avg variation Max RoE #1(DP1)<- #2(DP2) #2(DP2) [for case1] Min Avg variation 1.Board 16.80us 16.69us 16.75us 0.11us 16.96us 16.88us 16.92us 0.08us loopback 2. Map2map us 16.61us 16.53us 0.05us 16.64us 16.44us 16.53us 0.20us 3.RoE2RoE 16.78us 16.73us 16.76us 0.05us 16.83us 16.77us 16.80us 0.06us 4.map2map. with direct master clock 16.53us 16.49us 16.51us 0.04us 16.50us 16.45us 16.47us 0.05us 10

11 result for PDUsize of 48 CPRI frames Case (for 48 frame ) 1.Board loopback Max RoE #1(DP1) ->#2(DP2) #1(DP1)[for case1] Min Avg variation Max RoE #1(DP1)<- #2(DP2) #2(DP2) [for cas Min Avg Dela variati 12.65us 12.61us 12.63us 0.04us 12.52us 12.34us 12.42us 0.18u 2. Map2map us 12.58us 12.61us 0.06us 12.77us 12.58us 12.68us 0.19u 3.RoE2RoE 12.66us 12.61us 12.63us 0.05us 12.72us 12.51us 12.61us 0.21u 4.map2map. with direct master clock 12.54us 12.50us 12.52us 0.04us

12 Case #5. RoE to RoE with TSN sw over 12.6km optical fiber GPS Receiver FMC- XM10 5 RoE Mapper RoE #1(DP1) 1588v2 Grand Master 10MHz 1PPS 1588v2 OC TSN Switch PTP Packet 12.6km PSN 1588v2 OC TSN Switch 10MHz 1PPS FMC- XM10 5 RoE Mapper SF P RoE#2(DP2) CPRI Tester (slave) Port#1 Port#2 CPRI Tester (slave) Uplink (between TSN switches) over a 12.6km optical fiber Tansmission delay (about 5 µs per kilometer); 12.6km x 5us = 63us one way delays Payload Size DP #1 -> DP#2 w/o fiber spool DP #2 -> DP#1 over fiber Max Min Avg Max Min Avg 64 frame 16.90us 16.79us 16.83us 83.23us 83.06us 83.13us 12

13 Jitter measurement measurement on clock performance Measure the performance regarding clock recoverty, frequency accuracy under ITU-T G.8261/Y.1361 based profiles Layer 2 (BBU-RRH) : frequency accuracy budget Layer 1 (Fronthaul) : total jitter Fronthaul link or RoE link Fronthaul solution is applicable section of the Layer 1 CPRI link BBU (REC) and RRH (RRE). To measure the Service Access Point (SAPs) of Layer 2, BBU/RRH are needed. 13

14 Case #6. Jitter test jitter measurements on the DL and the UL will be done on the point 1 through 6 The relative jitter is expected to be of the order of 142.4ps Case #6 Jitter measurement (1) DOWN Link (2) UP Link (3) DLUL (round trip) 14

15 Case #6. Jitter TEST CASE JITTER Fronthaul jitter Estimated (1) DL 1 -> 2 Point (1) 50.17ps Point (2) 53.92ps (2) (1)= 3.75ps (2) UL: 4 -> 3 Point (4) 37.33ps Point (3) 52.73ps (4) (3) = 15.4ps Case 1. point (1) Case 1. point (2) (3) DLUL: 5<->6 Point (5) 46.64ps Point (6) 59.11ps (6) (5) = 12.47ps NOTE. After Lock, it measures the jitter during 1 min. Case 2. point (4) Case 2. point (3) Case 3. point (5) Case 3. point (6) 15

16 Result PARAMETER SPECIFICATION E2E CPRI CONNECTIVITY / ETHERNET TRAFFIC TEST value NO CV ONE WAY DELAY 16.78US (64 FRAMES) 12.61US (48 FRAMES) JITTER 3.75PS/15.4PS (UP/DOWN LINK) 12.47PS (DOWNUPLINK) BER <10-12 MAXIMUM DISTANCE 83.12US FOR 12.6KM

17 2. RoE with 10G synce clock from CPRI RoE consisting of a mapper a TSN switch with 10G synce clock extracted from CPRI BBU RoE Mapper RoE #1(DP1) 10GsyncE TSN Switch 10GsyncE PSN 10GsyncE TSN Switch 10GsyncE RoE Mapper SF P RoE#2(DP2) RRH CPRI Tester (slave) Port#1 Port#2 CPRI Tester (slave) downlink uplink 17

18 Tests for, jitter and frequency accuracy on RoE with 10G synce clock from CPRI are still in progress, with the scenario of Measure MTIE with - Network Traffic model 1 80 / 5 / 15% of the load must be min./ medium/ max. size packets (64/576/1518 octets) Maximum size packets will occur in bursts lasting between 0.1s and 3s -Network Traffic model 2 30 / 10 / 60% of the load must be min./ medium/ max. size packets (64/576/1518 octets) Maximum size packets will occur in bursts lasting between 0.1s and 3s Measure frequency drift with G.8261 test cases Test case 12 with traffic model 2 network disturbance load with 80% in the forward direction (Server-> Client) and 20% in the reverse direction (Client -> Server) for 1 hour Test case 13 with traffic model 1 network disturbance load with 80% for 1hour and disturbance with 20% for the next 1hr in the forward direction and disturbance with 50% for 1hr and with 10% for the next 1hr in the reverse direction Estimate jitter by measuring CPRI link. -> CPRI Option 3 ( Gbps) ± 0.002ppm => ± 5 bit ( < 2 ns) -> CPRI Option 7 ( Gbps) ± 0.002ppm => ± 1 bit ( < 0.5 ns)

19 3. Estimation with RoE switch chips On BS line card Clock synch (ns) RoE sw. chip PS N BB DSP PSN RoE mapper De-jitter buffer framer RRH RoE link Requirement : RoE packet jitter <1us CPRI link Phase accuracy <16ns RoE sw. chips connect CPRI radio domain & Ethernet domain phase alignment with RoE sw. chip Radio synchronization with de-jitter buffer Insert Title here Insert Date here 19

20 3. with RoE sw. vs. TDM sw RoE sw. chip RoE link CPRI link BB DSP RoE mapper De-jitter buffer framer RRH buffer Configurable buffer depth TDM sw. (switching delay~30-50ns) CPRI link BB DSP RRH buffer Insert Title here Insert Date here 20

21 3. with RoE sw. vs. TDM sw For downlink delay with 20MHz LTE signals over 20km CPRI link (transmission delay of 100us) 1 OFDMA symbol in DSP buffer (67us) de-jitter buffer depth of 0.25 packet (=128bytes 512B packets=1us), RoE sw. underperforms legacy TDM sw. only by 0.5%. RoE sw. fronthaul is competitive in regards to latency. Insert Title here Insert Date here 21

22 Conclusion and future plan for implementation Demonstration of a RoE system with RoE structure agnostic mapper interfacing with legacy radio systems variation controllable by buffering (<15ms) De jitter buffer in RoE sw. chip enables radio synchronization latency penalty of RoE, with respect to legacy radio system, is negligible > RoE sw. is a promising fronthaul solution even latencywise and can expand to in building deployment (size of BBU pools and fiber infrastructure in buildings are correlated) Other options for implementation system with 10G synce clock from CPRI ( seems to outperform those with clock from 1588v2 ) timestamp for frequency resolution and buffer management Specification on timing parameters 22

23 Thanks 23