Tessent TestKompress & Adv. Topics. Student Workbook

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1 Student Workbook 2016 Mentor Graphics Corporation All rights reserved. This document contains information that is trade secret and proprietary to Mentor Graphics Corporation or its licensors and is subject to license terms. No part of this document may be photocopied, reproduced, translated, distributed, disclosed or provided to third parties without the prior written consent of Mentor Graphics.

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3 Module 1: TestKompress Basics Objectives Course Prerequisites What Is Tessent TestKompress? What Is EDT? Why Tessent TestKompress? How Does Tessent TestKompress Impact the Design? Compression Logic Terminology Standard Test Application Process Tessent TestKompress Test Application Uncompressed ATPG versus EDT Uncompressed ATPG versus EDT (Cont.) Uncompressed ATPG versus EDT (Cont.) ATPG Test Pattern Generation Process TestKompress Pattern Generation Process Calculating Data Compression Create Patterns Report Statistics Tessent TestKompress Logic Placement External Logic Placement Internal Logic Placement Tessent TestKompress Output Files Tessent TestKompress Output Files (Cont.) Sharing Tessent TestKompress Pins Tessent TestKompress Control Signals I

4 Basic Tessent TestKompress Logic Architecture (Cont.) The Decompressor Decompressor Representative Block Diagram Tessent TestKompress Control Fill Rate Test Pattern Decompression The Compactor The Compactor (Cont.) The Compactor (Cont.) Scan Chain Masking Scan Chain Masking Solution Fault Aliasing Fault Aliasing Solution Additional Shift Cycles Additional Shift Cycles (Cont.) Bypass Logic Bypass Logic (Cont.) Lockup Cells Example: Location of Lockup Cells Pipeline Stages in the Compactor Pipeline Stages in the Compactor (Cont.) Pipeline Stages in Channel I/O Pipeline Stages in Channel I/O (Cont.) Pipeline Stages in Channel I/O (Cont.) Getting Help With Tessent Tools Getting Help With Tessent Tools (Cont.) II

5 Getting Help With Tessent Tools (Cont.) Accessing UNIX Commands From the Tool Command Line Getting Help: Useful Tool and System Commands Customer Support Summary Lab 1: Exploring the Help System Module 2: TestKompress Insertion Flows Objectives Tessent TestKompress Operation Additional Tessent TestKompress Commands Additional Tessent TestKompress Commands (Cont.) Additional Tessent TestKompress Commands (Cont.) Logic Creation Flows External and Internal Logic Creation Flows Post-Synthesis Flows Logic Creation Flows Pre-Synthesis Flow Logic Creation Flows Pre-Synthesis Flow (Cont.) Post-Synthesis External Logic Creation Post-Synthesis External Logic Creation (Cont.) Post-Synthesis External Logic Creation Flow Insert Scan Scan Chain Insertion Dofile Create EDT Logic Create EDT Logic (Cont.) Synthesize Synthesize (Cont.) III

6 Test Pattern Generation Test Pattern Generation (Cont.) Generate Patterns in Bypass Mode (Optional) Generate Patterns in Bypass Mode (Optional) (Cont.) Lab 2: Exercise 1 Post-Synth. External Logic Creation Post-Synthesis Internal Logic Creation Flow Post-Synthesis Internal Logic Creation Flow (Cont.) Post-Synthesis Internal Logic Insertion TestKompress-Based EDT Logic Insertion TestKompress-Based EDT Logic Insertion (Cont.) Synopsys DC-Based EDT Logic Insertion Synopsys DC-Based EDT Logic Insertion (Cont.) Scan Chain Insertion Scan Chain Insertion (Cont.) Tessent TestKompress Logic Creation Insertion Tessent TestKompress Logic Creation and Insertion (Cont.) Synthesize Tessent TestKompress Logic DC Synthesis Script: created_dc_script.scr DC Synthesis Script: created_dc_script.scr (Cont.) Synthesis Script: created_dc_script.scr (Cont.) Create Test Patterns Create Test Patterns (Cont.) Lab 2: Exercise 2 Post-Synth. Internal Logic Creation Pre-Synthesis External Logic Creation Pre-Synthesis External Logic Creation Flow IV

7 create_skeleton_design Input File Create a Design Interface File (External Flow Only) create_skeleton_design Inputs and Outputs Run the create_skeleton_design Utility Create Tessent TestKompress Logic Create Tessent TestKompress Logic (Cont.) Design, Integrate, and Synthesize Design Tessent TestKompress Pattern Generation Tessent TestKompress Pattern Generation (Cont.) Created_edt.dofile Created_bypass.dofile Flattened Net Names in Dofiles Created_edt.testproc File Created_bypass.testproc Compressed Test Pattern Generation Uncompressed Test Pattern Generation (Bypass) Saving Test Patterns Saving Test Patterns (Cont.) Saving Test Patterns for Verilog Simulation Pattern Reordering Why no Reordering After Saving Patterns Why no Reordering After Saving Patterns (Cont.) Why no Reordering After Saving Patterns (Cont.) Summary Lab 2: Exercise 3 Pre-Synth. Internal Logic Creation V

8 Lab 2: Exercise 4: Logic Options (Optional) Module 3: DRC and Simulation Mismatch Debug Objectives Tessent TestKompress K Design Rule Checks K19 Design Rule Check K19 Design Rule Check (Cont.) Using Gate Reporting Using Gate Reporting (Cont.) Using Gate Reporting (Cont.) Using Gate Reporting (Cont.) Using Gate Reporting (Cont.) Inverted Signals (Cont.) K20 Design Rule Check K20 Design Rule Check (Cont.) K21 Design Rule Check K22 Design Rule Check K22 Design Rule Check (Cont.) Possible DRC Error Causes Possible DRC Error Causes (Cont.) Summary: Troubleshooting K19 and K22 Violations EDT Finder EDT Finder Usage Common EDT Finder Design Rule Checks EDT Finder F Rules in DFTVisualizer EDT Logic Visualization VI

9 F DRC Rule Debugging Report EDT Finder Report EDT Finder (Cont.) Design Rule Checking: More Information Lab 3 Exercise 1: Tessent TestKompress (DRC) Pattern Simulation and Mismatch Debug Analyze Simulation Mismatches Automatic Simulation Mismatch Analysis Flow Simulation Mismatch Debugging Saving Pattern Files for Simulation Mismatch Debugging Summary Lab 3 Exercise 2: Auto. Pattern Sim. Mismatch Analysis Module 4: Maximizing Performance Objectives Maximizing Performance Evaluating Performance Evaluating Performance (Cont.) Improving Performance Through Analysis Chain to Channel Ratio: Analyze Compression Analyze Compression Analyze Compression: Examples Modular EDT Analyze Compression: Example Analyze Compression Procedure Analyzing Results Analyzing Results (Cont.) VII

10 Automating Compression Analysis Compression Advisor Compression Advisor (Cont.) Resolving Compression Issues EDT Test Points Test Point Types Insertion Flows Command Overview Command Overview (Cont.) Example Flow Post Scan Insertion Example Flow Post Scan Insertion: TP Stitching Report Test Points Test Point Advisor Summary Lab 4: Compression and Performance Module 5: Modular TestKompress Objectives Top Level TestKompress Implementation Options Top Level Modular Tessent TestKompress Implementation Benefits of Modular Tessent TestKompress Modular TestKompress Implementation Core Mapping Module Level Core Mapping Flow Module Level Core Mapping Flow (Cont.) Tessent Core Description (.tcd) File VIII

11 Top Level Core Mapping Flow Core Mapping at the Top Level Top Level Pattern Generation Modular Tessent TestKompress Rules Broadcasting to Identical Blocks Broadcasting to Identical Blocks Implementation Modular TestKompress With Channel Sharing Modular TestKompress with Channel Sharing (Cont.) Block-Level EDT Setup Example: No Channel-Sharing Example: Channel-Sharing Case Example: Channel-Sharing Case Channel Sharing Implementation Channel Sharing Implementation (Cont.) Top-Level Netlist Asymmetrical Channel Configuration Summary Lab 7: Modular Tessent TestKompress Flow Module 6: Additional Topics Objectives Set_Edt_Options On -Force_1hot_Masking Chain Masking Dual Tessent TestKompress Configurations Dual Configuration Tessent TestKompress Logic Hybrid TestKompress / LogicBIST IX

12 Multi-Threaded ATPG (Distributed Processing) User Defined Fault Model (UDFM) ATPG Model - Review User Defined Fault Model: Test Alternatives User Defined Fault Model: Gate Exhaustive User Defined Fault Model: Gate Exhaustive (Cont.) User Defined Fault Model: Cell-Aware Cell-Aware Model Creation: Layout Extraction Cell-Aware Model Creation: Layout Extraction (Cont.) Cell-Aware Model Creation: Fault Simulation Cell-Aware Model Creation: Model Generation Cell-Aware Model Creation: Usage More Information Low Power / Power Aware ATPG Control and Observe Test Cube Reducing Switching Activity: Shift (Non-EDT) Reducing Switching Activity: Shift (EDT) Limiting Switching During Capture (EDT and Non-EDT) Basic Usage Flow for Low Power ATPG (EDT) EDT Power Control Block Diagram Load/Response Shift Switching Activity Low Power ATPG Flow Example 1: Power Metrics Reporting Example 2: Power Metrics Reporting Example 3: Power Metrics Reporting X

13 Example 4: Pattern Filtering Low-Power / Power-Aware Test Flow IEEE1801 (UPF 2.0) and CPF Usage Overview Usage Overview (Cont.) Test Sequencing Power State During Scan Test Testing Low Power Components More Information Motivations for Low Pin Count Test Top Level Routing Congestion Low Channel TestKompress Impact of Scan Channel Reduction Tessent TestKompress Standard Pin Test Access Overlapping Use of Scan Clock With EDT Clock Low Pin Count Test Access Low Pin Count Controller Type Internally Generated EDT Signals: Overview Low Pin Count Controller Type Low Pin Count Controller Type Tessent TestKompress Three Pin Controller: Overview Three Pin Controller Overview: Where to Get Help Accessing SupportNet Material Customer Support XI

14 Customer Support (Cont.) Related Courses Summary No Lab XII