Calibre Fundamentals: Writing DRC/LVS Rules. Student Workbook

Transcription

1 DRC/LVS Rules Student Workbook 2017 Mentor Graphics Corporation All rights reserved. This document contains information that is trade secret and proprietary to Mentor Graphics Corporation or its licensors and is subject to license terms. No part of this document may be photocopied, reproduced, translated, distributed, disclosed or provided to third parties without the prior written consent of Mentor Graphics.

2 Layout Verification Process Flow for nmlvs Task: Invoke Calibre nmlvs Task: Review the Extraction Report Task: Review the LVS Reports LVS Report Components LVS Summary Report Task: Invoke RVE to View nmlvs Results The LVS RVE Window Task: Cross-Probe LVS Results Lab Exercise Module 2: Basic SVRF Job Statements Objectives The SVRF Language Basic Calibre DRC/LVS Job Statements Part I Task: Specify Rule File Comments Task: Specify Layout Information Task: Include Another SVRF File Pre-Processor Directives Task: Use Conditional Execution Rule File Variables Using a Rule File Variable in a Comment Basic Calibre DRC/LVS Job Statements Part II Task: Specify Output Information Task: Specify Output Format II

3 Task: Grouping Rule Checks Task: Execute Selected Rule Checks Task: Disable Selected Rule Checks Task: Limit Result Count Task: Exclude Specified Cell(s) Task: Specify nmdrc Options Basic Calibre DRC/LVS Job Statements Part III Task: Specify Source Information Task: Specify Output Information Task: Specify nmlvs Options Lab Exercise Module 3: Rule File Implementation Basics Objectives Working With Foundry Rules Rule File Basics Rule File Header Comments Identify Drawn Layers Layer Mapping Example of Using the LAYER MAP Statement When Drawn Layers Are Not Enough Derived Layers Creating Derived Layers With Boolean Operations The SVRF Boolean Operations The Boolean AND Operation III

4 The Boolean OR Operation The Boolean NOT Operation The Boolean XOR Operation Summary Lab Exercise Module 4: Dimensional Check Basics Objectives Implementing Dimensional Checks What Is A Scalable Process? Using the MOSIS SCMOS Process Working With Foundry Rules Spec Example Metal1 Rules Dimensional Checks Calibre Dimensional Checks Geometric Data Types Edges Must Face Each Other Which Edge Pairs Will Be Checked? DRC Constraints The PRECISION Statement Calibre Edge-Based Dimensional Checks Dimensional Check Metrics Calibre Rule Checks Rule Check Step 1 Define the "Skeleton" Rule Check Step 2 Code the Dimensional Check IV

5 Rule Check Step 3 Add User Comments Coding the Minimum Spacing Rule Coding the Contact Enclosure Rule Contact Enclosure Rule Output Using A Layer Set Review: Layers and Layer Operations The COPY Layer Operation References Lab Exercise Module 5: Using Dimensional Check Secondary Keywords Objectives Review Which Edges Are Checked? Edge Breaking A Case for Checking Abutting Edges The ABUT Keyword Another Case for Abutting Edges The SINGULAR Keyword Modifying Rule Output The SCMOS Poly Rules Enhancing a Poly Rule Implementing the Well Rules Coding the Well Minimum Width Rule Coding the Well Minimum Spacing Rule The CONNECTED Keyword V

6 Summary Lab Exercise Module 6: Additional Dimensional Check Keywords Objectives Review Using Dimensional Check Keywords Implementing the Poly2 Capacitor Rules A Case for Global Derived Layers Review Local Versus Global Derived Layers A Case for Checking Overlapping Edges The OVERLAP Keyword More Secondary Keywords The Metal2 Rules Extending the Via Enclosure Rules The OUTSIDE ALSO and INSIDE ALSO Keywords Measuring Notches and Spaces The PROJECTING Keyword PROJECTING Examples Intersection Re-Visited The INTERSECTING ONLY Keyword Other Dimensional Check Keywords Summary Lab Exercise Module 7: Additional SCMOS Layer Operations Objectives VI

7 Review Dimensional Checks Metal1 Rules Revisited The WITH WIDTH Layer Operation Implementing the Wide Metal1 Rule Poly Contact Rules Revisited Implementing the Contact Size Rule First Attempt Implementing the Contact Size Rule Second Attempt The RECTANGLE Operation Via Rules Implementing the Via Size Rule First Attempt Implementing the Via Size Rule Second Attempt The OUTSIDE Operation Revisiting the Via Enclosure Rules The INSIDE Operation Finding Bad Nwells The ENCLOSE Operation Poly Rules Implementing the Gate Extension Rule First Attempt The Touch Operation Implementing the Gate Extension Rule Second Attempt The EDGE Layer Operations The EDGE Layer Operations Examples The CONVEX EDGE Operation The EXPAND EDGE Operation Summary VII

8 Lab Exercise Module 8: More Layer Operations Objectives Additional Layer Operations The INTERACT Layer Operation The SIZE Layer Operation Basic Form The SIZE Layer Operation OVERLAP ONLY The SIZE Layer Operation UNDEROVER/OVERUNDER The SIZE Layer Operation INSIDE OF/OUTSIDE OF SIZE Example The GROW and SHRINK Layer Operations GROW and SHRINK Examples The LENGTH Layer Operation The WITH EDGE Layer Operation An Interesting Question Layer Constructors and Layer Selectors Layer of Origin The Impact of Layer of Origin The AREA Layer Operation The DONUT Layer Operation The HOLES Layer Operation The HOLES Layer Operation Examples The NET Layer Operation The EXTENT DRAWN Layer Operation VIII

9 The DENSITY Layer Operation DENSITY Example The RECTANGLES Layer Operation RECTANGLES Example Summary Lab Exercise Module 9: Antenna Rules Objectives Antenna Effect Antenna Theory Antenna Rule Basics Building the Layout Connectivity Model The CONNECT Operation The NET AREA RATIO Statement Basic Form Example of NET AREA RATIO Basic Form The NET AREA RATIO Statement RDB Keyword Example of NET AREA RATIO RDB The NET AREA RATIO Statement BY LAYER Keyword Example of NET AREA RATIO RDB BY LAYER Improving Antenna Accuracy The DRC INCREMENTAL CONNECT Statement The NET AREA RATIO Statement ACCUMULATE Keyword Example of NET AREA RATIO ACCUMULATE NAR Accumulation Example IX

10 Summary Lab Exercise Module 10: Rule File Optimization Objectives Achieving Rule File Optimization Writing Efficient SVRF Code How Calibre Maximizes Capacity Layer Operation Scheduling An Example Reading Operation Information From the Log File Capturing the Log File Calibre DRC-H Layer Statistics First Line Calibre DRC-H Layer Statistics Second Line Calibre DRC-H Layer Statistics Third Line What are LVHEAP Statistics? Layer Generation Naming Conventions Layer Generation Scheduling The LogView Utility Using the LogView Utility Concurrency Concurrency Example Data Reduction Data Reduction Example Using Alternative Approaches Using Alternative Approaches: Example X

11 Using Secondary Keywords Using Secondary Keywords Using A Different Operation and Secondary Keywords Using CONNECT Help Calibre Develop Good Hierarchy Layout Base Layer General Optimization Tip Summary Lab Exercise Module 11: Properties and Equation-Based DRC Objectives Back to Basics Layer Properties Example Automatic Property Creation Property Operations DFM PROPERTY Basic Syntax Property Expressions Property Expression Operators Property Expression Math Functions Selected Measurement Functions DFM FUNCTION Basic Syntax Creating Layer Output With Properties DFM RDB Basic Syntax DFM COPY Basic Syntax XI

12 DFM PROPERTY Layer Clustering DFM PROPERTY Cluster Syntax Layer Cluster Example # Measurement Functions for Secondary Layers Layer Cluster Example # Layer Cluster Example # Equation-Based DRC Traditional DRC Example Traditional DRC Implementation Traditional DRC Limitations Equation-Based DRC Example Equation-Based DRC Implementation Lab Exercise Module 12: Working with Layout Data Objectives The Problem Relating Layout Coordinates to Constraint Values Layout Magnify Fixing A Rule File/Layout Precision Mismatch Using LAYOUT PATH Options Summary Lab Exercise Module 13: Establishing Connectivity Objectives XII

13 Connectivity Extraction Terminology Calibre Connectivity Extraction Process Nets How Calibre Establishes Connectivity The CONNECT Operation The SCMOS Connectivity Rules What Are Soft Connections? Soft Connection Example The SCONNECT Operation SCONNECT Example The LVS SOFTCHK Statement Locating Soft Connections With the SCONNECT Operation LVS REPORT OPTION S Implementing the SCMOS Well Connectivity Rules The LVS ABORT ON SOFTCHK Statement Initial Correspondence Points Summary Lab Exercise Module 14: Working With Text Objectives Working With Layout Text Finding and Using Layout Text The TEXT LAYER Statement The PORT LAYER TEXT Statement XIII

14 PORT LAYER TEXT Examples The TEXT DEPTH STATEMENT Hierarchical Text Example How to Attach Text Labels to Target Objects The ATTACH Statement Example of Explicit Label Attachment Example of Implicit Label Attachment The LABEL ORDER Statement Example of Free Label Attachment Text Attachment Priority Inserting Text Objects Into the Database The LAYOUT TEXT Statement The TEXT Statement The Calibre Text Process Summary Lab Exercise Module 15: Devices and Device Properties Objectives From Layout to Netlist Device Elements The DEVICE Statement Device Recognition A Recap The Resistor Definition Built-In Devices XIV

15 PMOS Transistor Definition Capacitor Definition Device Subtypes Auxiliary Layers Specifying Additional Pin Information Built-In Device Properties The Built-In Language Built-In Language Structure Built-In Language Functions Built-In Language Units The Adjustable Resistor Property Computation Debugging Property Routines Debug Output for Adjustable Resistor Using TRACE PROPERTY Invoking Tcl Procedures Using Layer Properties Custom Devices A Custom Device Based On A Built-In Device A Fully-Custom Device Summary Lab Exercise Module 16: Macros and Tcl Verification Format Objectives Defining Macros XV

16 Calling Macros Tcl Verification Format (TVF) Overview TVF Benefits SVRF and Compile-Time TVF Comparison Compile-Time TVF Example Runtime TVF TVF FUNCTION Syntax Layer Functions Available to TVF FUNCTION Layer Operations Available to TVF FUNCTION TVF Layer Operation Syntax TVF FUNCTION Example: Check Layer Usage in a Design Lab Exercise XVI