CS241 Computer Organization Spring Introduction to Assembly

Transcription

1 CS241 Computer Organization Spring 2015 Introduction to Assembly

2 Outline! Rounding floats: round-to-even! Introduction to Assembly (IA32) move instruction (mov) memory address computation arithmetic & logic instructions (add, imul, xor, shr, ) stack frame HW#3 due today Read: CS:APP2 Chapter 3, sections IA32 Overview (available in Online References) Quiz on 2s-complement & float Tuesday, 2/10 Lab#1 Datalab due Feb. 24, teams encouraged Exam#1 Thursday, Feb. 19, 8:00 pm

3 Floating-Point: Distribution of Values 6-bit IEEE-like format e = 3 exponent bits f = 2 fraction bits Bias is = 3 s exp frac Notice how the distribution gets denser toward zero Denormalized Normalized Infinity

4 Distribution of Values (close-up view) 6-bit IEEE-like format e = 3 exponent bits f = 2 fraction bits Bias is 3 s exp frac Denormalized Normalized Infinity

5 Interesting Numbers {single,double} Description exp frac Numeric Value Zero Smallest Pos. Denorm {23,52} x 2 {126,1022} Single 1.4 x Double 4.9 x Largest Denormalized (1.0 ε) x 2 {126,1022} Single 1.18 x Double 2.2 x Smallest Pos. Normalized x 2 {126,1022} Just larger than largest denormalized One Largest Normalized (2.0 ε) x 2 {127,1023} Single 3.4 x Double 1.8 x

6 Special Properties of Encoding FP Zero Same as Integer Zero All bits = 0 Can (Almost) Use Unsigned Integer Comparison Must first compare sign bits Must consider -0 = 0 NaNs problematic Will be greater than any other values What should comparison yield? Otherwise OK Denorm vs. normalized Normalized vs. infinity

7 Rounding! Round to (nearest) even *Default *! Rounding in binary: lsb should be 0 (even) example: frac bits? 5 frac bits? 7 frac bits?

8 Creating Floating Point Number Steps Normalize to have leading 1 Round to fit within fraction Postnormalize to deal with effects of rounding 7 6 s exp 3 2 frac 0 Case Study Convert 8-bit unsigned numbers to tiny floating point format Example Numbers

9 Normalize 7 6 s exp 3 2 frac 0 Requirement Set binary point so that numbers of form 1.xxxxx Adjust all to have leading one Decrement exponent as shift left Value Binary Fraction Exponent

10 Postnormalize Issue Rounding may have caused overflow Handle by shifting right once & incrementing exponent Value Rounded Exp Adjusted Result /6 64

11 Assembly IA32 The traditional x86 x86-64/em64t The emerging standard Presentation Book has IA32 References for x86-64 Lecture will cover both

12 Definitions Architecture: (also instruction set architecture: ISA) The parts of a processor design that one needs to understand to write assembly code. Architecture examples: instruction set specification, registers. Example ISAs (Intel): x86, IA, IPF Microarchitecture: Implementation of the architecture. Microarchitecture examples: cache sizes and core frequency.

13 Definitions Architecture: (also instruction set architecture: ISA) The parts of a processor design that one needs to understand to write assembly code. Example ISAs (Intel): x86, IA, IPF Microarchitecture: Implementation of the architecture. Architecture examples: instruction set specification, registers. Microarchitecture examples: cache sizes and core frequency.

14 Intel x86 Processors Totally dominate computer market Evolutionary design Backwards compatible up until 8086, introduced in 1978 Added more features as time goes on Complex instruction set computer (CISC) Many different instructions with many different formats But, only small subset encountered with Linux programs Hard to match performance of Reduced Instruction Set Computers (RISC) But, Intel has done just that!

15 Intel x86 Evolution: Milestones Name Date Transistors MHz K 5-10 First 16-bit processor. Basis for IBM PC & DOS 1MB address space K First 32 bit processor, referred to as IA32 Added flat addressing Capable of running Unix 32-bit Linux/gcc uses no instructions introduced in later models Pentium 4F M First 64-bit processor Meanwhile, Pentium 4s (Netburst arch.) phased out in favor of Core line

16 Intel x86 Processors: Overview Architectures Processors X X86-32/IA32 MMX SSE SSE2 SSE3 X86-64 / EM64t SSE Pentium Pentium MMX Pentium III Pentium 4 Pentium 4E Pentium 4F Core 2 Duo Core i7 time IA: often redefined as latest Intel architecture

17 Intel x86 Processors, contd. Carnegie Mellon Machine Evolution M Pentium M Pentium/MMX M PentiumPro M Pentium III M Pentium M Core 2 Duo M Added Features Instructions to support multimedia operations Parallel operations on 1, 2, and 4-byte data, both integer & FP Instructions to enable more efficient conditional operations Linux/GCC Evolution Very limited

18 New Species: ia64, then IPF, then Itanium, Name Date Transistors Itanium M First shot at 64-bit architecture: first called IA64 Radically new instruction set designed for high performance Can run existing IA32 programs On-board x86 engine Joint project with Hewlett-Packard Itanium M Big performance boost Itanium 2 Dual-Core B Itanium has not taken off in marketplace Lack of backward compatibility, no good compiler support, Pentium 4 got too good

19 x86 Clones: Advanced Micro Devices (AMD) Historically AMD has followed just behind Intel A little bit slower, a lot cheaper Then Recruited top circuit designers from Digital Equipment Corp. and other downward trending companies Built Opteron: tough competitor to Pentium 4 Developed x86-64, their own extension to 64 bits Recently Intel much quicker with dual core design Intel currently far ahead in performance em64t backwards compatible to x86-64

20 Intel s 64-Bit Intel Attempted Radical Shift from IA32 to IA64 Totally different architecture (Itanium) Executes IA32 code only as legacy Performance disappointing AMD Stepped in with Evolutionary Solution x86-64 (now called AMD64 ) Intel Felt Obligated to Focus on IA64 Hard to admit mistake or that AMD is better 2004: Intel Announces EM64T extension to IA32 Extended Memory 64-bit Technology Almost identical to x86-64! Meanwhile: EM64t well introduced, however, still often not used by OS, programs

21 Anatomy of a Computer: 5 components Personal Computer Computer Processor (active) Control ( brain ) Datapath ( brawn ) Memory (passive) (where programs & data live when running) Devices Input Output Keyboard, Mouse Disk (where programs & data live when not running) Display, Printer

22 Assembly Characteristics: Operations Perform arithmetic function on register or memory data Transfer data between memory and register Load data from memory into register Store register data into memory Transfer control Unconditional jumps to/from procedures Conditional branches

23 Integer Registers (IA32) Origin (mostly obsolete) %eax %ax %ah %al accumulate general purpose %ecx %edx %ebx %esi %cx %dx %bx %si %ch %dh %bh %cl %dl %bl counter data base source index %edi %di destination index %esp %sp stack pointer %ebp %bp base pointer 16-bit virtual registers (backwards compatibility)

24 Move instruction: mov IA32 instructions:! movl moves an int (4 bytes) transfer reg reg, reg mem, mem reg Memory addressing:! D(Rb,Ri,S) Mem[Reg[Rb]+S*Reg[Ri]+ D] D displacement 1, 2, or 4 bytes Rb Base register: Any of 8 integer registers Ri Index register: Any, except for %esp (or %ebp) S: Scale: 1, 2, 4, or 8

25 Memory layout of a process /* add 1 to x */ int main() { int x = 17; FP (%ebp) SP (%esp) x = x + 1; return 0; } PC

26 /* add1.c */ int main() { } int x = 17; x = x + 1; return 0; compile with gcc c S -m32 add1.c.file.text.globl main.type main: leal andl pushl pushl movl pushl subl movl addl movl addl popl popl leal ret.size.ident "add1.c" 4(%esp), %ecx $-16, %esp -4(%ecx) %ebp %esp, %ebp %ecx $16, %esp $17, -8(%ebp) $1, -8(%ebp) $0, %eax $16, %esp %ecx %ebp -4(%ecx), %esp main,.-main "GCC: (GNU) 4.1.2