Synaptic Labs' AXI HyperBus Memory Controller (HBMC) IP for Xilinx FPGA Devices Tutorial

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Synaptic Labs' AXI HyperBus Memory Controller (HBMC) IP for Xilinx FPGA Devices Tutorial X-T001A: A Vivado based MicroBlaze Reference design with a simple application running on a HyperRAM device

This tutorial is targeted specifcally to the wide range of low cost TE0725 family of FPGA System on Module (SoM) boards from Trenz Electronic GmbH.

1 Synaptic Labs' AXI HyperBus Memory Controller (HBMC) IP for Xilinx FPGA Devices Tutorial X-T001A: A Vivado based MicroBlaze Reference design with a simple application running on a HyperRAM device using S/Labs' HBMC IP This tutorial describes a simple reference design for S/Labs HBMC IP for Xilinx FPGA Devices. This tutorial is targeted specifcally to the wide range of low cost TE0725 family of FPGA System on Module (SoM) boards from Trenz Electronic GmbH. This reference design can be easily adapted by the reader to support other Xilinx FPGA based boards. This tutorial describes key aspects of a pre-confgured Vivado reference project and then walks through the process of generating and compiling that Vivado project. This tutorial then describes how to compile the example MicroBlaze source code, integrate the frmware into the FPGA bitstream and then run the reference design on the development board. The reference project for this Tutorial is bundled with a Free Trial License for the full edition of S/Labs HBMC IP for Xilinx FPGA devices. No customer registration is required. No License Key installation is required. Please note: Trenz Electronic GmbH are in the process of creating several offcial reference designs for their wide range of HyperBus enabled reference boards. Those reference designs will include a comparable Free Trial License HBMC IP bundle for Xilinx and Intel FPGA devices. You can fnd Trenzzs wide range of HyperBus enabled reference boards on the link below: X-T Jul info@synaptic-labs.com V5.4 page 1

2 Table of Contents Set-Up Requirements:...3 Step 1: Obtain core materials Contents of the reference project Reference Project Implementation on Vivado Check the correct FPGA device is selected Open the reference Block design project Synthesize and assemble the Design Generate the bitstream Preparing the frmware Open the Xilinx SDK Create a simple application and BSP Confgure the Board Support Package (BSP) Confgure the Linke script Build the MicroBlaze Application Program the FPGA Bitstream into the FPGA device Run the Dhrystone application...14 X-T Jul info@synaptic-labs.com V5.4 page 2

3 Set-Up Requirements Step 1: Obtain core materials a) Download and install Xilinx Vivado ( or later) on your PC. Please ensure that your PC meets the required minimum specifcation. Step 2: Read the License Agreement a) If you have not already done so, please read S/Labs License and Confdentiality Agreement for the HBMC IP here: Agreement.pdf Step 3: Download the reference project a) By downloading, installing, copying or Using the Licensed Product bundled in the reference project below, You acknowledge that You have read the above Agreement, understand it, accept it and agree to be bound by all its Provisions: Xilinx/SynapticLabs-HBMC-Tutorial001A-HyperBlaze.zip b) Please note: S/Labsz AXI HBMC IP for Xilinx Devices is already installed in the project directory/ip_lib folder. No License Key is required to enable the HBMC IP. Step 4: Optional Registration a) If you would like to receive notifcations when the next version of S/Labs' HMBC IP for Xilinx FPGA is published, or if you would like to download the latest version of S/Labs HBMC IP for Xilinx FPGA, please register on the following link: X-T Jul V5.4 page 3

4 1. Contents of the reference design project Synaptic Labs' HyperBus Memory Controller (HBMC) reference design project includes the following fles and directories: The HyperBlaze folder contains the Vivado project fles for this reference project. The HyperBlaze/ip_lib/sll_axi_hbmc_demo folder contains S/Labs HBMC encrypted IP. The HyperBlaze/ip_lib/sll_axi_hbmc_demo/HyperRAM.xdc fle will contain a typical constraint fle for Trenz Te0725 development board. Note: Synaptic Labs' HyperBus Memory Controller (HBMC) IP bundled with this IP can not be simulated with the Xilinx Simulator. Please contact S/Labs on info@synaptic-labs.com if you require Simulation support. X-T Jul info@synaptic-labs.com V5.4 page 4

2. Reference Project Implementation on Vivado In the menu bar of Vivado select File Open Project Select the fle HyperBlaze.xpr in the project directory Click the [ Open ] button. 2.

5 2. Reference Project Implementation on Vivado In the menu bar of Vivado select File Open Project Select the fle HyperBlaze.xpr in the project directory Click the [ Open ] button. 2.1 Check the correct FPGA device is selected Ensure that the FPGA Project Part matches the one being used in your design. X-T Jul info@synaptic-labs.com V5.4 page 5

6 2.2 Open the reference Block design project In the Flow Integration section of Vivado, locate the IP Integrator and open the block design. Click the [ Generate Block Design ] button to complete this step. 2.3 Synthesize and assemble the Design Go to the Vivado Flow Navigator section. Select: Implementation Run Implementation 2.4 Generate the bitstream Go to the Vivado Flow Navigator section. Select: Program and Debug Generate Bitstream X-T Jul info@synaptic-labs.com V5.4 page 6

3. Preparing the frmware In Vivado, the hardware needs to be exported.

File Export Export Hardware Make sure to tick the [x] Include bitstream

1 Open the Xilinx SDK In Vivado, go to the menu bar and select: File

7 3. Preparing the frmware In Vivado, the hardware needs to be exported. This is used by Xilinx SDK to create the board support package. File Export Export Hardware Make sure to tick the [x] Include bitstream feld. 3.1 Open the Xilinx SDK In Vivado, go to the menu bar and select: File Launch SDK Click the [ OK ] button. A new window, similar to the one below will open. X-T Jul info@synaptic-labs.com V5.4 page 7

8 3.2 Create a simple application and BSP We need to create a MicroBlaze application, and MicroBlaze board support package for that application: In the Xilinx SDK window, go the menu bar and select: File New Application Project A window, similar to the one above will open. Select a Project name. In this example, we are using Dhrystone as the project name. Ensure that: [x] Use default location is ticked. Leave all the other options to their default values Press the [ Finish ] button to complete the current step. X-T Jul info@synaptic-labs.com V5.4 page 8

Press Next to enter the Application selection menu. We now need to select a template from the Project Template list. In this example, select the Dhrystone template.

9 Press Next to enter the Application selection menu. We now need to select a template from the Project Template list. In this example, select the Dhrystone template. Click the [ Finish ] button to complete the current step. The Xilinx SDK will now generate: a Dhrystone folder that contains the dhrystone source fles. a Dhrystone_bsp folder that contains the Board Support Package (BSP) fles. X-T Jul info@synaptic-labs.com V5.4 page 9

10 3.3 Confgure the Board Support Package (BSP) The MicroBlaze BSP must be confgured before we can compile the source code. In the Project Explorer tab, right click on: Dhrystone_bsp Modify this BSP's Setting. Click on the standalone Tab. Ensure that the stdin and stdout are mapped to the JTAG UART (mdm_1) X-T Jul V5.4 page 10

11 3.4 Confgure the Linker script Click on the Dhrysone application. In Xilinx SDK, open the linker script (Xilinx Generate Linker Srcipt). For this tutorial example, we are going to: Map the instruction code (.text) in the HyperRAM memory Map all other data regions (.bss,.heap,.rodata,.rwdata,.stack) to the HyperRAM memory This will map all memory regions generated by the GCC tools to the HyperRAM memory region. Now: Click on the [ Generate ] button on the bottom right hand corner. X-T Jul info@synaptic-labs.com V5.4 page 11

12 3.5 Build the MicroBlaze Application We now want to run the compiler and linker: Go to the Xilinx SDK eclipse window. Go to the menu bar and select: Project ->Build All The Dhrystone executable frmware (.ELF) is now generated. The.ELF can be downloaded directly into HyperRAM using the MicroBlaze II Debugger. X-T Jul V5.4 page 12

4. Program the FPGA Bitstream into the FPGA device Connect the Trenz TE0725 Evaluation kit to the USB port of your computer Connect a 3.3V supply to the Trenz TE0725 Evaluation kit.

13 4. Program the FPGA Bitstream into the FPGA device Connect the Trenz TE0725 Evaluation kit to the USB port of your computer Connect a 3.3V supply to the Trenz TE0725 Evaluation kit. In Vivado Program and Debug Section, open the target communication. Vivado Program and Debug Section Open Hardware manager Open target Auto Connect. Program the FPGA Vivado Program and Debug Section Open Hardware manager Program Device. Click the [ Program ] button. X-T Jul info@synaptic-labs.com V5.4 page 13

14 5. Run the Dhrystone application In the Xilnx SDK, click on Run Run as Launch on Hardware Messages similar to the one below should be displayed in the Virtual Terminal. X-T Jul V5.4 page 14

Synaptic Labs HyperBus Memory Controller (HBMC) Tutorial for Intel FPGA devices

Synaptic Labs HyperBus Memory Controller (HBMC) Tutorial for Intel FPGA devices Benjamin Gittins Chief Technical Officer Mbl: +995 551 026 588 b.gittins@synaptic-labs.com Synaptic Laboratories Ltd. Company ID 41272593 www.synaptic-labs.com info@synaptic-labs.com Monday, July 16, 2018