10/02/2015 Vivado Linux Basic System
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1 Contents 1 History Introduction Open Vivado New Project Project Settings Create Processor System New Block Diagram Generate Output Products HDL Wrapper Implement Design Export Hardware Launch SDK New Application Project Hello Bootloader Bootloader debug flags Program FPGA Debug Setup Configure Debug Application Boot Image Booting from Micro SD card Micro SD card preparation Set Avnet MicroZed Development Board Boot Mode Configure HyperTerminal Reset Avnet MicroZed Development Page 1 of 40
2 1 History Revision Date Author Description A 5/2/2015 info@syfer.com.au Initial Revision Table 1 : History 2 Introduction This document describes how to build a Processor System (PS) system for the Avnet MicroZed development board using Vivado on Ubuntu LTS (64-bit). Ubunto LTS (64-bit) Guest is running Oracle VM VirtualBox on a Windows 7 Professional Service pack 1 (64-bit) Host. Create Block Diagram Implement design Export hardware to SDK Launch SDK Create application Create bootloader Debug application (Avnet MicroZed) Create boot image Boot FPGA from Micro SD card (Avnet MicroZed) Page 2 of 40
3 3 Open Vivado Open terminal ctrl+alt+t. $ source /opt/xilinx/vivado/2014.4/settings64.sh $ vivado & Figure 1: Open Vivado Figure 2: Vivado Page 3 of 40
4 4 New Project Create a new Vivado project. File -> New Project. Figure 3: Vivado Click on the Next button. Figure 4: New Project - Create a New Vivado Project Page 4 of 40
5 Select Project Name and Location. Project name: -> basic_test Project location: -> /home/syfer/projects/basic_test Click on the Create project subdirectory check box to un-check. Click on the Next button. Note: If you have permission problems then use sudo chmod R 777 /home/syfer/projects Figure 5: New Project - Project Name Page 5 of 40
6 Select the Project Type. Click on the RTL Project radio button to select. Click on the Next button. Figure 6: New Project - Project Type Page 6 of 40
7 Add HDL Source Files. No HDL sources are required to be added at this stage. Click on the Next button. Figure 7: New Project - Add Sources Page 7 of 40
8 Add Existing IP. No Existing IP are required to be added at this stage. Click on the Next button. Figure 8: New Project - Add Existing IP (Optional) Page 8 of 40
9 Add Constraints. No constraints are required to be added at this stage. Click on the Next button. Figure 9: New Project - Add Constraints (Optional) Page 9 of 40
10 Select Development Board. Select MicroZed Board. Note: Ensure that Revision F is selected. Click on the Next button. Figure 10: New Project - Default Part Page 10 of 40
11 Project Summary. Click on the Finish button. Figure 11: New Project - New Project Summary Figure 12: Vivado (New Project) Page 11 of 40
12 5 Project Settings Tools -> Project Settings. Select General. Select Target language: -> VHDL Click on the OK button. Figure 13: Project Settings - General Page 12 of 40
13 6 Create Processor System 6.1 New Block Diagram Flow -> Create Block Diagram. Type Design name -> system. Click on the OK button. Click on the Add IP hyperlink. Click on the ZYNQ7 Processing System IP. Press Enter to add IP. Figure 14: Create Block Diagram Figure 15: ZYNQ7 Processing System IP Page 13 of 40
14 ZYNQ7 Processing System block diagram without connections. Figure 16: Vivado Add ZYNQ7 Processing System IP (Complete) Page 14 of 40
15 Make external connections. Click on the Run Block Automation hyperlink. Click on the OK button. Figure 17: Run Block Automation Page 15 of 40
16 Validate Design. Tools -> Validate Design Figure 18: Vivado ZYNQ7 Processing System IP (Run Block Automation Complete) Click on the OK button. Figure 19: Validate Design Page 16 of 40
17 6.2 Generate Output Products Click on the Sources tab in the Sources window and select system block diagram. Right click and select Generate Output Products. Click on the Generate button. Click on the OK button. Figure 20: Generate Output Products Figure 21: Generate Output Products (Complete) Page 17 of 40
18 6.3 HDL Wrapper Click on the Sources tab in the Sources window and select system block diagram. Right click and select Generate Output Products. Click on the Copy generated wrapper to allow user edits radio button to select. Click on the OK button. Click on the OK button. Figure 22: Create HDL Wrapper Figure 23: Create HDL Wrapper (Complete) Page 18 of 40
19 HDL Wrapper. Figure 24: Vivado - HDL Wrapper Page 19 of 40
20 7 Implement Design Flow -> Run Implementation Vivado lets the user know if any dependent sources are missing or out of date. Click on the OK button. Figure 25: Vivado Missing Synthesis Results Click on the Generate Bitstream radio button to select. Figure 26: Implementation Completed Click on the Open Implemented Design radio button to select. Click on the OK button. Figure 27: Bitstream Generation Completed Page 20 of 40
21 Take a few moment to explore the implemented design in the Device window. Figure 28: Vivado - Implemented Design Page 21 of 40
22 8 Export Hardware Export hardware to SDK. File -> Export Hardware Click on the Include bitstream check box to select. Click on the OK button. Figure 29: Export Hardware Page 22 of 40
23 9 Launch SDK File -> Launch SDK Click on the OK button. Figure 30: Launch SDK Figure 31: SDK Project Page 23 of 40
24 10 New Application Project 10.1 Hello File -> Application Project Type Project name -> hello. Click on the Next button. Figure 32: Hello Application Project Page 24 of 40
25 Select Hello World template. Click on the Finish button. Figure 33: Templates - Hello World Page 25 of 40
26 10.2 Bootloader File -> Application Project Type Project name -> zynq_fsbl. Click on the Next button. Figure 34: Bootloader Application Project Page 26 of 40
27 Select Zynq FSBL template. Click on the Finish button. Figure 35: Templates - Zynq FSBL Page 27 of 40
28 10.3 Bootloader debug flags Set Debug flags for zynq_fsbl. Select the zynq_fsbl application in the Project Explorer window, right click and select Properties. Select C/C++ Build -> Settings Select Tool Settings tab. Select ARM gcc compiler -> Debugging Type -DFSBL_DEBUG_INFO=1 for Other debugging flags. Figure 36: "zynq_fsbl" properties Page 28 of 40
29 11 Program FPGA Ensure that the Xilinx Platform Cable USB is connected to the target and the target is powered. The Xilinx Platform Cable USB LED should be green. Ensure that Devices -> USB Devices -> XILINX is selected. Xilinx Tools -> Program FPGA. Select Bitstream: -> system_wrapper.bit. Click on the Program button. Figure 37: Enable USB Figure 38: Program FPGA Ensure that the DONE LED D2 is turned off then on to signify successful configuration. The SDK Log will also indicate Programming Status. Ensure that Programming was successful. Page 29 of 40
30 12 Debug 12.1 Setup Ensure that the Xilinx Platform Cable USB is connected to the target and the target is powered. The Xilinx Platform Cable USB LED should be green. Ensure that Devices -> USB Devices -> XILINX is selected. Figure 39: Enable USB On the Windows 7 Host open HyperTerminal. Configure HyperTerminal with settings /8/n/1/n. Page 30 of 40
31 12.2 Configure Select hello in the Project Explorer window. Run -> Debug Configurations. Select Xilinx C/C++ application (GDB), right click and select New. Figure 40: Debug Configurations Page 31 of 40
32 Select hello Debug. Select the Target Setup tab. Set Initalization file: -> ps7_init.tcl Click on the Run ps7_init check box to select. Click on the Run ps7_post_config check box to select. Note: Run ps7_post_config sets the SLCR registers to enable level shifters, FPGA reset and AFI registers. AXI communication will fail if the SLCR registers are not configured. Figure 41: Debug Configurations - Target setup Page 32 of 40
33 Select the Application tab. Select Project Name -> hello by clicking on the Browse button. Select Application: -> Debug/hello.elf by clicking on the Search button. Click on the Close button. Figure 42: Debug Configurations - Application Page 33 of 40
34 12.3 Debug Application Select the hello application in the Project Explorer window. Click on the Perspective button. Figure 43: SDK Select Debug. Click on the OK button. Figure 44: Open Perspective Page 34 of 40
35 Run -> Debug Figure 45: Debug Debug Perspective Execution is halted at main. Use ctrl + double click and click on the OK button to add break point. Use right click for breakpoint control. Run -> Resume. Figure 46: Debug - Add breakpoint Page 35 of 40
36 Execution halts at breakpoint. Run -> Resume. Execution is complete. Figure 47: Debug - hello.elf stopped at breakpoint Figure 48: hello.elf execution complete Page 36 of 40
37 Terminate application. Run -> Terminate. Figure 49: Debug - Terminate Application Close SDK Figure 50: Exit SDK Ensure that HyperTerminal output displays Hello World Figure 51: HyperTerminal Page 37 of 40
38 13 Boot Image Select the hello application in the Project Explorer window, right click and select Create Boot Image. system_wrapper.bit and hello.elf are type datafile. zynq_fsbl.elf is type bootloader Click on the Create Image button. Figure 52: Create Zynq Boot Image Page 38 of 40
39 14 Booting from Micro SD card 14.1 Micro SD card preparation The Micro SD card must be formatted as FAT32. Copy BOOT.bin from $HOME/projects/basic_test/basic_test.sdk/hello/bootimage to /media/sf_vbox. $ cp /home/syfer/project/basic_test/basic_test.sdk/hello/bootimage/boot.bin /media/sf_vbox Figure 53: Copy BOOT.bin Copy I:\syfer\Vbox\BOOT.bin to the Micro SD card Set Avnet MicroZed Development Board Boot Mode Disconnect power from the Avnet MicroZed Development Board. Insert Micro SD card into Avnet MicroZed Development Board Micro SD card connector J6. Set the Avnet MicroZed Development Board Boot Mode to Micro SD. JP3=2,3 JP2=2,3 Jp1=1,2 Figure 54: Boot Mode Page 39 of 40
40 14.3 Configure HyperTerminal Connect USB cable to PC and Avnet MicroZed Development Board J2. On the Windows 7 Host open HyperTerminal. Configure HyperTerminal with settings /8/n/1/n. Figure 55: HyperTerminal 14.4 Reset Avnet MicroZed Development Press SW2 on the Avnet MicroZed Development Board to reset the PS. Figure 56: HyperTerminal Page 40 of 40
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