Synaptic Labs' HyperBus Memory Controller (HBMC) Tutorial
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1 Synaptic Labs' HyperBus Memory Controller (HBMC) Tutorial T001B: A Qsys based Nios II reference design with a simple Memory Bandwidth Benchmark of the HyperRAM device using S/Labs' HBMC IP This tutorial should be started after completing all the steps described in the tutorial titled: T001A: A Qsys based Nios II Reference design with a simple self test of the HyperFlash and HyperRAM device using S/Labs' HBMC IP This tutorial assumes that the FPGA board type field in the Master Configuration tab of the HyperBus Memory Controller IP has been set to: Devboards - HyperMAX 10M25 (HyperRAM), or Devboards - HyperMAX 10M50 (HyperRAM), or Intel Cyclone 10LP Evaluation Kit (HyperRAM) comp, Synaptic Labs 2017 info@synaptic-labs.com V3.0 page 1
2 1. Modify the memory initialization field(s) in Qsys This memory benchmarking project does not fit within the 40 KB on-chip SRAM. Therefore, we are going to remove the.hex file initialization file for the on-chip memory in the Qsys project: In Qsys, open the hypernios.qsys project. Open the parameters for the On-Chip Memory module. Untick the [ ] Enable non-default initialisation file field. Save and regenerate the Qsys design Close the Qsys window. Recompile the Quartus Prime project. Synaptic Labs 2017 info@synaptic-labs.com V3.0 page 2
3 2. Preparing the memory benchmarking firmware 2.1 Open the NIOS II Software Built Tools for Eclipse In Quartus Prime, go to the menu bar and select Tools NIOS II Software Built Tools for Eclipse. Click the [Browse ] button. A new file selector window will open. In this tutorial we are going to select the software folder located inside the project folder as the workspace and then click the [ OK ] button. Be sure to leave the [ ] Use this as the default field unticked. Click the [ OK ] button. Synaptic Labs 2017 info@synaptic-labs.com V3.0 page 3
4 2.2 Create a simple application and BSP The software folder in the reference project will have the HelloWorld application from the previous tutorial. We now want to create a new Nios II application, and Nios II board support package for the Nios II software HyperRAM bandwidth benchmarking application: In the Eclipse window, go the menu bar and select: File New NIOS II Application and BSP from Template A new window will pop up: (most of the fields below will initially be empty) Synaptic Labs 2017 info@synaptic-labs.com V3.0 page 4
5 In the Target hardware information, click on the [ ] button A file browser window will open. Locate and select the hypernios.sopcinfo file generated by Qsys and stored in the project directory. Click [Open]. It may take around 30 seconds for the Eclipse application to parse the.sopcinfo file. Select a Project name. In this example, we are using Benchmark as the project name. Ensure that: [x] Use default location is ticked. We now need to select a template from the Project Template list. In this example, select the Hello World template. Press the [ Finish ] button to complete the current step. The Nios II SBT will now generate: a Benchmark application folder that contains the hello_world.c file. We will replace that hello_world.c file with a custom program that tests the HyperRAM device later in this tutorial. a Benchmark_bsp folder that contains the Nios II Board Support Package (BSP) hardware abstraction layer (HAL) specifically for the Benchmark application. Synaptic Labs 2017 info@synaptic-labs.com V3.0 page 5
6 2.3 Configure the Board Support Package (BSP) The Nios II BSP must be configured before we can compile the source code. In the Project Explorer tab, right click on: Benchmark_bsp Nios II -> BSP Editor Synaptic Labs 2017 V3.0 page 6
7 In the Main Tab of the BSP editor, in the panel on the left hand side, select: Settings Common Set the sys_clk_timer field to timer_0 This is used to generate a recurring system clock interrupt for the hardware abstraction layer. Set the timestamp_timer field to interval_timer This field is used to enable the hardware abstraction layer to perform fine precision timing. The Newlib ANSI C standard library can be configured as small or normal: Tick the [x] Enable small C library field to reduce the size of the executable code generated by the hardware abstraction layer (HAL). Ticking this option also reduces the functionality and performance of the HAL. Please note that the inbuilt memset() and memcpy() routines will be very slow. Untick the [ ] Enable small C library field to increase the functionality and performance of the executable code generated by the hardware abstraction layer (HAL). The inbuilt memset() and memcpy() routines will achieve good performance. However, the executable code will be considerably larger. We recommend Untick the [ ] Enable small C library for this specific tutorial. Synaptic Labs 2017 info@synaptic-labs.com V3.0 page 7
8 In the Main Tab of the BSP editor, in the panel on the left hand side, select: Settings Advanced hal.linker For the purpose of this specific tutorial, please use the following configuration: Tick [x] allow_code_at_reset Tick [x] enable_alt_load Tick [x] enable_alt_load_copy_rodata Tick [x] enable_alt_load_copy_rwdata Tick [x] enable_alt_load_copy_exception UnTick [ ] enable_exception_stack However, this specific configuration may not always be the best configuration for your project s needs. Please refer to Altera s documentation for detailed information on how to setup the hal.linker fields: Generic Nios II Booting Methods User Guide, UG-20001, Synaptic Labs 2017 info@synaptic-labs.com V3.0 page 8
9 Select the Linker Script Tab of the BSP editor. For this tutorial example, we are going to: Map the reset vector (.reset) to the onchip memory (onchip_memory2_0). This is generated by Qsys and depends on the location of the Nios II reset vector. Map the exception vector (.exceptions) to the onchip memory (onchip_memory2_0). This is generated by Qsys and depends on the location of the Nios II exception vector. Map the instruction code (.text) in the HyperRAM (sll_hyperbus_controller_top_0) Map all other data regions (.bss,.heap,.rodata,.rwdata,.stack) to the HyperRAM memory (sll_hyperbus_controller_top_0) For more information about linker sections in general, please see: Nios II Gen2 Software Developer's Handbook, NII5V2Gen2, Section 5, Nios II Software Build Tools Now: Click on the [ Exit ] button on the bottom right hand corner of the BSP Editor window. Then click on the [Yes, Save] button on the Save Changes window to save the BSP settings. Synaptic Labs 2017 info@synaptic-labs.com V3.0 page 9
10 2.4 Generate the BSP and clean the project The software developer must re-generate the BSP every time the Qsys project is regenerated. This ensures that the device drivers and addresses of peripherals are reflected correctly in the hardware abstract library. To (re)generate the BSP: Go to the Nios II eclipse window. Right click on Benchmark_bsp project then select Nios II then select Generate BSP. Right click on the Benchmark_bsp project then select Clean Project to delete any intermediate files generated by the gcc compiler for this application library. Right click on the Benchmark project then select Clean Project to delete any intermediate files generated by the gcc compiler for this application folder. 2.5 Install the memory testing source code We now want to replace the original HelloWorld.c source code with software hat checks the HyperRAM. Copy and replace the files located in: to: HyperNios_Project/source/TestMbs HyperNios_Project/software/Benchmark In the project explorer window of Eclipse, right click on the Benchmark folder. Then select Refresh. The new source code files should now be visible within Eclipse. Synaptic Labs 2017 V3.0 page 10
11 Important If the FPGA board type field of the "Master Configuration" tab of the HBMC IP, is set to Devboards - HyperMAX 10M25/50 (HyperFlash and HyperRAM), then please // COMMENT out line 8 in the new hello_world.c file located in the Benchmark project. From a HyperRAM only configuration: To a HyperFlash and HyperRAM configuration: Synaptic Labs 2017 info@synaptic-labs.com V3.0 page 11
12 2.6 Build the Nios II Application We now want to run the compiler and linker: Go to the Nios II eclipse window. Right click on the Benchmark project, then select Build Project. If the project produces warning / error messages, you may need to build the project twice. The Benchmark executable firmware (.ELF) is now generated. The.ELF can now be downloaded directly into on-chip SRAM and off-chip SDRAM using the Nios II development environment. Synaptic Labs 2017 info@synaptic-labs.com V3.0 page 12
13 3. Program the FPGA Bitstream into the FPGA device Ensure that the HyperMAX/Intel C10LP evaluation board is connected to the USB port of your computer Open the Quartus Prime window In the menubar, click on Tools then Programmer to start the Altera Programmer If the HyperMAX/Intel C10LP Evaluation kit device is not already selected: Click on Hardware Setup. A new window will open. Double Click on the HyperMax (or Intel C10LP Evaluation kit) device, then click the [ Close ] button. If the NIOS_HyperRAM_time_limited.sof is not already selected: Click Add File... in the programmer window. Go to the output_files folder Double click on NIOS_HyperRAM_time_limited.sof Click the [ Start ] button and the FPGA bitstream will be programmed into the SRAM configuration memory of the FPGA device. A window called OpenCore Plus Status should open. Synaptic Labs 2017 info@synaptic-labs.com V3.0 page 13
14 4. Run the Benchmark from within Nios II SBT Select the Nios II Software Built Tools for Eclipse window. Right click on Benchmark Run As Run Configurations... Synaptic Labs 2017 V3.0 page 14
![A new window will open Make sure the Project name: field says Benchmark. Select the Target Configuration tab. Press the [Refresh Connection] button to detect the Nios II processor.](/docs-images/85/93033372/images/15-0.jpg "Tick the [Ignore mismatched System ID] field. Tick the [Ignore mismatched System timestamp] field.")
15 A new window will open Make sure the Project name: field says Benchmark. Select the Target Configuration tab. Press the [Refresh Connection] button to detect the Nios II processor. Tick the [Ignore mismatched System ID] field. Tick the [Ignore mismatched System timestamp] field. Press the [ Run ] button to download the firmware from the desktop and copy it directly into HyperRAM and then run the firmware from HyperRAM. If the download does not work, please check that the static timing constraints of your project are passing. Synaptic Labs 2017 info@synaptic-labs.com V3.0 page 15
16 Messages similar to the one below are displayed in the Nios II Console Window. Synaptic Labs 2017 V3.0 page 16
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