借助 SDSoC 快速開發複雜的嵌入式應用

Transcription

1 借助 SDSoC 快速開發複雜的嵌入式應用 May 2017

2 What Is C/C++ Development System-level Profiling SoC application-like programming Tools and IP for system-level profiling Specify C/C++ Functions for Acceleration Full System Optimizing Compiler Rapid system performance estimation by fast SW/HW partitioning and implementation ARM Code main() Connectivity Accelerator func() Full system optimizing compiler GCC Vivado Page 2

3 What Is C/C++ Development System-level Profiling 21 4 Days Days Specify C/C++ Functions for Acceleration Full System Optimizing Compiler ARM Code main() Connectivity Accelerator func() With SDSoC, I was able to complete a full Zynq design in 4 days Then, I did the same design without SDSoC and took me 3 weeks with the same QoR Daniele B, Xilinx DSP Specialist for EMEA GCC Vivado Page 3

4 Typical SoC Development Flow and Challenges APP(){ funca(); funcb(); funcc();} System Team Hard to know final system bottle neck during early system design funca HW-SW partition? HW-SW Connectivity? funcb, funcc Hardware Team Manually translating algorithms to HDL takes long time Manually implementing data mover network takes time Software Team funca Processing System (PS) Datamover PS-PL interfaces SW drivers funcb, funcc Programmable Logic (PL) Write drivers for register control interface Write and debug device driver of DMA Page 4

5 Before SDSoC: HW-SW Partition Exploration Met Req? C/C++ SDK Application C SDK, OS Tools PS Driver IPI project IP Integrator Datamover PS-PL interface PL HLS Verilog, VHDL Vivado IP HW-SW partition spec Involving multiple discipline to explore architecture Page 5

6 After SDSoC: Automatic System Generation Met Req? Application C/C++ PS Driver func1();<-sw func2();<-hw func3();<-hw Select functions for PL PL Datamover PS-PL interface IP C/C++ to System in hours, days Page 6

7 SDSoC: Makes Everyone More Productive System Team Explore HW-SW partitions and architecture rapidly in C/C++ Hardware Team No need to translate algorithms to HDL No need to implement data mover network Build IO system into a re-usable platform Software Team Now I can accelerate my code in HW No need to write device driver Page 7

8 Find Optimal Solution with Fast Iterations System Team One Click to toggle SW and HW implementation One line #pragma to change data port and data mover type func1();<-sw func2();<-sw C/C++ func3();<-sw func1();<-sw func2();<-hw C/C++ func3();<-hw func1();<-sw #pragma SDS func2();<-hw C/C++ func3();<-hw SW HW ACP, DMA 2 3 HP, SGDMA 2 3 Page 8

9 Look into Details by Event Trace Tool System Team Enable by one click during compile time Differentiate among SW, Data Mover and Accelerator IP Page 9

10 Automatic HW & SW Connection Software Team Hardware Team Auto generate register access device driver Auto generate data motion DMA driver Easy to integrate RTL based IP into SDSoC using C- callable IP Application PS Driver Datamover PS-PL interface PL HDL IP Page 10

11 Architecture-aware Algorithm Implementation Hardware Team Manual RTL translation is not required Algorithm and HW team work together to optimize IP Traditional Flow Algorithm spec in C/C++ Functional specification Translate to RTL Optimize RTL SDSoC Flow Algorithm spec in C/C++ Optimize C/C++ Optimize RTL Page 11

12 Easy to Create Base Platform for Custom Boards Software Team Hardware Team Platform = Vivado project + Bootable software images HW: define AXI interface and interrupt in Vivado project in tcl SW: define boot images (FSBL, kernel, rootfs, etc) in GUI tool Application Processing Systems (PS) Application Driver AXI Bus Driver Interface IPs Interface IPs Programmable Logic (PL) Platform Page 12

13 Easy to Create Base Platform Software Team Hardware Team Platform = Vivado project + Bootable software images SDSoC generated IP can hook to AXI in base platform Application Driver Generated Application Driver AXI Bus Application Driver Interface IPs Connectivity IP IP IP IP Interface IPs Platform Page 13

14 Examples and Use Cases Page 14

15 Computer Vision Design Example 4K60 Dense Optical Flow Xilinx ZU9 Frames/s 60 Power (W) 48 Latency (ms) 167 Utlization 15% main(){ imread(a); imread(b); denseopticalflowpyrltr(a,b,out); imshow(out);} ZCU102 EV Platform PS PL Application Libraries Linux AXI Drivers SDSoC Generated Platform DMA AXI-S MIPI denseoptical FlowPyrltr HDMI Benchmarks do not include the camera inputs and HDMI/DP LK dense optical flow, non-pyramidal, non-iterative, Window size 53x53 Page 15 DMA AXI-S

16 Computer Vision Design Example Stereo Disparity Map Xilinx ZU9 Frames/s 140 Power (W) 48 Latency (ms) 71 Utlization 14% main(){ imread(a); imread(b); stereorectify(a,b,c,d); stereolbm(c,d,out); imshow(out);} ZCU102 EV Platform PS PL USB3 Application Libraries Linux AXI Drivers SDSoC Generated Platform DMA AXI-S Stereo Rectify Stereo LBM HDMI SAD based stereo localbm Benchmarks do not include the camera inputs and HDMI/DP outputs Page 16

17 Use Case: Surveillance DDR3/4 4K60 CMOS Sensor LVDS ISP CNN (Face Detect) Overlay PS DP VCU H265 ENET DDR3/4 Zynq UltraScale Target Device ZU4EV or ZU5EV < 6W total power Linux based OS H264 HP, H265 encoder Page 17

18 Use Case: Machine Vision DDR3/4 4K60 CMOS Sensor LVDS ISP Feature Extract Color Inspect USB3 GTH PS GigE 1G Eth Coax GTH Zynq UltraScale DDR3/4 Target Device ZU2 or ZU3 Linux based OS Page 18

19 Use Case: Drone/UAV DDR3/4 2K60 CMOS Sensor MIPI Optical PS DP 2K60 CMOS Sensor MIPI CNN 4K60 CMOS Sensor MIPI Stereo Vision ADC 4K60 CMOS Sensor MIPI ISP VCU H265 Radio Zynq UltraScale DDR3/4 Target Device ZU4EV, ZU5EV or ZU7EV Linux based OS Page 19

20 Use Case: AR DDR3/4 Gyro/ Accer Position tracking PS DP 2K60 CMOS Sensor MIPI CNN (Eye tracking) WiFi 4K60 4K60 CMOS Sensor CMOS Sensor MIPI MIPI ISP Stereo Vision Gesture H265 VCU Zynq UltraScale DDR3/4 Target Device ZU4EV, ZU5EV or ZU7EV Linux based OS Page 20

21 Embedded Vision Development Kits Base Zynq Board ZCU102 ZCU106 ZC702 ZC706 Device ZU9 (16nm) ZU7 (16nm) Z7020 (28nm) Z7045 (28nm) CPU Quad Cortex A53 up to 15GHz Dual Cortex A9 up to 10GHz Peak INT On-chip RAM (Mbits) Inputs USB3, MIPI, HDMI USB3, MIPI, HDMI HDMI* HDMI* Outputs HDMI, DisplayPort HDMI, DisplayPort HDMI HDMI Video Codec Units No 4K60 Encode/Decode No No revision Support xfopencv, xfdnn xfopencv, xfdnn xfopencv, xfdnn xfopencv, xfdnn Sensor Inputs Sony IMX274 Quad OnSemi AR0231 StereoLab Zed Stereo econ camera Spec 60 FPS 30 FPS 30 FPS 60 FPS Interface MIPI via FMC MIPI via FMC USB3 USB3 * Requires an HDMI IO FMC card Page 21

22 SDSoC Enhancements Zynq Ultrascale+ MPSoC enhancements Full support to zcu102 platform, with additional clocks Increased high performance HP port data width to 128-bits Support for custom Zynq Ultrascale+ MPSoC platforms System compiler enhancements Support of packed structs and scalar widths up to 1024-bits (was 32-bits) Support for HLS dataflow and multi-buffered BRAM-mapped array arguments at the function top level Support for SG-DMA on MIG accessible DDR HW/SW event trace support for async hardware functions Page 22

23 Application Development DNN CNN GoogLeNet SSD FCN Algorithm Development Platform Development Page 23

24 Time on Platform Time on Apps Removing the Barrier to Broad Adoption ML Apps OpenCV Apps Ease of Use Algorithm to RTL System Integration Bitstream Generation Traditional RTL flow OpenCV Machine Learning Page 24

25 SDSoC Resources Access SDSoC Portal for learning materials Page 25

26 Documents SDSoC Basic Usage UG1028: SDSoC Tuturial UG1127: SDSoC Environment User Guide Video: SDSoC Development Environment Demo Custom Platform Creation UG1146: Platform Development Guide Video: SDSoC Custom Platform Generation C-Callable IP UG1127 Chapter 5 SDSoC Optimization Guide UG1235 Page 26

27 Conclusion: Faster Time-to-Market using SDSoC System Team Explore HW-SW partitions and architecture rapidly in C/C++ Hardware Team Build IO system into a re-usable platform for software team Help software team to optimize C code rather than translate C into RTL manually Software Team Focus on algorithm function and performance Page 27

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