Memory (1A) Young Won Lim 9/7/17

Transcription

1 (1A)

2 Copyright (c) Young W. Lim. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free Documentation License". Please send corrections (or suggestions) to youngwlim@hotmail.com. This document was produced by using OpenOffice.

3 Access Operations WR n-bit Data k-bit Address RD n-bit Data k-bit Address 3

4 A Write Example 2-bit address 4-bit data WR 4-bit Data 11 2-bit address 2-bit address bit data 11 WR Address: Data: 11 4

5 A Read Example 2-bit address 4-bit data RD 4-bit Data 2-bit address 10 RD Address: 10 Data: 5

6 A and A Map Write Data k-bit Address n-bit data k-bit Address Read Write Input n-bit Data Unit 2 k words n-bit per word Output n-bit Data Read Data 2 4 words

7 The Inputs and Outputs of a Input n-bit Data k-bit Address Read Unit 2 k words n-bit per word Write n-bit Data k-bit Address Output n-bit Data 7

8 Assignment and Write Operation 2-bit address bit data 11 WR 4-bit Data 11 2-bit address address data &a a int a; a = 7; WR Address: Data: 11 LHS (Left Hand Side) 8

9 Assignment and Read Operation 2-bit address 4-bit data RD 4-bit Data 2-bit address 10 address data &a a &b b int a; x = a + b; RD Address: 10 Data: RHS (Right Hand Side) 9

10 Tiny pcl pcinc intrs PC mmx 1 0 mal MAR Add/Sub mdil mdol mdo MDR mdi Z mem_w accl cla Acc irl IR Based on ISA (2A) 10

11 Tiny and mmx mal Data Bus 1 0 MAR mdil mdol mdo mem_w MDR mdi Tiny Address Bus Based on ISA (2A) 11

12 Write Cycle Input n-bit word k-bit address WR Mem_En RD/WR Unit 2 k words n-bit per word n-bit Data Bus k-bit Address Bus Synchronous WRITE Clock k-bit Output n-bit word n-bit 2 4 words Address WE Data Valid Address Valid Data ISA (2A) 12

13 Read Cycle Synchronous Input n-bit word k-bit address RD Mem_En RD/WR Unit 2 k words n-bit per word n-bit Data Bus k-bit Address Bus Synchronous READ Clock k-bit Output n-bit word n-bit 2 4 words Address WE Data Valid Address MEM Valid Data ISA (2A) 13

14 Write Cycle Example for a 4x4 WR Address: Data: 11 Data: 11 2-bit address 4-bit word I3 I2 I1 I0 4-bit Data Bus 2-bit address Bus 11 A0 A1 word0 word1 select select select select select select select select Clock Address Address: 2 x 4 decoder word2 select select select select Enable Initiating WR op Latch Data word3 select select select select Data 11 O3 O2 O1 O0 Data & Address Buses Output (RD) Data Bus Data: 11 Input (WR) ISA (2A) 14

15 Instruction Set Architecture 8-bit 8-bit OP code M: Operand Address ADD 0 M ADD $M ; ACC ACC + [M] STR 0 M STR $M ; [M] ACC CLA 1 CLA ; ACC 0 JNZ 1 M JNZ $M ; PC M if Z=0 RST 111 RST ; PC 0 Variable Length Based on ISA (2A) 15

16 Addr. Machine Codes CLA ;Clear Acc and then adding the operand is ADD $ONE ;equivalent to move the operand to Acc FF STR $FF 05 A0 JNZ $ 07 E0 RST 78 ONE: DAT ;Constant 1 00 FE FF FF A0 E0 FF 78 ISA (2A) 16

17 Array 17

18 References [1] Essential C, Nick Parlante [2] Efficient C Programming, Mark A. Weiss [3] C A Reference Manual, Samuel P. Harbison & Guy L. Steele Jr. [4] C Language Express, I. K. Chun