FPGA RAM (C1) Young Won Lim 5/13/16

Transcription

1 FPGA RAM (C)

2 Copyright (c) Young W. Lim. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version.2 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free Documentation License". Please send corrections (or suggestions) to youngwlim@hotmail.com. This document was produced by using LibreOffice and Octave.

3 Virtex LUT RAM module ram6x(q, a, d, we, clk); output q; input d; input [3:0] a; input clk, we; reg mem [5:0]; clk) begin if(we) mem[a] <= d; end assign q = mem[a]; Synchronous Write Asynchronous Read endmodule FPGA RAM (C) 3

4 LUT RAM Timing WRITE WRITE WRITE WRITE Xilinx Document FPGA RAM (C) 4

5 Virtex Block RAM Every block SelectRAM - synchronous write - syncrhronous read - dual-ported - independent control signals - independent data widths - independent A & B bit RAM A ENA RSTA >A A[#:0] A[#:0] B ENB RSTB >B B[#:0] B[#:0] DOA[#:0] DOB[#:0] FPGA RAM (C) 5

6 Virtex Block RAM Timing EN SSR WRITE Xilinx Document SSR (Synchronous Set Rest) value = 00 FPGA RAM (C) 6

7 Sync RD Cycle - worst & best case Timing Specification EN best case delay SSR WRITE worst case delay more realistic timing CPU Clock Synchronous Address CPU Valid Address WRITE Data Valid Data FPGA RAM (C) 7

8 Async RD Cycle - worst & best case Timing Specification EN best case delay SSR WRITE worst case delay more realistic timing CPU Clock Address Asynchronous CPU Valid Address WRITE Data Valid Data FPGA RAM (C) 8

9 WR Cycle worst & best case Timing Specification EN best case delay SSR WRITE worst case delay CPU more realistic timing Synchronous WRITE Clock WRITE Address Data CPU CPU Valid Address Valid Data FPGA RAM (C) 9

10 Waveform Viewer Timing () * timing figures without delay (Ideal case) RTL functional simulation * timing figures with delay Gate level simulation with SDF annotation FPGA RAM (C) 0

11 Waveform Viewer Timing (2) Sync WRITE Sync Reg Reg FSM MAR MDR _WR : _RD : timing figures without delay (Ideal case) Reg MAR Reg FSM MDR _WR : _RD : timing figures with delay unintended write cycle! _RD : One cycle ahead FPGA RAM (C)

12 Waveform Viewer Timing (3) Sync Async Reg FSM MAR _RD : _RD : timing figures without delay (Ideal case) Reg FSM MAR _RD : _RD : timing figures with delay unintended write cycle! _RD : One cycle ahead FPGA RAM (C) 2

13 LUT as a combination logic block Input -bit Data x y z F F 3-bit Address {x, y, z} Read Write Memory Unit 2 3 words -bit per word Sum of Product Output -bit Data F FPGA RAM (C) 3

14 LUT : Async Read Async CL _RD : LUT Data Write Address : Inputs Data : Outputs The outputs available in the same cycle where the inputs are applied Combinational Logic Block : A set of Boolean Functions {x, y, z} Memory Unit 2 3 words -bit per word F FPGA RAM (C) 4

15 References [] [2] [3] [4] [5] [6] [7] [8] Digital Systems, Hill, Peterson, 987 [9] [0]