The Quad-RDBE (RDBE-Q) International VLBI Technology Workshop

Transcription

1 The Quad-RDBE (RDBE-Q) International VLBI Technology Workshop MIT Haystack Observatory Russell McWhirter Chester Ruszczyk Arthur Neill Christoper Beaudoin Contributions from NRAO, CASPER, Others

2 Historical Perspective VLBI DBE using ibob (Interconnect Break-out Board) Xilinx Virtex-II Pro 2VP x18 multipliers Designed with CASPER tool set 2-bit threshold setting estimated from bit states 2 Gbps data rate

3 VLBI DBE using Roach (Reconfigurable Open Architecture Computing Hardware) PowerPC 440EPx Processor Xilinx Virtex-5 XC5VSX95T FPGA x18 multipliers RDBE-H Geodetic v1.4 (svn r ) RDBE-S Astro single channel (svn r ) NRAO DDC design

4 Haystack RDBE v1.4 Top Level Two 512 MHz IF bands split into 16 channels of 32 MHz 16 channels selected from 32 total channels, 2 Gbps data storage rate Geodetic select odd channels 1, 3, 5 from each IF / pol VHDL FIR-FFT polyphase filter bank, CASPER modules for 10 GbE Automated quantization thresholds Noise diode synchronous switching and power detection for Tsys op_casper2010_haystack_vlbi_russ_mcwhirter.pdf

5 Haystack RDBE v1.4.1 Testing Memo #093 Testing of RDBE PFBG version S.R. McWhirter

6 RDBE-Q Four 512 MHz IF bands Flexible 2 / 4 / 8 Gbps data storage rate VDIF output packets single N point complex FFT to compute two N point real FFT tuff/t0001/pt10.htm

7 FFT Separation fft channel format mux if if Mux fft with x and y real z=x+jy; Xk = (Zk + conj(zn-k))/2 Yk = -j(zk - conj(zn-k))/2 Xreal = real Zk + ZN-k Ximag = imag Zk - ZN-k Yreal = imag Zk + ZN-k Yimag = real ZN-k - Zk Zk = ZN-k =

8 RDBE-Q Device Utilization Summary Slice Registers critical resource (78%) DSP and memory resource remaining (55% and 27%) DSP 264 two IF 356 four IF (+14%)

9 RDBE-Q Simulation Rdbesim.m FIR1(255,1/32) 256 tap lowpass prototype filter with Hamming window h=exp(j*pi/16*(1:length(firq))); fvtool(firq,1,firq.*h,1) svn+ssh://vault/svnrepos/rdbe/fpga/trunk/ M-files/RoachGUI/rdbesim.m

10 RDBE-Q Testing./ram_load_4if.sh $h $p tvg_ram_data_4if/ramtones.txt 0 notburst > /dev/null setastro./setquant.sh $h $p /readbs.sh $h $p start=$(date --date now+10sec perl -ne 'if (/(..):(..):(..)/){print "$1:$2:$3"}') stop=$(date --date now+20sec perl -ne 'if (/(..):(..):(..)/){print "$1:$2:$3"}')./ntp_rdbes.sh $h $start $stop #statusa ssh shifu -t 'cd RoachGUI; sudo tcpdump -i eth3 -s 0 -c w ~/tmp/etha.pcap & sudo tcpdump -i eth5 -s 0 -c w ~/tmp/ethb.pcap ' scp shifu:~/tmp/etha.pcap shifu:~/tmp/ethb.pcap./tvg_ram_data_4if/

11 RDBE-Q Testing for ch=0:15; ramtones += 7*cos(2*pi*(ch*32+ch/2+.5)*1e6*n/1024e6); ramtones2 += 7*cos(2*pi*(ch*32+ch/2+1)*1e6*n/1024e6); end; Bpplotter.py

12 RDBE-Q Testing [invalid_a, legacy_a, sec_a, unass_a, refepoch_a, frame_a, ver_a, chns_a, len_a, cplx_a, bits_a, thread_a, station_a, edv_a, euda_a, eudb_a, psn_a, sync_a, dat_a, bstater_a, bstatei_a] = rd_vdif(file_a,frames); figure;for c=1:16;subplot(16,1,c);hold on;plot(ra(c,1:128),'r');plot(ia(c,1:128),'b');end svn+ssh://vault/svnrepos/rdbe/fpg A/trunk/M-files/RoachGUI/vdif_test.sh

13 RDBE Software Hardware Abstraction Layer (HAL) ICD to quad IF requires enhancement HAL updated to reflect the new ICD rdbe_server VSI-S interface to outside world Command set update for 2 output ethernet configuration Vdif data format User writable fields addition 4 IF configuration Time format is the same as supporting PFBG 1.4 YYYYDDDHHMMSS Conversion to respective data payload type performed in application Quantization command interface is the same Process to determine the quantization states Now performed in software Written back to FPGA

14 PCAL Personality Bill Petrachenko design RoachVLBI2010_pcal svn r svn+ssh://vault/svnrepos/rdbe/fpga/trunk/toplevel Builds/RoachVLBI2010_pcal

15 Automatic Level Control Designed by NRAO -10 to +22 db in 1 db increments Optional 20 db pad for solar mode Possible redesign for four IF inputs svn+ssh://vault/svnrepos/rdbe/doc/trunk/hardware/alc

16 Roach 2 with ADC1x Virtex-6 SX475T FPGA three times DSP resource Two Z-DOK+ 8-bit dual 2.5GSPS in two-channel mode CX4 or SFP+ mezzanine board for eight 10 GbE links