Integrated Silicon Pressure Sensor On-Chip Signal Conditioned, Temperature Compensated and Calibrated
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1 Freescale Semiconductor Technical Data Integrated Silicon Pressure Sensor On-Chip Signal Conditioned, Temperature Compensated and Calibrated The series piezoresistive transducers are state-of-the-art monolithic silicon pressure sensors designed for the appliance, consumer, healthcare and industrial market. The analog output can be read directly into the A/ D input of Freescale microcontrollers. This transducer combines advanced micromachining techniques, thin-film metallization, and bipolar processing to provide an accurate, high level analog output signal that is proportional to the applied pressure. The axial port has been modified to accommodate industrial grade tubing. Features 1.5% Maximum Error for 0 to 100 mm H 2 O over +10 to +60 C with Auto Zero 2.5% Maximum Error for 100 to 400 mm H 2 O over +10 to +60 C with Auto Zero 6.25% Maximum Error for 0 to 400 mm H 2 O over +10 to +60 C without Auto Zero Temperature Compensated over +10 to +60 C Available in Surface Mount (SMT) or Through-hole (DIP) Configurations Application Examples Washing Machine Water Level Measurement (Reference AN1950) Ideally Suited for Microprocessor or Microcontroller-Based Systems Appliance Liquid Level and Pressure Measurement Respiratory Equipment SERIES INTEGRATED PRESSURE SENSOR 0 to 3.92 kpa (0 to 400 mm H 2 O) 1.0 to 4.9 V OUTPUT Rev 1, 01/2006 SURFACE MOUNT W6U CASE U/T1 CASE THROUGH-HOLE ORDERING INFORMATION Device Type Case No. MPVZ Series Order No. Packing Options Device Marking J Surface Mount W6U Rails MZ5004GW Through-Hole W7U Rails MZ5004GW Surface Mount U Rails MZ5004G Surface Mount T1 Tape & Reel MZ5004G Through-Hole 482B-03 7U Rails MZ5004G W7U CASE PIN NUMBERS (1) 7U CASE 482B-03 1 N/C 5 N/C 2 V S 6 N/C 3 GND 7 N/C 4 V OUT 8 N/C 1. Pins 1, 5, 6, 7, and 8 are internal device connections. Do not connect to external circuitry or ground. Pin 1 is noted by the notch in the lead. Freescale Semiconductor, Inc., All rights reserved.
2 V S Sensing Element Thin Film Temperature Compensation and Calibration Circuitry Gain Stage #2 and Ground Reference Shift Circuitry V OUT Table 1. Maximum Ratings (1) GND Pins 1, 5, 6, 7, and 8 are NO CONNECTS for small outline package device. Figure 1. Fully Integrated Pressure Sensor Schematic Rating Symbol Value Unit Maximum Pressure (P1 > P2) P MAX 16 kpa Storage Temperature T STG 30 to +100 C Operating Temperature T A 0 to +85 C 1. Exposure beyond the specified limits may cause permanent damage or degradation to the device. Table 2. Operating Characteristics (V S = 5.0 V DC, T A = 25 C unless otherwise noted, P1 > P2) Characteristic Symbol Min Typ Max Units Pressure Range P OP Supply Voltage (1) 1. Device is ratiometric within this specified excitation range. kpa mm H 2 O V S V DC Supply Current I S 10 madc Full Scale Span V S = 5.0 Volts V FSS 4.0 V (3) (4) Offset V OFF V Sensitivity V/P Accuracy (4) (5) 0 to 100 mm H 2 O (10 to 60 C) 100 to 400 mm H 2 O (10 to 60 C) 0 to 400 mm H 2 O (10 to 60 C) V/kPa mv/mm H 2 O ±1.5 %V FSS with auto zero ±2.5 %V FSS with auto zero ±6.25 %V FSS without auto zero 2. Span is defined as the algebraic difference between the output voltage at specified pressure and the output voltage at the minimum rated pressure. 3. Offset (V off ) is defined as the output voltage at the minimum rated pressure. 4. Accuracy (error budget) consists of the following: Linearity: Output deviation from a straight line relationship with pressure over the specified pressure range. Temperature Hysteresis: Output deviation at any temperature within the operating temperature range, after the temperature is cycled to and from the minimum or maximum operating temperature points, with zero differential pressure applied. Pressure Hysteresis: Output deviation at any pressure within the specified range, when this pressure is cycled to and from the minimum or maximum rated pressure, at 25 C. Offset Stability: Output deviation, after 1000 temperature cycles, -30 to 100 C, and 1.5 million pressure cycles, with minimum rated pressure applied. TcSpan: Output deviation over the temperature range of 10 to 60 C, relative to 25 C. TcOffset: Output deviation with minimum rated pressure applied, over the temperature range of 10 to 60 C, relative to 25 C. Variation from Nominal: The variation from nominal values, for Offset or Full Scale Span, as a percent of V FSS, at 25 C. 5. Auto Zero at Factory Installation: Due to the sensitivity of the, external mechanical stresses and mounting position can affect the zero pressure output reading. Autozeroing is defined as storing the zero pressure output reading and subtracting this from the device's output during normal operations. Reference AN1636 for specific information. The specified accuracy assumes a maximum temperature change of ± 5 C between autozero and measurement. 2 Freescale Semiconductor
3 ON-CHIP TEMPERATURE COMPENSATION, CALIBRATION AND SIGNAL CONDITIONING The performance over temperature is achieved by qualification test for dry air, and other media, are available integrating the shear-stress strain gauge, temperature from the factory. Contact the factory for information regarding compensation, calibration and signal conditioning circuitry media tolerance in your application. onto a single monolithic chip. Figure 3 shows the recommended decoupling circuit for Figure 2 illustrates the Differential or Gauge configuration interfacing the output of the to the A/D input of in the basic chip carrier (Case 482). A gel die coat isolates the the microprocessor or microcontroller. Proper decoupling of die surface and wire bonds from the environment, while the power supply is recommended. allowing the pressure signal to be transmitted to the silicon Figure 4 and Figure 5 shows the sensor output signal diaphragm. relative to pressure input. Typical, minimum and maximum The series sensor operating characteristics output curves are shown for operation over a temperature are based on use of dry air as pressure media. Media, other range of 10 C to 60 C using the decoupling circuit shown in than dry air, may have adverse effects on sensor Figure 3 The output will saturate outside of the specified performance and long-term reliability. Internal reliability and pressure range. Wire Bond Fluorosilicone Gel Die Coat P1 Die Stainless Steel Cap Thermoplastic Case +5 V V out OUTPUT V s Lead Frame IPS 1.0 µf 0.01 µf GND 470 pf Differential Sensing Element P2 Die Bond Figure 2. Cross-Sectional Diagram (Not to Scale) Figure 3. Recommended Power Supply Decoupling and Output Filtering. (For additional output filtering, please refer to Application Note AN1646.) TRANSFER FUNCTION: V out = V S *[(0.2*P) + 0.2] ± 6.25% V FSS V S = 5.0 Vdc TEMP = 10 to 60 C TRANSFER FUNCTION: V out = V S *[(0.2*P) + 0.2] ± 2.5% V FSS V S = 5.0 Vdc TEMP = 10 to 60 C Output (V) MAX MIN TYPICAL Output (V) MAX MIN TYPICAL Differential Pressure (kpa) Figure 4. Output versus Pressure Differential at ±6.25% V FSS (without auto zero, note 5 in Operating Characteristics) Differential Pressure (kpa) Figure 5. Output versus Pressure Differential at ±2.5% V FSS (with auto zero, note 5 in Operating Characteristics) Freescale Semiconductor 3
4 PRESSURE (P1)/VACUUM (P2) SIDE IDENTIFICATION TABLE Freescale Semiconductor designates the two sides of the pressure sensor as the Pressure (P1) side and the Vacuum (P2) side. The Pressure (P1) side is the side containing a gel die coat which isolates the die from the environment. The Freescale Semiconductor pressure sensor is designed to operate with positive differential pressure applied, P1 > P2. The Pressure (P1) side may be identified by using the table below. Part Number Case Type Pressure (P1) Side Identifier W6U Vertical Port Attached W7U Vertical Port Attached 6U/T Stainless Steel Cap 7U 482B-03 Stainless Steel Cap INFORMATION FOR USING THE (CASE 482) MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the surface mount packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct footprint, the packages will self align when subjected to a solder reflow process. It is always recommended to design boards with a solder mask layer to avoid bridging and shorting between solder pads TYP 8X TYP 8X TYP 8X 2.54 inch mm SCALE 2:1 Figure 6. SOP Footprint (Case 482) 4 Freescale Semiconductor
5 PAGE 1 OF 3 CASE ISSUE A Freescale Semiconductor 5
6 PAGE 2 OF 3 CASE ISSUE A 6 Freescale Semiconductor
7 PAGE 3 OF 3 CASE ISSUE A Freescale Semiconductor 7
8 PAGE 1 OF 3 CASE ISSUE C 8 Freescale Semiconductor
9 PAGE 2 OF 3 CASE ISSUE C Freescale Semiconductor 9
10 PAGE 3 OF 3 CASE ISSUE C 10 Freescale Semiconductor
11 -A- -B G D 8 PL 0.25 (0.010) M T B S A S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, CONTROLLING DIMENSION: INCH. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006). 5. ALL VERTICAL SURFACES 5 TYPICAL DRAFT. J K S N M C PIN 1 IDENTIFIER H -T- SEATING PLANE INCHES MILLIMETERS DIM MIN MAX MIN MAX A B C D G BSC 2.54 BSC H J K M N S CASE ISSUE O -A- -B- 5 8 J -T- S N 4 1 G C M DETAIL X PIN 1 IDENTIFIER D 8 PL S 0.25 (0.010) M T B A S DETAIL X K SEATING PLANE NOTES: DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, CONTROLLING DIMENSION: INCH. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. MAXIMUM MOLD PROTRUSION 0.15 (0.006). ALL VERTICAL SURFACES 5 TYPICAL DRAFT. DIMENSION S TO CENTER OF LEAD WHEN FORMED PARALLEL. DIM A B C D G J K M N S INCHES MILLIMETERS MIN MAX MIN MAX BSC 2.54 BSC CASE 482B-03 ISSUE B Freescale Semiconductor 11
12 How to Reach Us: Home Page: USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH N. Alma School Road Chandler, Arizona or Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen Muenchen, Germany (English) (English) (German) (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo Japan or support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado or Fax: LDCForFreescaleSemiconductor@hibbertgroup.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals, must be validated for each customer application by customer s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc All rights reserved. Rev. 1 01/2006
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