DK-DEV-GW2AR18. User Guide

Transcription

1 DK-DEV-GW2AR18 User Guide DBUG E,03/02/2018

2 Copyright 2018 Guangdong Gowin Semiconductor Corporation. All Rights Reserved. No part of this document may be reproduced or transmitted in any form or by any means, electronic, mechanical, photo-copying, recording or otherwise, without the prior written consent of GOWINSEMI. Disclaimer GOWINSEMI, LittleBee, Arora TM, and the GOWINSEMI logos are trademarks of GOWINSEMI and registered in China, the U.S. Patent and Trademark Office and other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at GOWINSEMI assumes no liability, provides no warranty either expressed or implied relating to the usage, or intellectual property right infringement except as provided for by GOWINSEMI Terms and Conditions of Sale. All information in this document should be treated as preliminary. GOWINSEMI may make changes to this document without notice. Anyone relying on this documentation shall contact GOWINSEMI for the current documentation and errata.

3 Revision History Date Version Description 01/23/ E Initial version. 03/02/ E Modify contents of JTAG Download Circuit.

4 Contents Contents Contents... i List of Figures... iv List of Tables... v 1 About This Guide Purpose Supported Products Related Documents Abbreviation and Terminology Support and Feedback Development Board Description Overview Diagram Feature Specification Development Board Circuit Hardware Circuit Overview FPGA FPGA Introduction I/O Introduction Download Overview JTAG Download Port USB Download Circuit MSPI download DBUG E i

5 Contents Pin Location Power Supply Overview Circuit Ethernet interface Overview Circuit Pin Distribution Clock Overview Circuit Pin Distribution Reset Overview Circuit Pin Distribution LED Introduction Circuit Pin Distribution Slide switch Overview Circuit Pin Distribution Key Switch Overview Circuit Pin Distribution GPIO Overview DBUG E ii

6 Contents Circuit Pin Distribution Notes Gowin Software User Guide DBUG E iii

7 List of Figures List of Figures Figure 2-1 Development Board View... 5 Figure 3-1 Development Board Hardware Diagram... 9 Figure 3-2 FPGA I/O Pins Figure 3-3 JTAG Download Circuit Figure 3-4 USB Download Circuit Figure 3-5 External Flash Circuit Figure 3-6 Power Circuit Figure 3-7 Ethernet Circuit Figure 3-8 Clock Circuit Figure 3-9 Reset Circuit Figure 3-10 LED Circuit Figure 3-11 Slide Switch Circuit Figure 3-12 Key Switch Circuit Figure 3-13 GPIO Circuit DBUG E iv

8 List of Tables List of Tables Table 1-1 Abbreviations and Terminologies... 2 Table 2-1 GW2AR Series FPGA Product Information List... 4 Table 2-2 Development Board Specification... 6 Figure 3-1 FPGA I/O Pins Distribution Table 3-2 Download FPGA Pin Location Table 3-3 Ethernet FPGA Pins Distribution Table 3-4 Clock FPGA Pins Distribution Table 3-5 Reset Signal FPGA Pins Distribution Table 3-6 LED FPGA Pins Distribution Table 3-7 Slide Switch FPGA Pins Distribution Table 3-8 Key Switch FPGA Pins Distribution Table 3-9 J14 FPGA Pins Distribution Table 3-10 J15 FPGA Pins Distribution DBUG E v

9 1About This Guide 1.1Purpose 1About This Guide 1.1 Purpose DK-DEV-GW2AR18 development board (hereinafter referred to as Development Board) user manual includes the following four parts: 1. Briefly introduce the features and hardware resources of development board; 2. Introduce hardware circuits functions, circuit, and pins distribution; 3. Precautions for using development board; 4. Operation of Gowin software. 1.2 Supported Products The information in the guide applies to the following products: GW2AR-18 products. 1.3 Related Documents The latest user guides are available on our Website. Refer to the related documents via 1. GW2AR series FPGA Products Data Sheet 2. GW2AR-18 Pinout 3. GW2AR series FPGA Products Package and Pinout DBUG E 1(34)

10 1About This Guide 1.4Abbreviation and Terminology 1.4 Abbreviation and Terminology The abbreviations and terminologies used in this manual are as shown in Table 1-1 below. Table 1-1 Abbreviations and Terminologies Abbreviations and Terminology FPGA Full Name Field Programmable Gate Array Meaning Field Programmable Gate Array LED Light Emitting Diode Light Emitting Diode LDO Low Dropout Regulator Low Dropout Regulator GPIO General Purpose Input Output General Purpose Input Output LUT4 4-input Look-up Tables 4-input Look-up Tables S-SRAM Shadow SRAM Shadow SRAM B-SRAM Block SRAM Block SRAM PLL Phase-locked Loop PLL DLL Delay-locked Loop DLL DSP 1.5 Support and Feedback Digital Signal Processing Digital Signal Processing Gowin Semiconductor provides customers with comprehensive technical support. If any questions, comments, or suggestions, please feel free to contact us directly. Website: Tel: DBUG E 2(34)

11 2Development Board Description 2.1Overview 2Development Board Description 2.1 Overview The development board uses GW2AR series FPGA GW2AR-18 products, which is the first generation products of Gowin Arora family. GW2AR-18 series FPGA products are one kind of SIP chip. Compared with GW2A series, the difference is that GW2AR series integrates 64Mbit SDRAM. GW2A series also provides high-performance DSP resources, high-speed LVDS interface, and abundant BSRAM memory resources. These embedded resources with a streamlined FPGA architecture and 55nm process make GW2AR series FPGA products suitable for high-speed and low-cost applications, which can help users quickly design and develop the programmable logic products. Integrated with two Ethernet interfaces, the development board provides a hardware development and test platform for LED users with abundant GPIO resource. Besides that, the development board also offers slide switch, key switch, clock, and GPIO, which can be used by developers or hobbyists. Refer to GW2AR-18 Pinout Manual and GW2AR Series FPGA Product Package and Pinout for GW2AR-18 FPGA products packaging. Please refer to GW2AR series FPGA Product Data Sheet for GW2AR series FPGA product resources. DBUG E 3(34)

12 2Development Board Description 2.1Overview Table 2-1 GW2AR Series FPGA Product Information List Device GW2AR-18 LUT4 20,736 Flip-Flop (FF) 15,552 Shadow SRAM S-SRAM(bits) 41,472 Block SRAM B-SRAM(bits) 828K B-SRAM Quantity B-SRAM 46 SDRAM (bits) 64M 18 x 18 Multiplier 48 PLLs + DLLs 4+4 Total Number of I/O Bank 8 Max. User I/O 117 Core voltage 1.0V DBUG E 4(34)

13 2Development Board Description 2.2Diagram 2.2 Diagram Figure 2-1 Development Board View JTAG Download Port 3 50MHz Crystal Oscillator 5 GPIO 7 Power switch 9 LDO Power Circuit 11 Serial Flash 2 USB Download Port 4 Ethernet interface 6 DC5V Power Input 8 Slide switch 10 FPGA 12 Key Switch 2.3 Feature The structure and features of the development board are as follows: 1. FPGA - LQFP144 package - Up to 117 user I/O - 55nm SRAM technology - Support 1.0V core voltage DBUG E 5(34)

14 2Development Board Description 2.4Specification 2.4 Specification - Clock dynamically turning on/ turning off - Integrate SDRAM system in package chip - Multiple I/O Standards - Flexible PLLs+DLLs - High Performance DSP - Abundant LUT4 resources - Multiple modes and capacities of B-SRAM 2. FPGA Configuration Mode: JTAG, MSPI 3. USB-JTAG module circuit on board, can be used as a download cable 4. Communication interface: 2 Gigabit Ethernet Interfaces 5. Clock resource: 50MHz Clock Crystal Oscillator 6. Key switch and Slide switch - 1 reset button - 1 key switch - 2 slide switch 7. LED - 1 power indicator (green) - 1 DONE indicator (green) - 4 LEDs (green) 8. Memory device: 64Mbit SPI Flash 9. GPIO: 80 I/O Resources 10. LDO power - Inverse voltage protection, overcurrent protection - Electrical converter: 5 V V, 3.3 V -1.0V Table 2-2 Development Board Specification No. Item Functions Technical Conditions Remarks 1 FPGA Core chip, used for RTL code design 2 Download Support USB port and USB download mode: Switch DBUG E 6(34)

15 2Development Board Description 2.4Specification No. Item Functions Technical Conditions Remarks JTAG interface USB-JTAG module on board between download JTAG download: use PL- two modes Support JTAG, MSPI programming modes USB-CABLE to download, with an interface voltage of 3.3 V using jumper Input power: 5V Provide power for FPGA, 3 download circuit and other Provide DC 5V input; 3.3 V Power circuits via 5V 3.3 V circuit and 1.0V output via LDO Supply Provide power to FPGA core circuit via 3.3 V 1.0V circuit Output precision of 3.3 V and 1.0 V: ± 2%. 4 Ethernet interfaces support 10/100/1000 modes Ethernet Ethernet data RJ45 connector with built-in interface communication transformer 2 Ethernet data Channels 5 Slide switch Available for testing 2 6 Key Switch Connect to RECONFIG_N pin reset Provide reset signal for button FPGA/PHY 1 8 LED Mode indicator, DONE indicator, Power indicator User status Indicators, green 1 DONE indicator, green 1 Power indicator, green Crystal 9 Oscillator User 10 extension GPIO 11 Protection Provide 50MHz clock for FPGA I / O, used for testing LED display USB interface: ESD protection; Power interface: Inverse current and over current protection Crystal Oscillator Package GPIOs 5V USB interface ESD protection: ±15kV non-contact discharge, ± 8kV contact discharge Schottky diode is connected between positive and negative anodes of power outlet 2A self-recovery fuses is connected at power inlet DBUG E 7(34)

16 2Development Board Description 2.4Specification No. Item Functions Technical Conditions Remarks 12 Voltage 2.7V~5.5V 13 Humidity 95% 13 Temperature Operating range: 20 ~70 DBUG E 8(34)

17 3.1Hardware Circuit Overview 3Development Board Circuit 3.1 Hardware Circuit Overview Hardware circuit of development board mainly includes FPGA circuit, power, download circuit, clock circuit, GPIO circuit, LED, slide switch, button switch, and reset circuit, etc. Figure 3-1 Development Board Hardware Diagram DC 5V Input DC5V Input Protec tion Circuit Power LED INdica tor 4 LEDs User Extension GPIO USB Inter face LDO Power DC3.3V LDO Power DC1.0V 74HC245 2 Dip Switches USB Differenti al Signal ESD Circuit USB Download JTAG Download Select USB/ JTAG Download LED Indicator JTAG SIgnal GW2AR-18 (FPGA) SPI Flash 50MHz Active Cryst al Oscillator 1 Key Switch 1 Reset Key 74HC245 Ethernet Circuit 1 Ethernet Circuit 2 GPIO Interface DBUG E 9(34)

18 3.2FPGA 3.2 FPGA FPGA Introduction GW2AR series FPGA products are the first generation of Arora family products, and they are one kind of SIP chip. Compared with GW2A series, the difference is that GW2AR series integrates abundant SDRAM. GW2AR series also provides high-performance DSP resources, high-speed LVDS interface, and abundant BSRAM memory resources. These embedded resources with a streamlined FPGA architecture and 55nm process make GW2AR series FPGA products suitable for high-speed and low-cost applications. Features of GW2AR-18 series FPGA products are as follows: LQFP144 package Up to 117 user I/O 55nm SRAM technology Support 1.0V core voltage Clock dynamically turning on/ turning off Integrate SDRAM system in package chip Multiple I/O Standards Flexible PLLs+DLLs High Performance DSP Abundant LUT4 resources Multiple modes and capacities of B-SRAM See GW2AR series FPGA Products Data Sheet for more details. DBUG E 10(34)

19 3.2FPGA I/O Introduction Figure 3-2 FPGA I/O Pins IO Bank0 IO Bank1 IO Bank7 IO Bank6 GW2AR-18 IO Bank2 IO Bank3 IO Bank5 IO Bank4 Figure 3-1 FPGA I/O Pins Distribution I/O BANK Introduction I/O Bank Number I/O BANK0 3.3V I/O BANK1 3.3V I/O BANK2 3.3V I/O BANK3 3.3V Modules Connected Pins used for download mode selection GPIO Interface Slide switch LED Key Switch Reset Circuit MSPI download GPIO Interface GPIO Interface Ethernet interface GPIO Interface JTAG download 50MHz clock input DONE DBUG E 11(34)

20 3.3Download 3.3 Download Overview Development board provides USB download and JTAG download interfaces. Switch between interfaces using jumper. Data stream file can be downloaded to internal SRAM, or external Flash as needed. When downloaded to SRAM, the data stream file will be lost if device is power down, and the data stream file will need to be downloaded again after power-on. If downloaded to Flash, the data stream file will not be lost. Note! JTAG download: connect pin 1 of J3, J4, J5, J6 to pin 2 using jumper; USB download: connect pin 3 of J3, J4, J5, J6 to pin 2 using jumper; MSPI: a) Set MODE [1:0] pin to 011, download configuration data to the internal Flash device via JTAG interface; b) Set MODE pin to "000", power up again and the device will read bitstream from external Flash automatically to complete configuration. DBUG E 12(34)

21 3.3Download JTAG Download Port Figure 3-3 JTAG Download Circuit DBUG E 13(34)

22 3.3Download USB Download Circuit Figure 3-4 USB Download Circuit DBUG E 14(34)

23 3.3Download DBUG E 15(34)

24 3.4Power Supply MSPI download Figure 3-5 External Flash Circuit Pin Location Table 3-2 Download FPGA Pin Location FPGA Pin No. 3.4 Power Supply Overview Signal Name I/O BANK Description 13 TMS I 3 JTAG Signal 14 TCK I 3 16 TDI I 3 18 TDO O 3 93 MSPI_CK O 1 MSPI Signal 94 MSPI_CS O 1 95 MSPI_DI O 1 96 MSPI_DO I 1 DC5V Input power interface has overcurrent and inverse current protection. Overcurrent limit is 2A. TI LDO power supply chip is used to step down voltage from 5V to 3.3V and 3.3V to 1.0V; power supply can support up to 1.5 A. Input voltage range is 2.7 V to 5.5 V, which can meet the power demand of development board. DBUG E 16(34)

25 3.4Power Supply Circuit Figure 3-6 Power Circuit DBUG E 17(34)

26 3.4Power Supply DBUG E 18(34)

27 3.5Ethernet interface 3.5 Ethernet interface Overview Circuit Development board has 2 Ethernet circuits and supports gigabit mode, which can be used to test hardware environment in LED display applications, and Ethernet data transmission. Interface connected with other devices is RJ45 with built-in transformer. Figure 3-7 Ethernet Circuit DBUG E 19(34)

28 3.5Ethernet interface Pin Distribution Table 3-3 Ethernet FPGA Pins Distribution FPGA Signal Name I/O BANK Description Pin No. 45 PHY_MDC O 2 Management channel clock 46 PHY_MDIO I/O 2 Manage channel data 47 PHY2_GTCLK O 2 TXCLK 48 PHY2_TXD0 O 2 TXD[3:0] 49 PHY2_TXD1 O 2 50 PHY2_TXD2 O 2 51 PHY2_TXD3 O 2 52 PHY2_TXEN O 2 Send enable 54 PHY2_RXC I 2 Clock receive 56 PHY2_RXD0 I 2 RXD[3:0] 57 PHY2_RXD1 I 2 58 PHY2_RXD2 I 2 59 PHY2_RXD3 I 2 60 PHY2_RX_DV I 2 RXEN 61 PHY1_GTCLK O 2 TXCLK 62 PHY1_TXD0 O 2 TXD[3:0] 63 PHY1_TXD1 O 2 64 PHY1_TXD2 O 2 65 PHY1_TXD3 O 2 66 PHY1_TXEN O 2 Send enable 67 PHY1_RXC I 2 Clock receive 68 PHY1_RXD0 I 2 RXD[3:0] 69 PHY1_RXD1 I 2 70 PHY1_RXD2 I 2 71 PHY1_RXD3 I 2 72 PHY1_RX_DV I 2 RXEN DBUG E 20(34)

29 3.6Clock 3.6 Clock Overview Circuit A 50MHz external clock provided for FPGA in development board connects to PLL input pin, which can be used as input clock of PLL in FPGA, and output clock as needed via PLL frequency multiplication and division. Figure 3-8 Clock Circuit Pin Distribution Table 3-4 Clock FPGA Pins Distribution FPGA Signal Name I/O BANK Description Pin No. 6 FPGA_CLK I 3 50MHz crystal oscillator DBUG E 21(34)

30 3.7Reset 3.7 Reset Overview Circuit A reset circuit is added for better running FPGA program. After power on, reset chip automatically generates reset signal to reset FPGA and Ethernet PHY chip. In addition, FPGA program can be reset manually using reset button for program test. Figure 3-9 Reset Circuit Pin Distribution Table 3-5 Reset Signal FPGA Pins Distribution FPGA Signal Name I/O BANK Description Pin No. 79 RST_N I 1 Reset DBUG E 22(34)

31 3.8LED 3.8 LED Introduction Circuit 4 green LED lights in development board are used to display the required status. Meanwhile, 2 LED lights are reserved to observe power supply and FPGA loading status. If output signal of related pins is logic high, LED is on; if logic low, LED is off. Figure 3-10 LED Circuit DBUG E 23(34)

32 3.9Slide switch Pin Distribution Table 3-6 LED FPGA Pins Distribution FPGA Signal Name I/O BANK Description Pin No F_R22 F_G22 O O 0 0 GPIO outputs numbers, LED indicator pins and GPIO pins are reused. If GPIO function is used, LED indicator is invalid. 128 F_B22 O F_R23 O Slide switch Overview Circuit 2 Slide switches in development board are used to control input during testing. Figure 3-11 Slide Switch Circuit DBUG E 24(34)

33 3.10Key Switch Pin Distribution Table 3-7 Slide Switch FPGA Pins Distribution FPGA Pin No. Signal Name I/O BANK Description F_B23 F_G23 I I 0 0 GPIO outputs numbers, slide switch pins and GPIO pins are reused. If GPIO function is used, slide switch is grounded Key Switch Overview Circuit One key switch is installed in development board, you can manually reset FPGA or input the control signal used for testing. Figure 3-12 Key Switch Circuit DBUG E 25(34)

34 3.11GPIO Pin Distribution Table 3-8 Key Switch FPGA Pins Distribution FPGA Pin No. Signal Name I/O BANK Description 82 F_OE_1 I 1 GPIO outputs numbers, key switch pins and GPIO pins are reused GPIO Overview Circuit Two 20P double-column pins are reserved on development board for testing LED. The output level is 5V. Figure 3-13 GPIO Circuit DBUG E 26(34)

35 3.11GPIO DBUG E 27(34)

36 3.11GPIO DBUG E 28(34)

37 3.11GPIO Pin Distribution Table 3-9 J14 FPGA Pins Distribution FPGA 50P Double Signal I/O BANK Remarks Pin No. Row Pin No. Name 1 GND Output 5V 2 VCC5 O power supply; 3 GND Recommended 4 VCC5 O current output 5 GND 1A 6 VCC5 O 7 GND 8 VCC5 O 9 GND 10 VCC5 O H_G11 O 0 Customized H_B11 O 0 signal H_B10 O H_R11 O H_R10 O H_G10 O H_G9 O H_B9 O H_B8 O H_R9 O H_R8 O H_G8 O H_G7 O H_B7 O H_B6 O H_R7 O H_R6 O H_G6 O H_G5 O H_B5 O H_B4 O H_R5 O H_R4 O H_G4 O H_G3 O H_B3 O H_B2 O 3 DBUG E 29(34)

38 3.11GPIO FPGA 50P Double Signal I/O BANK Remarks Pin No. Row Pin No. Name H_R3 O H_R2 O H_G2 O H_G1 O H_B1 O H_D_1 O H_R1 O H_B_1 O H_C_1 O H_LAT_1 O H_A_1 O H_OE_1 O H_CLK_1 O 2 DBUG E 30(34)

39 3.11GPIO Table 3-10 J15 FPGA Pins Distribution FPGA 50P Double Signal Name I/O BANK Remarks Pin No. Row Pin No. 1 GND Output 5V; 2 VCC5 O Recommende 3 GND d current 4 VCC5 O output 1A 5 GND 6 VCC5 O 7 GND 8 VCC5 O 9 GND 10 VCC5 O H_G23 O 0 Customized H_B23 O 0 signal H_B22 O H_R23 O H_R22 O H_G22 O H_G21 O H_B21 O H_B20 O H_R21 O H_R20 O H_G20 O H_G19 O H_B19 O H_B18 O H_R19 O H_R18 O H_G18 O H_G17 O H_B17 O H_B16 O H_R17 O H_R16 O H_G16 O H_G15 O H_B15 O 1 DBUG E 31(34)

40 3.11GPIO FPGA 50P Double Signal Name I/O BANK Remarks Pin No. Row Pin No H_B14 O H_R15 O H_R14 O H_G14 O H_G13 O H_B13 O H_D_2 O H_R13 O H_B_2 O H_C_2 O H_LAT_2 O H_A_2 O H_OE_2 O H_CLK_2 O 1 DBUG E 32(34)

41 4Notes 4Notes Precautions for using development board are as follows: 1. Handle with care, and pay attention to electrostatic protection. 2. When downloading bitstream files to external Flash, set MODE pin state to correct configuration value, please refer to GW2A(R) series FPGA products Programming and Configuration User Guide for details; 3. USB download circuit is integrated on development board, and JTAG signal can be used as a download cable via pin 3 of J3 ~ J6: - If program is downloaded via USB, pin 2 and pin 3 of J3 ~ J6 pins need to be connected with jumper; - If program is downloaded via JTAG, pin 1 and pin 2 of J3 ~ J6 pins need to be connected with jumper; 4. After the development board is powered off, keep about 5 seconds before power on to ensure that the circuit state of the development board is zero. DBUG E 33(34)

42 5Gowin Software User Guide 5Gowin Software User Guide Please refer to Gowin Software User Guide for details. DBUG E 34(34)

43