Jignesh M. Patel. Blog:

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1 Jignesh M. Patel Blog:

2 Go back to the design Query Cache from Processing for Conscious 98s Modern (at Algorithms Hardware least for Hash Joins) Processor Processor Caches+TLB Processor Caches+TLB +Main Caches Memory +Main Memory +Multicore 23, Jignesh M. Patel, University of Wisconsin 2

3 Cycles / output tuple Probe Build ParBBon 5 4 Instruction path length is 58% of Radix 3.3x 3 more cache misses 7x more TLB misses on load 47% more cache 2 than Radix misses than Radix 24% faster 5% faster than WiscJ than Radix Radix WiscJ Radix WiscJ Intel Xeon Sun T2 22, Jignesh M. Patel, University of Wisconsin 3

4 Skew in partitioning- based hash join algorithms causes partition size skew à work imbalance Cycles / output tuple Probe Build Partition 2x faster than Radix Non- partitioned (Wisconsin) hash join improves with higher skew! 3.75x faster than Radix 6 cycles total Radix WiscJ Radix WiscJ Intel Xeon Sun T2 22, Jignesh M. Patel, University of Wisconsin 4

5 Hash join algorithm started simple, and with each architectural turn, it adapted. We have come full circle: The simple hash join is now very competitive. And, in many cases more efficient than the more complex methods! 22, Jignesh M. Patel, University of Wisconsin 5

6 π (project) σ (select) γ (aggregate) Fast & Data Scalable Relational- like τ U (sort) (join) (union) Data Processing Processing Primitives Kernels δ (anti- join) (bag- >set) (minus) 23, Jignesh M. Patel, University of Wisconsin 6

7 Want CPU caches Multicores, multi- socket, heterogeneous cores Constraint DRAM High Performance NVRAM (e.g. SSDs) Lower- powered, lower latency, higher bandwidth, persistent stores Low Cost Power Magnetic Hard Disk Drives 23, Jignesh M. Patel, University of Wisconsin 7

8 Goal Run data hardware speeds Short- term the speed of hardware today Long- term Hardware- software co- design for data kernels 24, Jignesh M. Patel, University of Wisconsin 9

9 Li and Patel, SIGMOD 3 What? Scan a column of a table applying some predicate Why? A key primitive in database The critical kernel in main memory analytic systems How? Conserve memory bandwidth: BitWeaving the data Use every bit of data that is brought to the processer efficiently using intra- cycle parallelism 24, Jignesh M. Patel, University of Wisconsin

10 Li and Patel, SIGMOD 3 Traditional Row Store shipdate discount quantity Mar % 5 Jan % 4 Apr % 3 May % 6 Feb % One big file shipdate Mar Jan Apr May Feb File: Column Store discount 5% 2% % % 5% File: n- quantity File: n 6 bits Order- preserving compression Column Codes: 3 bits , Jignesh M. Patel, University of Wisconsin

11 BitWeaving/H BitWeaving/V Code First batch of Processor Words (batch size = code size in bits) Code Code 5 Code 9 Code 3 Code 7 Code 2 Code 25 Code 29 Code 2 Code 6 Code Code 4 Code 8 Code 22 Code 26 Code 3 Code 3 Code 7 Code Code 5 Code 9 Code 23 Code 27 Code 3 Code 4 Code 8 Code 2 Code 6 Code 2 Code 24 Code 28 Code 32 Next batch of processor words First batch of Processor Words (batch size = code size in bits) 24, Jignesh M. Patel, University of Wisconsin Next batch of processor words 2

12 SELECT SUM(l_discount * l_price) FROM lineitem WHERE l_shipdate BETWEEN Date AND Date + year AND l_discount BETWEEN Discount. AND Discount +. AND l_quantity < Quantity BitWeaving/H l_price l_discount Aggregation RID List: 9, 5 Result bit vector Result bit vector AND Result bit vector BitWeaving/H Result bit vector AND Result bit vector l_quantity l_shipdate l_discount BitWeaving/V BitWeaving/V BitWeaving/H 24, Jignesh M. Patel, University of Wisconsin 3

13 Word Column Codes: The first (most significant) bits of 8 consecutive codes Word 2 The second bits of 8 consecutive codes Word 3 The third bits of 8 consecutive codes Word 4 The last (least significant) bits of 8 consecutive codes 24, Jignesh M. Patel, University of Wisconsin 4

14 Column Codes: Constant Predicate a < 5??????? Result Bit Vector Early Pruning: terminate the predicate evaluation on a segment, when all results have been determined. 24, Jignesh M. Patel, University of Wisconsin 5

15 Early pruning probability: 96% at bit position 4 Early Pruning Probability P(b) % 8% 6% 4% 2% % Segment size: 64 codes, code size: 32 bits Early pruning probability: 98% at bit position 8 Fill factor:% Fill factor: % Fill factor: % This cut- off mechanism allows for efficient evaluation of conjunction/disjunction Bit Posi8on b predicates 24, Jignesh M. Patel, University of Wisconsin 6

16 Segment Code size (3 + bits) c c2 c3 c4 c5 c6 c7 c8 c9 c c c2 c3 c4 c5 c6 c7 c8 c9 Segment word Predicate evaluation is done on the 4 codes in parallel c c5 c9 c3 < 5? Memory space word 2 word 3 word 4 c2 c6 c c4 c3 c7 c c5 c4 c8 c2 c6 Word size (6 bits) 24, Jignesh M. Patel, University of Wisconsin 7

17 Uses only 3 instructions! Without the delimiter, we would need ~2 instructions c= c5=7 c9=6 c3=2 X = ( c c 5 c 9 c ) 3 Y = 5555 ( ) ( Y + (X M) ) M 2 M = M2 = Works for arbitrary code sizes & word sizes! 24, Jignesh M. Patel, University of Wisconsin 8

18 Segment Code size (3 + bits) c c2 c3 c4 c5 c6 c7 c8 c9 c c c2 c3 c4 c5 c6 c7 c8 c9 Memory space Segment word word 2 word 3 word 4 c c5 c9 c3 c2 c6 c c4 c3 c7 c c5 c4 c8 c2 c6 < 5? < 5? < 5? < 5? >> >> >>2 >>3 c c2 c3 c4 Word size (6 bits) Result bit vector computed efficiently with this layout! 24, Jignesh M. Patel, University of Wisconsin 9

19 SYSTEM Intel Xeon X bits ALU 28 bits SIMD 2MB L3 Cache 24GB memory Single threaded execution WORKLOAD. Synthetic SELECT COUNT(*) FROM R WHERE R.a < C billion tuples Uniform distribution Selectivity: % 2. TPC- SF= scan only with materialized join results 24, Jignesh M. Patel, University of Wisconsin 2

20 8 Cycles / code 6 4 Naive Size of code (# bits) 24, Jignesh M. Patel, University of Wisconsin 2

21 SIMD Paper: T. Willhalm, N. Popovici, Y. Boshmaf, H. Plattner, A. Zeier, and J. Schaffner. SIMD- Scan: Ultra fast in- memory table scan using on- chip vector processing units. PVLDB 9 8 2X: SIMD parallelism Cycles / code Naive SIMD Size of code (# bits) 24, Jignesh M. Patel, University of Wisconsin 22

22 Blink Paper: R. Johnson, V. Raman, R. Sidle, and G. Swart. Row- wise parallel predicate evaluation. VLDB 8 8 Cycles / code Naive SIMD BL Size of code (# bits) 24, Jignesh M. Patel, University of Wisconsin 23

23 Cycles / code X- 4X speedup over BL: ) Use the extra (delimiter) bit 2) Easy to produce the result bit vector with the HBP layout Naive SIMD BL 2 BitWeaving/H Size of code (# bits) 24, Jignesh M. Patel, University of Wisconsin 24

24 8 Cycles / code Naive SIMD BL BitWeaving/H BitWeaving/V Size of code (# bits) Many more experiments in the paper 2X speedup: Early pruning 24, Jignesh M. Patel, University of Wisconsin 25

25 Customer Product Buy cid cname gender address Andy M Main st. 2 Kate F 2 th blvd. 3 Bob M 3 5 th ave. pid pname Milk 2 Coffee 3 Tea cid pid status 2 S 2 2 F 3 3 S 2 S cid cname gender address pid pname status Andy M Main st. 2 Coffee S 2 Kate F 2 th blvd. 2 Coffee F 3 Bob M 3 5 th ave. 3 Tea S Andy M Main st. 2 Coffee S NULL NULL NULL NULL Milk NULL WideTable 24, Jignesh M. Patel, University of Wisconsin

26 WideTable Denormalization Column-store Packed Scan Dictionary encoding Now we can run analytical workloads (e.g. TPC- H) using simple BitWeaved scans 24, Jignesh M. Patel, University of Wisconsin

27 Data Schema Graph Query Quickstep/WT Query Transformer Denormalizer Schema transformer Flatten using Bit- Weaved Scans {WideTables} Results Non- transformable query sent to the source system 24, Jignesh M. Patel, University of Wisconsin 28

28 Customer Customer Nation Region Buy Nation Region Buy Product Schema Graph Product Nation Schema Tree Region WideTable = (Region Nation Customer) (Region Nation Product Buy) SMW = {WideTables } e.g. for TPC- H, SMW={lineItemWT, orderswt, partsuppwt, customerwt} 24, Jignesh M. Patel, University of Wisconsin 29

29 TPC- H Queries Joins Nested Queries Non- FK joins WideTable Q, Q6 LineitemWT Q3, Q5, Q7- Q, Q2, Q4, Q9 LineitemWT Q4, Q5, Q7, Q8, Q2 LineitemWT Q Q2, Q, Q6 PartsuppWT Q3 OrdersWT Q22 OrdersWT 24, Jignesh M. Patel, University of Wisconsin 3

30 SYSTEM Intel Xeon E GHz 2 cores / 24 threads 5MB L3 Cache 32G, 6MHz DDR3 BENCHMARK SF: (~GB) SMW = lineitemwt orderswt partsuppwt customerwt dictionaries filter columns TOTAL 5.4 GB.7 GB.2 GB.5 GB.8 GB.3 GB 8.5GB 24, Jignesh M. Patel, University of Wisconsin 3

31 WideTable over X faster than MonetDB for about half of the 2 queries Speedup over MonetDB to Q Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q Q Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q2 Q22 24, Jignesh M. Patel, University of Wisconsin 32

32 Speedup over MonetDB WideTable scales better to Q Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q Q Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q2 Q22 24, Jignesh M. Patel, University of Wisconsin 33

33 CPU caches Multicores, multi- socket, heterogeneous cores DRAM NVRAM (e.g. SSDs) Lower- powered, lower latency, higher bandwidth, persistent stores Magnetic Hard Disk Drives 23, Jignesh M. Patel, University of Wisconsin 34

34 22, Jignesh M. Patel, University of Wisconsin 35

35 Long Term: Raw computing + Server Box Processor and storage costs Memory Bus tends to zero! Memory The cost is in I/O Bus moving data and Spinning Disk powering the Modern Server Box circuits/devices For many decades 23, Jignesh M. Patel, University of Wisconsin Today Processor Memory Bus Memory I/O Bus Spinning Disk + 36

36 Do et al., SIGMOD 3 Total Energy (KJ), log scale Inside TPC- H the Flash Q6, SSD SF SRAM Host Interface Controller Embedded Processor Smart SSD DRAM Controller SAS SSD Bus Controller Bus Controller Bus Controller.5X Data storage Elapsed Time (seconds), log scale DRAM F F F HDD F F F.8X Bandwidth Relative to the I/O Interface Speed 27 Internal SSD I/O Interface 29 2 Year There Besides are similar data storage ways of using it has hardware creatively, Can we gain efficiency (performance and e.g. High IDISKs, I/O bandwidth ASICs, CGRA, inside FPGAs, the flash or chips GPUs. energy) Embedded by pushing computing big power data processing Basically, General- purpose primitives need hardware into memory the and Smart software SSD? synergy! 23, Jignesh M. Patel, University of Wisconsin 37

37 X, GPU X, CPU X, CPU X, CPU X, CPU X, CPU X, CPU X, GPU Scan Scattered Read/Write Sequential read kernel Index access kernel 23, Jignesh M. Patel, University of Wisconsin 38

38 Transformative architectural changes at all levels (CPU, memory subsystem, I/O subsystem) is underway Need to rethink data processing kernels current bare metal speed Need to think of hardware software co- design Big Data Hardware Big Data Software 23, Jignesh M. Patel, University of Wisconsin 39