Workload Optimized Systems: The Wheel of Reincarnation. Michael Sporer, Netezza Appliance Hardware Architect 21 April 2013

Transcription

1 Workload Optimized Systems: The Wheel of Reincarnation Michael Sporer, Netezza Appliance Hardware Architect 21 April 2013

2 Outline Definition Technology Minicomputers Prime Workstations Apollo Graphics Stellar/Stardent SMP Database Machines Data General MPP Database Machines Netezza/IBM What s Next? Conclusion 2

3 What Is Workload Optimized? Technology is advancing Groups of technologies play together Step functions lead to qualitative opportunities Opportunity is defined by a specific market Market is identified by workload Hardware/Software co-design optimize workload Often startups are leading indicator Established vendors follow or perish 3

4 Technology - Hardware Transistor Technology Moore s Law ICs -> CPUs, ASICs, FPGAs DRAM Busses and their protocols Magnetic Recording Technology - bpi Disks Networks Ethernet, primarily Graphic displays -> GPUs Cache and chip interconnect SMP and NUMA 4

5 Technology - Software Time-share OS Virtual Memory Languages: ASM, Fortran, C, C++, Java Object-Oriented Methods Open Source 5

6 Minicomputer Prime (1) Early 1970 s Engineers need computer access Mainframes too expensive 6 New IC technology, DRAM, PROM and costeffective, removable 14 Winchester disk drives Firmware technology for flexibility and ISA range Virtual memory and large address spaces OS technology pioneered by MULTICS

7 Minicomputer Prime (2) 7 Designed a multi-user time-shared minicomputer for CAD and SW development Architecture defined by software engineers Wrote our own optimizing compilers Process switch and VM table walk in firmware 32-bit ISA as extension to prior 16-bit version All 16-bit applications ran at GA New and recompiled apps ran in 32-bit mode Floating Point in firmware in PROM

8 Workstation Apollo (1) Early 1980 s Engineers needed dedicated performance Workgroups cooperating 8 Early microprocessors (68010) Ethernet proves networks can be built High resolution graphic displays available Bit-map technology proven by PARC and MIT

9 Workstation Apollo (2) Design a personal engineering workstation High resolution bit-map display Network OS with seamless file sharing 2D graphics SW system for cut and paste VM implemented by using 2x68010 Application development environment 9

10 Graphics Supercomputer Stellar/Stardent (1) Engineers need 3D displays for CAD, Biotech Heavy compute load using multiple threads 10 Sea-of-gates IC technology YACC Single-clock scan path design proven (by IBM) Parallelizing compilers beginning to be understood

11 Graphics Supercomputer Stellar/Stardent (2) Design a Graphics Supercomputer 20 MIPs, 80 MFLOPs, 120K Gouraud-shaded triangles Home-brew C-like simulation language using YACC 11 designs, 49 SEA-of-Gates chips per system First-pass operational Scan path SW Unix OS Home-brew parallelizing Fortran compiler 11

12 SMP Database Machine Data General (1) Early 90 s Database usage surging mostly OLTP 12 SMP reaching limits Dense AISCs available Intel CPUs becoming good

13 SMP Database Machine Data General (2) 13 Need lots of CPUs and lots of I/O to process the high OLTP tps demands and database size Design a 32-way system with distributed I/O SMP: 8 groups of 4-way M88K CPUs on a packet bus NUMA: 8 groups of 4-way Pentium CPUs on an SCI bus DG/UX to handle NUMA I/O subsystem aware of NUMA

14 MPP Database Machine Netezza/IBM (1) Data accumulating could it be used? OLTP systems groaning under OLAP workloads 14 Cyber Bricks at Microsoft computation is low cost Active Disks at CMU parallel algorithms near disk Inexpensive low-power CPU Inexpensive FPGA Inexpensive consumer disks Cheap 100Mb -> 1Gb Ethernet

15 MPP Database Machine Netezza/IBM (2) Design a simple SPU disk + FPGA + CPU + NIC Put lots into a rack Develop MPP SW Postgres front end Tuned Optimizer Parallelizer Query compiler code for CPU and FPGA Distributer of Snippet of work FPGA Decompress, Restrict, Project reduce CPU load Appliance easy to install, use, service, support 15

16 Netezza Snippet Processor 16 GigE to each SPU 1 GB RAM Socketed DIMM Enterprise SATA Disk Drive 400 GB CPU FPGA Disk Network 440GX Power PC 1M Gate FPGA

17 Netezza Streaming Processing 17 Zone Maps Base Table Data Blocks CBT Maps Dim 2: Zip Identify work not needed to done Do as much work as we can in parallel on SPU Move restricts into the FPGA Increase effective disk performance Execute operational streaming analytics Analytic Functions On Stream Col 1: Date Col 2: Zip Zone Maps: 18 out of 48 Extents Read Snippet Queue PowerPC Query Engine Joining Sorting Grouping Main Memory Dimension 1: Date CBT: 2 out of 48 Extents Read Streaming Record Processor DMA Project Restrict Compiled Tables Primary Mirror SPU Swap Transaction/Lock Manager Fault Recovery

18 First product 2003 Netezza Evolution MHz CPU 112 small FPGAs 8-bit datapath 64MB DRAM 33MB/s 40GB disk Current product GHz CPU cores 112 FPGA cores 32-bit datapath 8GB/core DRAM + 512MB/FPGA core for disk cache 160MB/s 600GB disk 18

19 What Netezza Got Right Streaming balanced architecture Disk, CPU, network overlap query time is max of all 3 FPGA technology Improve scan performance of HDD Decrease data to be processed by CPU -> cheap CPU MPP move processing toward disk Focus on GB/sec/$ 19 New products when step function in technology

20 What s Next From Market? Competition in markets Urgency to get ahead or at least stay even Need more sophisticated use of data More complex analytics On more data Better ability to do what if More uses and users of DB systems 20

21 What s Next From Technology? At limit of number of disks per rack Cache often not big enough 21 Flash provides very high IOPs Crossover IOPs/$ Lots of cores per CPU Lots of DRAM bandwidth Faster, lower overhead networks using RDMA GPUs can they be harnessed? FPGAs how do we get SW developers to use them?

22 Conclusions We are ready for a big step in technology (>10x) Old SW stacks will no longer work OLTP systems continue to not scale OLAP systems centered on HDDs 22 What are SW limits? MPP can it scale to 1000 nodes? How about 10,000? How do we minimize overheads hidden by HDDs? It is imperative for HW/SW to be co-designed. How are you handling it?