2 protocol and ISO/IEC C, Qstar-5R. series is. tag chips. What s. more, it. up to 30. years in. dbm [2] QSTAR FAMILY - Qstar-5R series

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1 - Ver APR24, 2017 Datasheet for Public Use Overview Conforming to EPCglobal Class 1 Gen 2 protocol and ISO/IEC C, Qstar-5R series is a highly integrated UHF RFID tag chips with industry leading sensitivity, reliability, consistency and flexibility even with 64Kbit user memory. What s more, it has an outstanding data retention of up to 30 years in 85 (Qstar-5RXP-E [1] only). Features Read sensitivity of up to -17 dbm [2] Write sensitivity of up to -11dBm [2] Extended temperature range (-55 ~ +150 ) for reliability in harsh conditionn EPCglobal Gen 2( V1.2.0) and ISO/IEC CC Compatible Up to 496 bits of EPC memory (Except CRC, PC) ). Up to 208 bits of TID memory Up to 64K bits of USER memory Up to 30 years of data retention time in 85 (Qstar-5RXP-E [1] only) Support BlockPermaLock: minimum lock size is 1 word, minimum lock size is 4 words.( (more information refers to Table 12.) Qstar-5R Series Datasheet Copyright 2017 Quanray Electronics Page: 1/22

2 Support BlockWrite: 1-8 words EPCglobal Gen2 (V1.2.0) and ISO/IEC C air interface (Ref[1]) [1] Qstar-5RXP-E is the memory reliability enhanced version of Qstar-5RXP. [2] Sensitivity on a dipole antenna. Key applications Aerospace /Railway Intelligent Manufacturing Intelligent Oil and Gas Pipe Industrial Assent management Smart City MRO Intelligent Constuction Qstar-5R Series Datasheet Copyright 2017 Quanray Electronics Page: 2/22

3 Contents 1. PRODUCT FAMILY OVERVIEW PAD DESCRIPTION WAFER LAYOUT MECHANICAL SPECIFICATION WAFER DIRECTION ON FRAME SPECIFICATION FOR FRAME AND FILM WAFER SPECIFICATION BUMP SPECIFICATION STORAGE ENVIRONMENT WAFER MAPPING WAFER PACKAGING ROHS REQUIREMENTS FUNCTIONAL DESCRIPTION SUPPORTED COMMANDS MEMORY CHARACTERISTICS PACKAGE OUTLINE SOLDER BUMP (WLCSP) SOP8L PINNING PIN DESCRIPTION TAPE AND REEL QFN8L PINNING PIN DESCRIPTION TAPE AND REEL REFERENCES Qstar-5R Series Datasheet Copyright 2017 Quanray Electronics Page: 3/22

4 1. Product family overview Table 1. Feature overview of family Ordering Number USER [1] (bit) EPC [2] (bit) TID (bit) Un bumped Wafer Gold bumped Wafer WLCSP SOP8L QFN8L Qstar-5AGU 64K Qstar-5AGB 64K Qstar-5AGW 64K Qstar-5AGS 64K Qstar-5AGF 64K Qstar-50GU 32K Qstar-50GB 32K Qstar-50GW 32K Qstar-50GS 32K Qstar-50GF 32K Qstar-59GU 16K Qstar-59GB 16K Qstar-59GW 16K Qstar-59GS 16K Qstar-59GF 16K Qstar-58GU 8K Qstar-58GB 8K Qstar-58GW 8K Qstar-58GS 8K Qstar-58GF 8K [1]: Support flexible USER memory configuration with the command of BlockPermaLock. (Refer to section 5.1). [2]: EPC is including CRC(16bits) and PC(16bits). Qstar-5R Series Datasheet Copyright 2017 Quanray Electronics Page: 4/22

5 Q s t a r 5 R X P /- Z [1] P:Package type X:Protocol type R:Size of user Memory 5:Product Serial Number Table 2. Size of user Memory(bits) Symbol(R) A 2rd Digits Description 8K 16K 32K 64K Table 3. Protocol type Symbol(X) 3rd Digits Description G Gen2 Table 4. Package type Symbol(P) B F S U W 4th Digits Description Bumped Wafer QFN8L SOP Unbumped wafer WLCSP Table 5. Special Digits Symbol(Z) E No code Digits Description Enhanced Reliability Standard Reliability [1]: Special Digits: Z, defined as chip with reliability and always located the ends. Qstar-5R Series Datasheet Copyright 2017 Quanray Electronics Page: 5/22

6 2. Pad Description There are totally 4 external pads for chip packaging: two antenna pads and two non-connected dummy pads. Fig.1 shows tag chip. Fig.1 Pad location and description for Chip Size (without scribe lane): 1500 x 1500 um Bumping pad: A1,A2,D1,D2 Table 6. Pad description for PAD Name Description Pad Window Size A1 RF Pad 80 x 80 um A2 Vss Pad 80 x 80 um D1 DUMMY 62 x 62 um D2 DUMMY 62 x 62 um Qstar-5R Series Datasheet Copyright 2017 Quanray Electronics Page: 6/22

7 3. Wafer Layout For delivered wafers, Fig.2 shows the related parameters. Fig.2 Wafer parameters for Qstar-5R Series Datasheet Copyright 2017 Quanray Electronics Page: 7/22

8 Table 7. Specific parameter values Parameters (1) X-scribe line width (2) Y-scribe line width (3) Chip step, x-length (4) Chip step, y-length (5) Gap, pad D1 to pad D2(X) (6) Gap, pad D2 to pad A2 (Y) (7) Gap, pad to seal ring X (8) Gap, pad to seal ring Y (9) Gap, pad A1 to pad A2 (X) Target Value 60 um 60 um 1560 um 1560 um 1220 um 1202 um 52 um 52 um 1184 um 4. Mechanical Specification 4.1 Wafer direction on frame Before delivered to the customers, wafer processess such as Back-grinding, dicing, bumping, passivation layers, will be included. Customers can also require special process combinationn for the ordered wafers. Fig.3 shows the wafer direction on frame. Fig.3 Wafer Direction on Frame for Qstar-5R Series Datasheet Copyright 2017 Quanray Electronics Page: 8/22

9 4.2 Specification for Frame and Film Table 8. Specification for Wafer Frame Parameters Inner Diameter of Frame (d, Fig. 4) Outer Diameter of Frame (A, Fig. 4) Frame Thickness (t, Fig. 4) Film property Film Thickness Target Value 252mm 275mm Metal: /-0.2 mm Plastic: mm UV tape 90um Toleranc e + /-4mm + /-1mm NA +/ /-20um Film minimum tensile strength Adhesive strength between chip and film after UV irradiation >25N/mm2 90mN / 25mmm +/ /- 10mN Fig.4 Dimension of the Frame for Qstar-5R Series Datasheet Copyright 2017 Quanray Electronics Page: 9/22

10 4.3 Wafer Specification Table 9. Specification for the Wafer Parameters Target Value Tolerance Wafer Size 8 (200mm) Wafer Thickness 150um +/- 10% Wafer Backside Material Si Wafer Backside Treatment Ground Scribe Line 60 um Pad Opening Size A1/A2: 80 x 80 um D1/D2: 62 x 62 um Passivation on Front HDP OX 10k /SRO 1500 /UVSIN 6k Passivation Thickness 1.75 um Pad Composition Al % Cu -0.5% 4.4 Bump Specification Table 10. Specification for the bumping Parameters Target Value Tolerance Bump material 99.9% pure Au Bump type Electroplated Au PI thickness 3.6 +/- 1 um Bump height 18 um +/- 3um Bump size Bump Co-Planarity A1/A2: 88 x 88 um D1/D2: 70 x 70 um 5um within wafer 2um within die Roughness 2um within Bump Hardness 50 HV +/- 15 HV Shear force 5g/mil2 Under bump metallization UBM Sputtered TiW Qstar-5R Series Datasheet Copyright 2017 Quanray Electronics Page: 10/22

11 4.5 Storage Environment Table 11. Wafer Storage Environment Chip Status Storage Temp. and Humidity Nitrogen Environment Storage Condition (After Delivery) within Sealed, 6 months Sawn wafer on UV tape C 40 ~ 60 %RH within Un-Sealed, 3 months without Un-Sealed, 10 days 4.6 Wafer Mapping Wafer Mapping Format: mapping format of TSK probing station (UF200a). Compatible with Muehlbauer TAL and FCM. 4.7 Wafer Packaging Wafer package for Qstar-5RXP(-E) is ESD-protected and sealed against moisture or contamination. 4.8 RoHS requirements The product must be RoHS compliant. The detailed requirements are referred to QP7513 General Specification on Substance Control Requirements. Qstar-5R Series Datasheet Copyright 2017 Quanray Electronics Page: 11/22

12 5. Functional description The tag chip fully supports all requirements of the "Specification for RFID Air Interface EPCglobal, EPC Radio-Frequency Identity Protocols, Class-1 Generation-2 UHF RFID, Protocol for Communications at 860 MHz to 960 MHz, Version 1.2.0". 5.1 Supported Commands The tag chip supports all mandatory EPCglobal V1.2.0 commands. The tag chip supports the following optional commands. Access BlockWrite (1to 8 words) BlockErase (1to 8 words) BlockPermaLock Table 12. BlockPermaLock Lock Size Definition Ordering Number USER Bank Memory(bits) BlockPermaLock Lock Size Qstar-5AXP 64K 4 words Qstar-50XP 32K 4 words Qstar-59XP 16K 1 word Qstar-58XP 8K 1word Qstar-5R Series Datasheet Copyright 2017 Quanray Electronics Page: 12/22

13 5.2 Memory Table 13. Mapping table for Air Interface of Bank Memory Address Description Memory type Bits TID bank 00h-CFh Unique Tag ID ROM h-0Fh CRC-16 RAM 16 EPC bank 10h-1Fh PC NVM 16 20h-20Fh EPC NVM 496 Reserved bank 00h-1Fh Kill password NVM 32 20h-3Fh Access password NVM 32 Table 14. Mapping table for Air Interface of (User bank) Ordering Number Bank Memory Address Memory type Bits Qstar-5AXP User bank 0000h-FFFFh NVM 64K Qstar-50XP User bank 0000h-7FFFh NVM 32K Qstar-59XP User bank 0000h-3FFFh NVM 16K Qstar-58XP User bank 0000h-1FFFh NVM 8K Qstar-5R Series Datasheet Copyright 2017 Quanray Electronics Page: 13/22

14 6. Characteristics Table 15. Operating conditions and electrical characteristics Parameters Conditions Min Typ Max Unit Operating Frequency Air Interface Characteristics Supported Frequency Range MHz Read Sensitivity Normal Read [1] - dbm Write Sensitivity Normal Write, Block Write [1] - dbm Maximum operating power dbm Equivalent input parallel resistance Equivalent input parallel capacitance Data retention (Qstar-5RXP) Data retention (Qstar-5RXP-E [2] ) At minimum input power [3][4][5] - Ω At minimum input power [3][4][5] - pf Memory Characteristics Temperature year Temperature year Endurance Temperature85-100,000 - cycle [1] Sensitivity on a dipole antenna. [2] Qstar-5RXP-E is the memory reliability enhanced version of Qstar-5RXP. [3] At minimum operating power and at 920MHz operating frequency point. [4] Only intrinsic capacitance is included. [5] Measured by Network Analyzer on straps (Wire bonding packaging). Table 16. Limiting Parameters Parameters Conditions Min Typ Max Unit Operating Temperature Normal application Storage Temperature Harsh environments ESD Human Body Model - ± V Qstar-5R Series Datasheet Copyright 2017 Quanray Electronics Page: 14/22

15 7. Package outline 7.1 Solder bump (WLCSP) Parameter Symbol Nominal Min Max Nominal Min Max Millimeters Inches Package Body Dimension X A Package Body Dimension Y B Package Height C Silicon +Back cover Thickness C Ball Height C Ball Diameter D Total Ball Count N 4 Ball Count X axis N1 2 Ball Count Yaxis N2 2 Pins Pitch X axis J Pins Pitch Y axis J BGA ball center to package center offset in X-direction X BGA ball center to package center offset in Y-direction Y BGA ball center to chip center offset in X-direction X BGA ball center to chip center offset in Y-direction Y Edge to Ball Center Distance along X S Edge to Ball Center Distance along Y S Fig.5.1 Parameters for Solder bump packaging Fig.5.2 Description for laser marking method The opposite pad of laser dot is A1. Laser mark (5 digits): - The number 1,2,3,4 on behalf of silicon wafer LOT ID. - The number 5 on behalf of Wafer ID. From 1 to 9, and A to S For example, for the 12th piece of silicon wafer of Lot ID.DP3768,marked characters will be 3768C. Qstar-5R Series Datasheet Copyright 2017 Quanray Electronics Page: 15/22

16 Fig.7 shows the information for tape and reel. Fig.6 Description for tape and reel of solder bump packaging. Table 17. Equivalent Input Parametersof WLCSP Parameters Conditions Min Typ Max Unit Equivalent input parallel resistance (WLCSP) Equivalent input parallel capacitance (WLCSP) Air Interface Characteristicss At minimum input power At minimum input power 3100 [ [1 1][2] 1][2] Ω pf [1] At minimum operating power and at 920MHz operating frequency point. [2] Only intrinsic capacitance is included. Qstar-5R Series Datasheet Copyright 2017 Quanray Electronics Page: 16/22

17 7.2 SOP8L Fig.7 Package outline SOP8L Qstar-5R Series Datasheet Copyright 2017 Quanray Electronics Page: 17/22

18 7.2.1 Pinning 1 8 RF Vss A5A0M33G01 QSTAR-50GS Fig.8 Pin configuration Marking: -One dot for No.1 footprint indication. -9 digits Product Type,such as QSTAR-50GS -12 digits is Product serial Number, such as 23A5A0M33G Pin description Table 18. Pin description (Other pins are floating, except Pin2 and Pin3.) Symbol Pin Description RF 2 Antenna Vss 3 ground Qstar-5R Series Datasheet Copyright 2017 Quanray Electronics Page: 18/22

19 Table 19. Equivalent Input Parametersof SOP8L Parameters Conditions Min Typ Max Unit Equivalent input parallel resistance (SOP8L) Equivalent input parallel capacitance (SOP8l) Air Interface Characteristics At minimum input power 3150 [1][2] Ω At minimum input power 1.2 [1][2] pf [1] At minimum operating power and at 920MHz operating frequency point. [2] Only intrinsic capacitance is included Tape and Reel Fig.9 Tape and Reel Qstar-5R Series Datasheet Copyright 2017 Quanray Electronics Page: 19/22

20 7.3 QFN8L Fig.10 Package outline QFN8L Qstar-5R Series Datasheet Copyright 2017 Quanray Electronics Page: 20/22

21 7.3.1 Pinning Fig.11 Pin configuration Marking: -One dot for No.1 footprint indication Pin description Table 20. Pin description (Other pins are floating, except Pin2 and Pin5.) Symbol Pin Description RF Pin 2 Antenna Vss Pin 5 ground Table 21.Equivalent Input Parametersof QFN8L Parameters Conditions Min Typ Max Unit Equivalent input parallel resistance (QFN8L) Equivalent input parallel capacitance (QFN8L) Air Interface Characteristics At minimum input power 2238 [1][2] Ω At minimum input power 1.08 [1][2] pf [1] At minimum operating power and at 920MHz operating frequency point. [2] Only intrinsic capacitance is included. Qstar-5R Series Datasheet Copyright 2017 Quanray Electronics Page: 21/22

22 7.3.3 Tape and Reel TBD 8. References Ref [1]: EPC Radio-Frequency Identity Protocols Class-1 Generation-2 UHF RFID Protocol for Communications at 860 MHz MHz Version Qstar-5R Series Datasheet Copyright 2017 Quanray Electronics Page: 22/22