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Rodney Cross
5 years ago
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6 next generation intelligent computing systems design (HW/SW)

9 What re your thoughts on the future of computing?

10 Transistor density of semiconductor chips will increase by 2X every 18 months Computing is here to stay, the complexity and parallelisation will only rise with generations; it s important that we understand every bit of it as electronic engineers

14 Symbol V GS Gate Insulator V DS More electronics Source (n+) Channel Drain (n+) Substrate (p)

15 Symbol V GS Gate Insulator V DS More holes Source (p+) Channel Drain (p+) Substrate (n)

17 +ve supply at gate in will see NMOS shorted to ground ve supply at gate in will see PMOS shorted to Vdd

18 +ve supply at A will see NMOS shorted to ground; PMOS open ve supply at A will see PMOS shorted to Vdd, NMOS open +ve supply at B will see NMOS shorted; PMOS open ve supply at B will see PMOS shorted to Vdd, NMOS open Now consider different A and B scenearios: like A and B are both +ve

19 +ve supply at A will see NMOS shorted to ground; PMOS open ve supply at A will see PMOS shorted to Vdd, NMOS open +ve supply at B will see NMOS shorted to ground; PMOS open ve supply at B will see PMOS shorted to Vdd, NMOS open Now consider different A and B scenearios: like A and B are both ve

20 Q outputs D input when Clock (C) is also positive Q_bar outputs D inverse when Clock (C) is also positive Clock and D drives the outputs The most basic sequential component

22 Gaming & media Commun. Devices Homes, Offices and Servers Security & Retail Computing Medical health care Industrial Control Transport

High Performance Computing Performance is key Highly parallel

! $$$$$$$ General purpose computing Performance is traded off

Computing Battery operated mostly Parallelism depends on

feature 4 8 cores Body sensor controllers have simpler single

23 High Performance Computing Performance is key Highly parallel systems Expensive!! $$$$$$$ General purpose computing Performance is traded off with costs Generally features parallel systems Embedded Computing Battery operated mostly Parallelism depends on performance requirements Modern mobile computing systems feature 4 8 cores Body sensor controllers have simpler single core systems Has to be light weight and low cost (and sometimes highly reliable) Modern cars have hundreds of systems in various places

24 Memory (DRAM) ports Fanless Heatsinks Core to computation is the processor and memory organisation IO devices allow various userinterfaced functionality Modularisation keeps things simple IOs and interfaces CPU/CPU socket PCI 1 3

Key components of a microprocessor: Memories Busses/Interconnects

) IOs and controllers Processor #1 Processor #n Datapath Registers

Cache Tightly Coupled Memory Data Cache (L1/L2) Shared Cache (L3)

25 Key components of a microprocessor: Memories Busses/Interconnects Processors (CPU, etc.) IOs and controllers Processor #1 Processor #n Datapath Registers Instr. Cache Datapath Registers Instr. Cache Tightly Coupled Memory Data Cache (L1/L2) Shared Cache (L3) Tightly Coupled Memory Data Cache (L1/L2) Interconnect(s) Memory #1 Memory Controllers (DMA etc.) Memory #N Bus and IO/Peripheral Controller IOs and Peripherals

27 Dynamic random access memory DRAM Static random access memory SRAM Cache L1/L2/L3 Cache Synchronous dynamic random access memory SDRAM Volatile Memory Nonvolatile memory Main Memory 6T RAMs CDROM ROM Electrically Erasable Programmable Read Only Memory EEPROM

29 Processor core with registers Instruction Cache Data Cache Cost Performance Memory Registers Access time 1 ns Capacity 1 Kb Level 2 Cache (SRAM) Cache Main memory 10 ns 100 ns 8 Mb 8 Gb Main Memory (DRAM) Size Hard drive ns 4 Tb

elements and how they are organised has direct performance and cost impact

30 The memory elements close to CPU are generally the fastest, and the costliest The memory elements further from the CPU are slower, and cheaper The sizes of memory elements and how they are organised has direct performance and cost impact Microprocessor designers have to carefully organise the size and hierarchy for cost and performance trade offs

33 A 6T SRAM cell I2 I1

34 A 6T SRAM cell I2 I1

37 L1 Miss Latency L1 Miss Latency = L2 Hit Ratio * L2 Hit Latency + L2 Miss Ratio * L2 Miss Latency and so on Caches are organised in blocks, i.e. 1kB organised in 32 Byte blocks (Latency) Cache management needs *very* careful design

38 1T DRAM cell (BL) (WL)

39 1T DRAM cell (BL) (WL)

40 Clocks per instruction Clocks per DRAM access

43 Total disk capacity = sector size number of sectors per track number of tracks per cylinder number of cylinders

51 Optional reading: Strukov et al: The missing memristor found, Nature, 2008 Also Leo Chua s paper

55 Processor #1 Memory #1 Peripheral #1 IO #1 Processor #1 Memory #2 Peripheral #2 IO #2 Processor #1 Memory #3 Peripheral #3 IO #3 Processor #P Memory #M Peripheral #P IO #N

56 Interconnection network

58 accessed shared power managed

59 Uneven wire lengths between send and receive nodes Bound to cause skew between them Designer need to design protocols addressing worst case skew times

68 A bus transaction (or bus cycle) includes two parts: Issuing the command and address and transferring the data The master starts the bus transaction through command & address The slave is the one who responds to the address by: Sending data to the master upon request Receiving data from the master Master issues command Bus Master Data can go either way Bus Slave master CPU CPU CPU I/O Co-processor slave memory I/O Co-processor memory memory description Fetching code or data Data transfer Graphics operations Data transfer Data transfer

69 AMBA: Advanced Microprocessor Bus Architecture Family of ARM s interconnect systems High Bandwidth External Memory Interface High Performance ARM processor Adv. High-performance Bus (AHB) Adv. Peripheral Bus (APB) APB Bridge UART Timer Keypad High-bandwidth on-chip RAM DMA Bus Master PIO High Performance Pipelined Burst Support Multiple Bus Masters Low Power Non-pipelined Simple Interface

73 Arbiter centralized arbitration / decode Master #1 HADDR HWDATA HRDATA HRDATA HADDR HWDATA Slave #1 1 unidirectional address bus (HADDR) 2 unidirectional data Master #2 Address/Control Slave #2 buses (HWDATA, HRDATA) Master #3 Write Data Read Data Slave #3 At any time only 1 active data bus Slave #4 Decoder

74 Multiplexed masters Multi layered masters New AXI4 AMBA standards feature multi layering, simpler handshaking and burst trans. Higher performance

75 PCI: Peripheral component interconnection High speed shared bus Intel released PCI in public domain in 1990s Bit/speed width depends on the Peripherals (eg: 32, or 64 bits at 66MHz)

82 NoC connected cores

83 Can borrow much from computer network practices Software Transport Traffic Modeling Architectures Queuing / Routing Theory Network Wiring Separation of concerns Networking

84 North Buffer LOGIC North Buffer LOGIC South East West Core Buffer Buffer Buffer Buffer LOGIC LOGIC LOGIC LOGIC Arbitration Routing South East West Core Buffer Buffer Buffer Buffer LOGIC LOGIC LOGIC LOGIC

85 Router in (a packet) Router out (a packet) FIFO controller Packet Data Packetiser or Data Depacketiser Data FIFO controller Core in (a packet) Core out (a packet)

87 Question: what motivated the designer to choose AHB crossbar switch?

90 The brain of the computing system, meant to carry out the intended functionality, as and when needed. Data Processor Processed data

91 Instructions Data CPU Processed data Simplified example of an instruction: Opcode Mode register Address

92 Memory Instruction / Data Control Process

93 Peripherals Computer CPU: Central Processing Unit Memory Computer System Interconnects Communication lines Input Output

94 CPU I/O Computer System bus Memory CPU Registers Internal Interconnects Arithmetic and Logic Units Control Unit

95 CPU I/O Computer System bus Memory CPU Registers Internal Interconnects Arithmetic and Logic Units Control Unit

100 Status Registers: A set of bits Includes Condition Codes Sign of last result Zero, Carry, and Equal Overflow Interrupt enable/disable Supervisor

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registers 16 bit status register (SR) 32 bit supervisor stack pointer (SSP) 32 bit

102 V1 Coldfire user visible registers 16 general purpose 32 bit registers (D0 D7, A0 A7) 32 bit program counter (PC) 8 bit condition code register (CCR) Internal (system) registers 16 bit status register (SR) 32 bit supervisor stack pointer (SSP) 32 bit vector base register (VBR) 32 bit CPU configuration register (CPUCR) Do NOT try to memorise this!

103 ARM AArch64 has a total of 37 registers 31 general purpose / user visible registers 6 internal (system) registers Mostly 32 bits each, depends on mode 16 User visible registers at once 7 modes of operations: User: normal execution mode System: OS system privilege mode FIQ: data transfer mode Supervisor: SVC Abort: abort instruction IRQ: general purpose interrupt services Undefined: when unintended instructions are executed Do NOT try to memorise this!

104 main() { int a,b,c[50]; b = 2; for( a= 0; a < 50; a++) c[a] = a * b; } You re not expected to learn ARM assembler from this lecture by the way! This shows Register use R0 R1.L3:.L2: mov r3, #2 str r3, [fp, # 16] mov r3, #0 str r3, [fp, # 20] b.l2 ldr r1, [fp, # 20] ldr r2, [fp, # 20] ldr r3, [fp, # 16] mul r0, r3, r2 mvn r2, #207 mov r3, r1, asl #2 sub r1, fp, #12 add r3, r3, r1 add r3, r3, r2 str r0, [r3, #0] ldr r3, [fp, # 20] add r3, r3, #1 str r3, [fp, # 20] ldr r3, [fp, # 20] cmp r3, #49 ble.l3 sub sp, fp, #12 ldmfd sp, {fp, sp, pc}

105 CPU I/O Computer System bus Memory CPU Registers Internal Interconnects Arithmetic and Logic Units Control Unit

106 Fetch next instruction Decode instruction Execute instruction Simplified view

107 Load PC address into Stack

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112 Fetch Decode Execute (Pre )Fetch Decode Execute Instr. N Instr. N+1

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114 Detailed data flow

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116 Instruction 3 caused a branch to 15 write Instructions 4 7 have stalls read

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119 Prefetch the branch instructions and store somewhere non conflicting

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121 Do not prefetch after branch

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123 Time (clock cycles) Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 I n s t r. O r d e r Load Instr 1 Instr 2 Instr 3 Instr 4 Ifetch Reg Ifetch ALU Reg Ifetch DMem ALU Reg Ifetch Reg DMem ALU Reg Ifetch Reg DMem ALU Reg Reg DMem ALU Reg DMem Reg Needs careful processor pipeline design with appropriate arbitration between streams (eg. skip the cycle 4)

124 Without pipelining, cycles per instruction (CPI) is equal to the number of stages in Data Flow; assuming each stage requires 1 cycle (= Ideal CPI x Pipeline depth) CPI: Cycles per instruction For simple pipeline, ideal CPI = 1: Clock rates

125 remember LOADs are problematic 0 loads Would you pay for a double port DRAM system or not?

126 ARM7TDMI 3 stage pipeline Instruction Fetch Thumb ARM decompress ARM decode Reg Select Reg Read Shift ALU Reg Write FETCH DECODE EXECUTE ARM9TDMI 5 stage pipeline Instruction Fetch ARM or Thumb Inst Decode Reg Decode Reg Read Shift + ALU Memory Access Reg Write FETCH DECODE EXECUTE MEMORY WRITE

127 Von Neumann Harvard CISC RISC CPU I/O Computer Registers Arithmetic and Logic Units System bus Memory CPU Internal Interconnects Control Unit

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130 Shared L1 Data/Instruction Cache typical in modern systems

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132 CISC: complex instruction set computer RISC: reduced instruction set computer Berkeley group coined the term RISC and made a cpu called RISC 1 soon after Stanford made a similar cpu: MIPS SPARC also emerged from SUN ARM has a range of RISC architectures early RISC CPUs had about 50 instructions compared to aim was to simplify CPU to process (and start) instructions faster

133 RISC: Reduced Instruction Set Computer (e.g. ARM) MIPS example: add $rd, $rs, $rt B B B B B 10 6 B 5 0 opcode register s register t register d shift amount function

134 CISC: Complex Instruction Set Computer (e.g. Intel Pentium)

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ARM Processors for Embedded Applications

ARM Processors for Embedded Applications Roadmap for ARM Processors ARM Architecture Basics ARM Families AMBA Architecture 1 Current ARM Core Families ARM7: Hard cores and Soft cores Cache with MPU or