CSE 502 Graduate Computer Architecture

Transcription

1 Computer Architecture A Quantitative Approach, Fifth Edition CAQA5 Chapter 1 CSE 502 Graduate Computer Architecture Lec Introduction Fundamentals of Quantitative Design and Analysis Larry Wittie Computer Science, StonyBrook University and ~lw 1

2 Administrivia Location: Light Engineering, Room 152 Time: 2:20-3:40PM Tuesday/Thursday Textbook: Computer Architecture: A Quantitative Approach, Hennessy and Patterson, 5th Edition (CAQA5, H+P); Elsevier/Morgan-Kaufmann (Sept 2011, "2012"), paperback, ISBN Instructor: Professor Larry Wittie Office/Lab: CompSci Building, Room 1308 Office Hrs: :30pm Tu/Th or when 1308 door open Phone: lw AT icdotsunysbdotedu Homepage: CSE502 2

3 Grading 18% Homeworks (practice for the exams) 74% Exams {4% Quiz, 20% Midterm, 50% Final Exam} 8% (Optional) Research Project (work in pairs) You need to show initiative Pick a topic (more on this later) Give an oral presentation or poster session Written report like a conference paper Five weeks work full-time for two people Opportunity to do research in the small to make transition from undergrad student to research colleague I may add up to 3% to a final score just below that for a higher grade, a bonus usually only for people showing marked improvement during the progress of the course. CSE502 3

4 Computer Technology Performance improvements: Improvements in semiconductor technology Feature size, clock speed Improvements in computer architectures Enabled by HLL compilers, UNIX Lead to RISC architectures Introduction Together have enabled: Lightweight computers Productivity-based managed/interpreted programming languages 4

5 Single Processor Performance Move to multi-processors multi-cores Introduction RISC Figure 1.1 Growth in processor performance since This chart plots performance relative to the VAX 11/780, as measured by the SPEC benchmarks. Before 1986, processor performance growth of 25% per year was largely technology driven. The increase in growth to 52% after 1986 is attributable to more advanced architectural ideas, ideas which increased performance another 25 times by Since 2003, limits on power and instruction-level parallelism have slowed uniprocessor growth to 22% per year. 5

6 Current Trends in Architecture Could not continue to leverage instruction-level parallelism (ILP) and faster processor clock rates No more automatic speedup of uniprocessor programs Single processor performance growth ended in 2003 Introduction New models for performance: Data-level parallelism (DLP) graphics processing units Thread-level parallelism (TLP) mixed instruction streams Request-level parallelism (RLP) distinct Google queries These require explicit restructuring of the application Explicitly parallel programs harder to code & debug 6

7 Classes of Computers Personal Mobile Device (PMD) e.g. smart phones, tablet computers Emphasis on energy efficiency and real-time response Desktop Computing Emphasis on price-performance and graphics capability Servers Emphasis on availability, scalability, throughput Clusters / Warehouse Scale Computers Used for Software as a Service (SaaS) Emphasis on availability, price-performance, and energy/calculation Sub-class: Supercomputers, emphasis: floating-point performance and fast internal networks Embedded Computers Emphasis: price Classes of Computers 7

8 Parallelism Classes of parallelism in applications: Data-Level Parallelism (DLP) Repeat code, much data Task-Level Parallelism (TLP) Many distinct routines Think of a bureaucracy of clerks working semi-independently Classes of Computers Classes of architectural parallelism: Instruction-Level Parallelism (ILP) instruction pipelines Vector architectures/graphics Processor Units (GPUs) Thread-Level Parallelism instructions from a few codes Request-Level Parallelism many independent jobs 8

9 Flynn s Taxonomy Single instruction stream, single data stream (SISD) Uniprocessors, single processor computers Single instruction stream, multiple data streams (SIMD) Vector architectures Multimedia extensions Graphics processor units Classes of Computers Multiple instruction streams, single data stream (MISD) No commercial implementation (early image processing pipelines) Multiple instruction streams, multiple data streams (MIMD) Tightly-coupled MIMD rapidly exchange data between processors Loosely-coupled MIMD execute many instructions before exchange Grain-size time spent usefully computing/time idle waiting for data 9

10 Defining Computer Architecture Old view of computer architecture: Instruction Set Architecture (ISA) design i.e. decisions regarding: registers, memory addressing, addressing modes, instruction operands, available operations, control flow instructions, instruction encoding Modern computer architecture: Specific requirements of the target machine Design to maximize performance within constraints: cost, power, and availability (part of time system OK) Includes ISA, microarchitecture (registers & busses), hardware (peripheral devices), and technology (circuit components) Defining Computer Architecture 10

11 Technology Improvement Trends Integrated circuit technology Transistor density: 35%/year Die size: 10-20%/year Integration overall: 40-55%/year Trends in Technology Memory (DRAM) capacity: 25-40%/year (slowing) Flash drive (solid-state disk ) capacity: 50-60%/year 15-20X cheaper/bit than DRAM Magnetic disk technology: 40%/year 15-25X cheaper/bit then Flash X cheaper/bit than DRAM 11

12 Bandwidth and Latency Bandwidth or throughput Total work finished in a given time period 10,000-25,000X improvement for networks and processors in 30 years X improvement for memory and disks Trends in Technology Latency or response time Time between start and completion of an event 30-80X improvement for networks and processors 6-8X improvement for memory and disks 12

13 Bandwidth and Latency Trends in Technology Log-log plot of bandwidth and latency milestones 13

14 Transistors and Wires Feature size Minimum size of transistor or wire in x or y dimension 10 microns in 1971 to.032 microns in 2011 (300x) Transistor performance scales linearly Wire delay does not improve with feature size! Integration density scales quadratically Intel ,000 transisters/80286 (in first IBM PCs) Intel ,170,000,000/core i7 (4 cores/chip today) Trends in Technology 14

15 Power and Energy Problem: Get power in, get power out Thermal Design Power (TDP) Characterizes sustained power consumption Used as target for power supply and cooling system Lower than peak power, higher than average power consumption Trends in Power and Energy Clock rate can be reduced dynamically to limit power consumption Energy per task is often a better measurement 15

16 Dynamic Energy and Power Dynamic energy Transistor switch from 0 -> 1 or 1 -> 0 ½ x Capacitive load x Voltage 2 Dynamic power ½ x Capacitive load x Voltage 2 x Frequency switched Maximum_Frequency/Voltage roughly constant Dynamic power varies as Frequency 3 (near max freq.) (Processing speed of same chip)/frequency almost constant Slower clock rate directly reduces power, not energy But less power (V 3 ) and less energy (V 2 ) if lower voltage Lower voltage => lower max frequency & processor speed Multi-cores at lower voltage => more calculations/energy E=P*T, F 4 =F/2, V 4 =V/2, P 4 = 4*P/8=P/2, T 4 >=2*T/4=T/2, E 4 =P*T/4=E/4 Trends in Power and Energy 16

17 Power Intel consumed ~ 2 W of power 3.3 GHz Intel Core i7 consumes 130 W (33 W / core) Heat must be dissipated from chip of 15 x 15 mm This is at limit of what can be cooled by air Trends in Power and Energy 17

18 Reducing Power Techniques for reducing power: Do nothing well Dynamic Voltage-Frequency Scaling Low power state for DRAM, disks Overclocking, turning off cores Trends in Power and Energy 18

19 Static Power Static power consumption Current static x Voltage Scales with number of transistors To reduce: power gating to logic sections Trends in Power and Energy 19

20 Trends in Cost Cost driven down by learning curve Yield: fraction of dies that make working chips Trends in Cost DRAM: price closely tracks cost Microprocessors: price depends on volume 10% less for each doubling of volume 20

21 Intel Core i7 Die Intel Core i7 Figure 1.13 Photograph of a quad-core Intel Core i7 microprocessor die in a 45 nm process. Dimensions are 18.9 mm by 13.6 mm (257 mm 2 ). (From Intel) 21

22 Intel Core i7 Die Intel Core i7 Figure 1.13a Die floorplan of a quad-core x out-of-order quad-issue Intel Core i7 microprocessor with 1.17 billion (10 9 ) transistors and 8 MB L3 cache. 22

23 Intel Core i7 Die Floorplan Intel Core i7 Figure 1.14 Floorplan of Core i7 die in Figure 1.13 on left, with close-up of floorplan of second core on right. 23

24 Intel 300 mm Wafer with 280 Dies 300 mm Wafer Figure 1.15 This 300 mm wafer contains 280 full Sandy Bridge dies, each 20.7 by 10.5 mm in a 32 nm process. (Sandy Bridge is Intel s successor to Nehalem used in the Core i7.) At 216 mm 2, the formula for dies per wafer estimates 282. (Courtesy Intel.) 24

25 Integrated Circuit Cost Integrated circuit Trends in Cost ( # dies by area - # dies cut by edge ) Bose-Einstein formula: Defects per unit area = defects per square cm (2010) N = process-complexity factor = (40 nm, 2010) Note: older processors with fewer critical steps, formula had lower N and defects for each layer were summed to count defects per unit area. For 64-bit 2005 AMD Opteron, with only 4 (= 4) critical masking steps: 25

26 Dependability Module reliability Mean time to failure (MTTF) Mean time to repair (MTTR) Mean time between failures (MTBF) = MTTF + MTTR Availability = MTTF / MTBF Easy way to calculate system MTTF by adding FITs: Add Failures In Time (10 9 hours) of all parts (if failures independent) (FIT = 10 9 /MTTF for 1 billion hours) Independent failures imply sum of component FITs = system FIT MTTF for system = 10 9 /FIT for system Dependability 26

27 Measuring Performance Typical performance metrics: Response time Throughput Speedup of X relative to Y Execution time Y / Execution time X Example: time Y / time X = 150 sec / 100 sec => speedup of x over y = 1.5 or X is 1.5 times faster than Y or X is 50% faster than Y never slower The Speedup = mushroom : The BIG Time the little time Execution time Wall clock time: includes all system overheads CPU time: only computation time Measuring Performance Benchmarks Kernels (e.g. matrix multiply) Toy programs (e.g. sorting) Synthetic benchmarks (e.g. Dhrystone) Benchmark suites (e.g. SPEC CPU2006 [12: Cint2006, 17: Cfp2006], TPC-C) 27

28 Principles of Computer Design Take Advantage of Parallelism e.g. multiple processors, disks, memory banks, pipelining, multiple functional units Principles Principle of Locality Reuse of data and instructions (from caches) Focus on the Common Case Amdahl s Law Speedup = 1/Sum{ (Fractions Old_Time Shortened by R j )/R j } 28

29 Principles of Computer Design The Processor Performance Equation Principles 29

30 Principles of Computer Design Different instruction types having different CPIs Principles 30