Evaluation Board for CS4340 and CS4341

Transcription

1 Features Evaluation Board for CS0 and CS l Demonstrates recommended layout and grounding arrangements l CS8 Receives AES/EBU, S/PDIF, & EIAJ-0 Compatible Digital Audio l Digital and Analog Patch Areas l Requires only a digital signal source and power supplies for a complete Digital-to- Analog-Converter system Description The evaluation board is an excellent means for quickly evaluating the CS0/ family of -bit, stereo D/A converters. Evaluation requires an analog signal analyzer, a digital signal source, a PC for controlling the CS and a power supply. Analog outputs are provided via RCA phono jacks for both channels. The CS8 digital audio receiver I.C. provides the system timing necessary to operate the Digital-to-Analog converters and will accept AES/EBU, S/PDIF, and EIAJ- 0 compatible audio data. The evaluation board may also be configured to accept external timing signals for operation in a user application during system development. ORDERING INFORMATION CDB0, CDB Evaluation Board I/O for Clocks and Data Control Port Mute Circuit CS8 Digital Audio Interface CS0/ Analog Filter Preliminary Product Information This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. P.O. Box 787, Austin, Texas (5) 5 7 FAX: (5) Copyright Cirrus Logic, Inc. 999 (All Rights Reserved) NOV 99 DS97DB

2 TABLE OF CONTENTS. SYSTEM OVERVIEW.... CS0/ DIGITAL TO ANALOG CONVERTER.... CS8 DIGITAL AUDIO RECEIVER.... CS8 DATA FORMAT ANALOG OUTPUT FILTER INPUT/OUTPUT FOR CLOCKS AND DATA POWER SUPPLY CIRCUITRY GROUNDING AND POWER SUPPLY DECOUPLING CDB CONTROL PORT SOFTWARE... LIST OF FIGURES LIST OF TABLES Figure. System Block Diagram and Signal Flow... 8 Figure. CS0/... 9 Figure. Analog Output Passive Filter... 0 Figure. External Mute Circuit... Figure 5. CS8 Digital Audio Receiver Connections... Figure 6. Digital Audio Inputs... Figure 7. MCLK Divider and Voltage Level Converter... Figure 8. Control Port Interface... 5 Figure 9. Reset Circuitry... 6 Figure 0. Power Supply... 7 Figure. I/O for Clocks and Data... 8 Figure. Silkscreen Top... 9 Figure. Top Side... 0 Figure. Bottom Side... Table. CS8 Supported Formats... Table. System Connections... 5 Table. CDB0 Jumper Selectable Options... 5 Table. CDB (IC Mode) Jumper Selectable Options... 6 Table 5. CDB (SPI Mode) Jumper Selectable Options... 7 Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: I C is a registered trademark of Philips Semiconductors. Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided AS IS without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at DS97DB

3 . SYSTEM OVERVIEW The evaluation board is an excellent means of quickly evaluating the CS0/. The CS8 digital audio interface receiver provides an easy interface to digital audio signal sources including the majority of digital audio test equipment. The evaluation board also allows the user to supply clocks and data through a 0-pin header for system development. The schematic has been partitioned into 0 schematics shown in Figures through. Each partitioned schematic is represented in the system diagram shown in Figure. Notice that the the system diagram also includes the interconnections between the partitioned schematics.. CS0/ DIGITAL TO ANALOG CONVERTER A description of the CS0 is included in the CS0 data sheet. A description of the CS is included in the CS data sheet.. CS8 DIGITAL AUDIO RECEIVER The system receives and decodes the standard S/PDIF data format using a CS8 Digital Audio Receiver, Figure. The outputs of the CS8 include a serial bit clock, serial data, left-right clock (FSYNC), de-emphasis control and a 56 Fs master clock. The operation of the CS8 and a discussion of the digital audio interface are included in the CS8 Datasheet. During normal operation, the CS8 operates in the Channel Status mode where the LED s display channel status information for the channel selected by the CSLR/FCK jumper. This allows the CS8 to decode the de-emphasis bit from the digital audio interface for control of the CS0 de-emphasis filter. When the Error Information Switch is activated, the CS8 operates in the Error and Frequency information mode. The information displayed by the LED s can be decoded by consulting the CS8 data sheet. It is likely that the de-emphasis control for the CS0 will be erroneous and produce an incorrect audio output if the Error Information Switch is activated and the CS0 is in the internal serial clock mode. Encoded sample frequency information can be displayed provided a proper clock is being applied to the FCK pin of the CS8. When an LED is lit, this indicates a "" on the corresponding pin located on the CS8. When an LED is off, this indicates a "0" on the corresponding pin. Neither the L or R option of CSLR/FCK should be selected if the FCK pin is being driven by a clock signal. The evaluation board has been designed such that the input can be either optical or coax (see Figure 6). However, both inputs cannot be driven simultaneously.. CS8 DATA FORMAT The CS8 data format can be set with jumpers M0, M, M, and M, as described the CS8 datasheet. The format selected must be compatible with the data format of the CS0 or CS, shown in the CS0 and CS datasheets. Please note that the CS8 does not support all the possible modes of the CS0 or CS, see Table for details. The default settings for M0-M on the evaluation board are given in Tables -5. CS CS0 CS8 External Internal Format Format Format SCLK SCLK 0 - Yes Yes 0 Yes No 0 No Yes Unsupported Unsupported Yes No 6-6 Yes Yes 7 0 Yes No Table. CS8 Supported Formats DS97DB

4 5. ANALOG OUTPUT FILTER The evaluation board includes a pair of single pole passive filters. The passive filters, Fig., have a corner frequency of approximately 95 khz with JP and JP6 installed and 90 khz without JP and JP6. 6. INPUT/OUTPUT FOR CLOCKS AND DATA The evaluation board has been designed to allow the interface to external systems via the 0-pin header, J9. This header allows the evaluation board to accept externally generated clocks and data. The schematic for the clock/data I/O is shown in Figure. The 7HC transceiver functions as an I/O buffer where jumpers HDR-HDR6 determine if the transceiver operates as a transmitter or receiver. A transmit function is implemented with the HDR-HDR6 jumpers in the 8 position. LRCK, SDATA, and SCLK from the CS8 will be outputs on J9. The transceiver operates as a receiver with jumpers HDR-HDR6 in the EXTER- NAL position. MCLK, LRCK, SDATA and SCLK on J9 become inputs. 7. POWER SUPPLY CIRCUITRY Power is supplied to the evaluation board by three binding posts (, +5V, +V/+5V) (see Figure 0). The +5V input supplies power to the +5 Volt digital circuitry (VA+5,, VDPC+5), while the +V/+5V input supplies power to the Voltage Level Converter and the CS0/ for evaluation in either + or +5 Volt mode. Note, the supply voltages, VCCA and VCCB, to the Voltage Level Converter (LVXC5) must remain within.5 Volts of each other in order to maintain proper operation. 8. GROUNDING AND POWER SUPPLY DECOUPLING The CS0/ requires careful attention to power supply and grounding arrangements to optimize performance. Figure 0 details the power distribution used on this board. The ground plane is split to control the digital return currents in order to minimize digital interference. The decoupling capacitors are located as close to the CS0/ as possible. Extensive use of ground plane fill on both the analog and digital sections of the evaluation board yields large reductions in radiated noise. 9. CDB CONTROL PORT SOFTWARE The CDB is shipped with Windows based software for interfacing with the CS control port via the DB5 connector, P. The software can be used to communicate with the CS in either SPI or I C mode; however, in SPI mode the CS registers are write-only. Run SETUP.EXE from the distribution diskette to install the software. Further documentation for the software is available on the distribution diskette. The documentation is available in the plain text format file, README.TXT. DS97DB

5 CONNECTOR INPUT/OUTPUT SIGNAL PRESENT +5 V input + 5 Volt power +V/+5V input + Volt or + 5 Volt power for the CS0/ and the Voltage Level Converter input ground connection from power supply Digital input input digital audio interface input via coax Optical input input digital audio interface input via optical J9 input/output I/O for master, serial, left/right clocks and serial data Parallel Port input/output parallel connection to PC for SPI/I C control port signals Control I/O input/output I/O for SPI/I C control port signals AOUTA output channel A analog output with single-pole passive filter AOUTB output channel B analog output with single-pole passive filter Table. System Connections JUMPER PURPOSE POSITION FUNCTION SELECTED CSLR/FCK Selects channel for CS8 HI See CS8 Datasheet for details channel status information *LO M0 M M M CS8 mode selection *Low *High *Low *Low SCLK Selects SCLK Mode INT *EXT DEM_8 HDR-6 HDR 7 HDR 8 MCLK Selects source of de-emphasis control Selects source of clocks and audio data Enables the external mute for AOUTA Enables the external mute for AOUTB Selects High-Rate or Base-Rate Modes *8 DEM *8 EXT *ON OFF *ON OFF *x HDR5 DIF HI *LOW HDR6 DIF0 HI *LOW HDR7 DEM0 HI *LOW ENCTRL Enables/Disables parallel port Enable *Disable See CS8 Datasheet for details Internal SCLK Mode External SCLK Mode CS8 de-emphasis De-emphasis input static low Selects CS8 as source Digital I/O header becomes an source Mute Enabled Mute Disabled Mute Enabled Mute Disabled Selects Base-Rate Mode Selects High-Rate Mode See CS0 Datasheet for details See CS0 Datasheet for details See CS0 Datasheet for details Invalid for CS0 Disables parallel port *Default setting from factory Table. CDB0 Jumper Selectable Options DS97DB 5

6 JUMPER PURPOSE POSITION FUNCTION SELECTED CSLR/FCK Selects channel for CS8 HI See CS8 Datasheet for details channel status information *LO M0 M M M CS8 mode selection *Low *High *Low *Low SCLK Selects SCLK Mode INT *EXT DEM_8 HDR-6 HDR 7 HDR 8 MCLK Selects source of de-emphasis control Selects source of clocks and audio data Enables the external mute for AOUTA Enables the external mute for AOUTB Selects High-Rate or Base-Rate Modes *8 DEM *8 EXT *ON OFF *ON OFF *x HDR5 SCL Pull-Up *HI LOW HDR6 SDA Pull-Up *HI LOW HDR7 AD0 HI *LOW ENCTRL Enables/Disables parallel port *Enable Disable See CS8 Datasheet for details Internal SCLK Mode External SCLK Mode Don t Care for CS Selects CS8 as source Digital I/O header becomes an source Mute Enabled Mute Disabled Mute Enabled Mute Disabled Selects Base-Rate Mode Selects High-Rate Mode SCL pulled high Invalid for I C mode SDA pulled high Invalid for I C mode Don t Care for Control Port Mode Enables parallel port Disables parallel port (must use HDR) *Default setting from factory Table. CDB (I C Mode) Jumper Selectable Options Notes: The CDB evaluation board is shipped from the factory configured for I C mode. 6 DS97DB

7 JUMPER PURPOSE POSITION FUNCTION SELECTED CSLR/FCK Selects channel for CS8 HI See CS8 Datasheet for details channel status information *LO M0 M M M CS8 mode selection *Low *High *Low *Low SCLK Selects SCLK Mode INT *EXT DEM_8 HDR-6 HDR 7 HDR 8 MCLK Selects source of de-emphasis control Selects source of clocks and audio data Enables the external mute for AOUTA Enables the external mute for AOUTB Selects High-Rate or Base-Rate Modes *8 DEM *8 EXT *ON OFF *ON OFF *x HDR5 CCLK Pull-up or Pull-down *HI LOW HDR6 CDIN Pull-up or Pull-down *HI LOW HDR7 CS Pull-up HI *LOW ENCTRL Enables/Disables parallel port *Enable Disable See CS8 Datasheet for details Internal SCLK Mode External SCLK Mode Don t Care for CS Selects CS8 as source Digital I/O header becomes an source Mute Enabled Mute Disabled Mute Enabled Mute Disabled Selects Base-Rate Mode Selects High-Rate Mode Don t Care for SPI mode Don t Care for SPI mode Don t Care for Control Port Mode Enables parallel port Disables parallel port (must use HDR) *Default setting from factory Table 5. CDB (SPI Mode) Jumper Selectable Options Notes: When in SPI mode, it is not possible to read the control registers of the CS. The CDB evaluation board is shipped from the factory configured for I C mode. DS97DB 7

8 I/O for Clocks and Data Fig Control Port Interface Fig 8 Digital Audio Input Fig 6 RXN RXP CS8 Digital Audio Receiver Connections Fig 5 MCLK Voltage MCLK LRCK Level LRCK CS0/ SCLK Converter SCLK SDATA SDATA Fig Fig 7 Reset Circuit Fig 9 Passive Analog Filter Fig External Mute Circuit Fig Figure. System Block Diagram and Signal Flow 8 DS97DB

9 DS97DB 9 ARP X7R C5.UF R R X7R.UF C7 TP5 MUTEC FERRITE_BEAD L TP R0 99 R R R 9.9 SDATA-A DEM/SCLK-A LRCK-A MCLK-A DIF0/SDA/CDIN 0UF C C.UF ALP C.UF X7R C.UF VA+/+5 MUTEC C UF C0 UF RST /RST SDATA SCLK LRCK MCLK SDA/CDIN AD0//CS MUTEC AOUTA VA AOUTB SCL/CCLK REF_ VCOM FILT CS_KS U7 CS DIF/SCL/CCLK-A DEM0/AD0/CS-A Figure. CS0/

10 0 DS97DB MUTEA ALP MUTEB ARP R8 0K R9 0K R8 HDRX HDR7 560 C8 500PF COG HDRX HDR8 R7 560 C 500PF COG JP JP6 C6 500PF COG C5 500PF COG Figure. Analog Output Passive Filter J CON_RCA_RA NC J CON_RCA_RA NC AOUTLP A AOUTRP B

11 DS97DB MUTEC Q MMUNLT VA+/+5 MMUNLT Q R5 R Figure. External Mute Circuit K K Q SC878 MUTEA MUTEB Q SC878

12 DS97DB RXP RXN CSLR/FCK INT/EXT SCLK ERROR & FREQ SCLK DEM/SCLK 8_DEM TP0 INT EXT DEM M0 M M CSLR/FCK D LED_RECT 560 RN CSLR/FCK VCC U8 SN7HC0N D LED_RECT LED_RECT D LED_RECT D6 LED_RECT D5 LED_RECT D VERF CE/F SDATA ERF M M0 VA+ FILT MCK M M CBL SEL U CS/FCK SCK FSYNC RXN RXP D VD+ /C0/E0 CA/E CB/E CC/F0 CD/F C CS8 U HDR HDRX LRCK HDRX HDR SDATA SCLK HDRX HDR 0 R VD HDR HDRX HDR5 HDRX MCLK VA VD S SW_BW_00 CS8_M0 CS8_M 8_M 8 VA+5 C6.UF 0UF C X7R C7.UF X7R.UF C6 HDRX M0 M HDRX HDRX M M HDRX HDRX CSLR/FCK 8_DEM HDRX EXT_INT_SCLK HDRX VA 70 R9 CS8_M X7R.068UF C 7.5K R7 VD 7.5K R6 UF C UF C 8_DEM Figure 5. CS8 Digital Audio Receiver Connections

13 DS97DB NC DIGITAL INPUT J5 CON_RCA_RA R0 75 C.0UF RXN 6 5 Figure 6. Digital Audio Inputs OPT TORX7 OPTICAL INPUT C9.0UF C0.0UF L 7UH RXP

14 DS97DB VA+/+5 /SET CLOCK DATA /RST /SET CLOCK DATA /RST VCC Q /Q Q /Q MC7HC7AN U MCLK J0 HDRX MCLK HRM BRM C5.UF SDATA-A DEM/SCLK-A LRCK-A MCLK-A DIF/SCL/CCLK-A DEM0/AD0/CS-A SDATA DEM/SCLK LRCK DIF/SCL/CCLK DEM0/AD0/CS MCLK-B.UF C B8 B7 B6 B5 B B B B VCC A8 A7 A6 A5 A A A A DIR /G SN7VHC5DW U5 Figure 7. MCLK Divider and Voltage Level Converter

15 DS97DB 5 VDPC+5 DIF0/SDA/CDIN HDR8 HDRX HDRX HDR R K HDR7 HDRX R K R0 K HDRX HDR6 R K K R9 R K R8 K R K K R R K DB5M_RA P 8Q 7Q 8D 7D VCC Q Q Q Q 5Q 6Q 6D 5D D D D D CLK /OC SN7HC57N U LATCH ENCTRL VDPC+5 C.UF C7.UF HDR5 HDRX R6 K ENCTRL VDPC+5 PC0 DIF0/SDA/CDIN VDPC+5 VA+/+5 DIF/SCL/CCLK DEM0/AD0/CS VDPC+5 LATCH VCC 7 SN7HCT5N U6 U6 SN7HCT5N 6 5 U6 SN7HCT5N SN7HCT5N U6 DIF/SCL/CCLK DEM0/AD0/CS K R5 Figure 8. Control Port Interface

16 VA+/+5 R 00K BAT85 D7 RST 00 C9.UF SW_BW_00 S R7 Figure 9. Reset Circuitry 6 DS97DB

17 DS97DB 7 C8 0UF C9.UF VA+5 VDPC+5 L FB +5V CON_BANANA J6 Z P6KE6V8P C5 L FB C 7UF C 7UF.UF CON_BANANA J7 Figure 0. Power Supply P6KE6V8P C Z C 7UF +V/+5V.UF CON_BANANA J VA+/+5

18 8 DS97DB MCLK SCLK LRCK SDATA C.UF B B B B U 7HC VCC A A A A GBA /GAB 6 5 Figure. I/O for Clocks and Data J9 HDR5X DIGITAL I/O HDRX HDR6 8 EXTERNAL CLK SOURCE MCLK SCLK LRCK SDATA

19 Figure. Silkscreen Top DS97DB 9

20 Figure. Top Side 0 DS97DB

21 Figure. Bottom Side DS97DB

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