HDMI To HDTV Converter

Transcription

1 Chrontel AN-B0 Application Notes P C B L ayout and Desig n Guide for CH7 03B HDMI To HDTV Converter.0 INTRODUCTION The CH703B is a low-cost, low-power semiconductor device, which can convert HDMI signals into HDTV outputs with IIS or SPDIF audio output. This application note focuses only on the basic PCB layout and design guidelines for CH703B Converter. Guidelines in component placement, power supply decoupling, grounding, input /output signal interface are discussed in this document. The discussion and figures that follow reflect and describe connections based on the 40-pin QFN package of the CH703B. Please refer to the CH703B datasheet for the details of the pin assignments..0 COMPONENT PLACEMENT AND DESIGN CONSIDERATIONS Components associated with the CH703B should be placed as close as possible to the respective pins. The following discussion will describe guidelines on how to connect critical pins, as well as describe the guidelines for the placement and layout of components associated with these pins.. Power Supply Decoupling The optimum power supply decoupling is accomplished by placing a 0.μF ceramic capacitor to each of the power supply pins as shown in Figure. These capacitors (C, C, C4, C, C7, C9, C0, C) should be connected as close as possible to their respective power and ground pins using short and wide traces to minimize lead inductance. Whenever possible, a physical connecting trace should connect the ground pins of the decoupling capacitors to the CH703B ground pins, in addition to ground vias... Ground Pins The grounds of the CH703B should be connected to a common ground plane to provide a low impedance return path for the supply currents. Whenever possible, each of the CH703B ground pins should be connected to its respective decoupling capacitor ground lead directly, then connected to the ground plane through a ground via. Short and wide traces should be used to minimize the lead inductance. Refer to Table for the Ground pins assignment... Power Supply Pins The power supply includes VDDPLL,,, _DAC, and AVDD. Refer to Table for the Power supply pins assignment. Refer to Figure for Power Supply Decoupling. Table : Power Supply Pins Assignment of the CH703B (QFN) Rev.0. 0//04

2 CHRONTEL AN-B0 Pin Assignment # Of Pins Type Symbol Description Power VDDPLL PLL Power Supply (.V), Power Digital supply voltage (.V) 3, 9 D Digital Ground, 3 Power Analog supply voltage (3.3V) 4, 7 Power _DAC DAC power supply (.5V~3.3V) 35 Power AVDD HDMI receiver power supply (.V) Thermal pad Ground Power supply ground QFN U D AVDD VDDPLL Thermal Pad _DAC, 3, , 3 4,7 C C 0.uF 0.uF C4 0.uF C 0.uF C3 0uF C5 0uF C C7 C 0.uF 0.uF0uF C9 0.uF C0 0.uF C3 0uF C 0uF 47R 00MHz L 47R 00MHz L5 47R 00MHz L 47R 00MHz L3 47R 00MHz L4 VCC_ CH703B Figure : Power Supply Decoupling and Distribution Note: All the Ferrite Beads described in this document are recommended to have an impedance of less than 0.05 at 5MHz & 47 at 00MHz. Please refer to Fair Rite part # for details or an equivalent part can be used for the diagram.. Internal Reference Pins RBIAS pin This pin sets the DAC current. A 0 KΩ, % tolerance resistor should be connected between RBIAS and as shown in Figure. A smaller resistance will create more DAC current. This resistor should be placed with short and wide traces as near as possible to CH703B. U RBIAS 9 QFN R 0K(%) Thermal Pad 4 CH703B Figure : RBIAS pin connection Rev.0. 0//04

3 CHRONTEL.3 General Control Pins AN-B0 RB This pin is the chip reset pin for CH703B, which is internally pulled-up, places the device in the power on reset condition when this pin is low. A power-reset switch can be placed on the RB pin on the PCB as a hardware reset for CH703B as shown in Figure 3. When the pin is high, the reset function can also be controlled through the serial port. U RB 0 RB R M SW P05SS-ND C 0.uF CH703B Figure 3: RB pin connection GPIO [:0] These pins are general-purpose input/output. Refer to reference schematic..4 Serial Port Control for CH703B SPC0 and SPD0 SPD0 and SPC0 function as a serial interface where SPD0 is bi-directional data and SPC0 is an input only serial clock. In the reference design, SPD0 and SPC0 pins are pulled up to +3.3V with.k resistors always as shown in Figure 4. and and are used to interface with the DDC of HDMI Source or transmitter and the serial PROM. This DDC pair needs to be pulled up to 5V through 47 KΩ resistors (Refer to Figure 4). U VDD5 R.K R.K QFN SPC0 SPD R3 47K R4 47K SPC0 SPD0 CH703B Figure 4: Serial Port Control.5 HDMI receiver Pins The,, RD [:0] P, RD [:0] N signals are high frequency differential signals that need to be routed with special precautions. Since those signals are differential, they must be routed in pairs Rev.0. 0//04 3

4 CHRONTEL AN-B0.5. Differential Pair Impedance To match the external cable impedance and maintain the maximal energy efficiency it is important to meet the impedance target of 00-Ω ± 0% for the differential data/clock traces. The restriction of this impedance target is to prevent any loss of signal strengths resulting from a reflection of unwanted signals. The impedance can be acquired by proper design of trace length, trace width, signal layer thickness, board dielectric, etc. The HDMI differential pairs should be routed on the top layer directly to the HDMI connector pads if possible..5. Trace Routing Length To prevent from capacitive and impedance loading, trace lengths should be kept as minimal as possible. Vias and bends should always be minimized; inductive effects may be introduced, causing spikes in the signals. Trace routing lengths from CH703B to the HDMI connector are limited to a maximum of inches. The CH703B should be as close to the HDMI connector as possible..5.3 Length Matching for Differential Pairs The HDMI specifies the intra-pair skew and the inter-pair skew as in Table. The intra-pair skew is the maximum allowable time difference on both low-to-high and high-to-low transitions between the true and complement signals. The inter-pair skew is the maximum allowable time difference on both low-to-high and high-to-low transitions between any two single-ended data signals that do not constitute a differential pair. Table : Maximum Skews for the HDMI Transmitter Skew Type Intra-Pair Skew Inter-Pair Skew Maximum at Transmitter 0.5 T bit 0.0 T Pixel Where T bit is defined as the reciprocal of Data Transfer Rate and T Pixel is defined as the reciprocal of Clock Rate. Therefore, T Pixel is 0 times T bit. In other words, the intra-pair length matching is much more stringent than the interpair length matching. It is recommended that length matching of both signals of a differential pair be within 5 mils. Length matching should occur on a segment-by-segment basis. Segments might include the path between vias, resistor pads, capacitor pads, a pin, an edge-finger pad, or any combinations of them, etc. Length matching from one pair to any other should be within 00 mils. Note that lengths should only be counted to the pins or pad edge. Additional etch within the edge-finger pad, for instance, is electrically considered part of the pad itself..5.4 ESD Protection for HDMI Interface In order to minimize the hazard of ESD, a set of protection diodes are highly recommended for each HDMI input (data and clock). International standard EN 5504:99 establishes 4kV as the common immunity requirement for contact discharges in electronic systems. kv is also established as the common immunity requirement for air discharges in electronic systems. International standard EN :995 / IEC :995 establishes the immunity testing and measurement techniques. System level ESD testing to International standard EN :995 / IEC :995 has confirmed that the proper implementation of Chrontel recommended diode protection circuitry, using BCD AT40 diode array devices, will protect the CH703B device from HDMI transmitter discharges of greater than 9kV (contact) and 0kV (air). The AT40 have a typical capacitance of only 0.50pF between I/O pins. This low capacitance won t bring too much bad effect on HDMI eye diagram test Rev.0. 0//04

5 CHRONTEL AN-B0 Figure5 (A) and (B) show the connection of HDMI connectors, including the recommended design of AT40 diode array devices. HDMI connector is used to connect the CH703B HDMI inputs from HDMI transmitter. U QFN RDN RDP RDN RDP RDN RDP RDN RDP CH703B Figure 5(A): The connection of the HDMI input J RDP RDN RDP RDN C0 AT40 0.uF U LINE NC NC LINE 3 3 LINE3 NC NC LINE4 U4 C 0uF LINE NC NC LINE 3 3 LINE3 NC NC LINE RDP RDN RDP RDN RDP RDN RDP RDN VDD5_0 RX+ RX_shld RX- RX+ RX_shld RX- RX0+ RX0_shld RX0- RXC+ RXC_shld RXC- CEC RESERVED SCL SDA DDC_ +5V HTPLUG HDMI_A AT40 D SM57 R5 k R R7 47K 47K D AZ55-0H D4 D5 AZ55-0H AZ55-0H HDMI input Figure 5(B): The connection of the HDMI inputs-ch703b HDMI connectors Rev.0. 0//04 5

6 CHRONTEL The following is the description for each HDMI interface pins HDMI Link Data Channel (RD [:0] P and RD [:0] N) AN-B0 These pins provide HDMI differential inputs for data channel 0 (blue), data channel (green) and data channel (red). (Refer to Figure 5 (A)). HDMI Link Clock Outputs ( and ) These pins provide the HDMI differential clock inputs for HDMI corresponding to data on the RD [:0] P and RD [:0] N inputs (Refer to Figure 5 (A)). (HDMI Hot Plug Detect) This output pin connects to the +5V power through a KΩ resistor. Refer to Figure 5 (B) for the design example.. HDTV Outputs DAC0~ HDTV (YPbPr) output Three on-chip 9-bit high speed DACs provide YPbPr (HDTV) output. If the DACs require a double termination, A resistor should be placed between each DAC pin and the ground as shown in Figure. (Refer to Figure ) DAC R DAC R9 DAC0 R0 C3 00pF C 00pF pf L 0.33uH C5 pf L9 0.33uH C L0pF 0.33uH C9 00pF C C4 7pF C7 7pF C30 7pF D3 AZ55-0H Y D Pr AZ55-0H D7 Pb CN JACK-RCA-P CN JACK-RCA-P CN3 JACK-RCA-P AZ55-0H Figure : CH703B YPbPr (HDTV) output.7 Audio Output Rev.0. 0//04

7 3 CHRONTEL IIS AN-B0 IIS audio output can be configured through programming CH703B registers. (Refer to Figure 7) SPDIF For SPDIF output, CH703B supports audio sample frequencies from 3Khz to 9kHz. (Refer to Figure 7) J HEADER 3 U SPDIF SD/SPDIF WS SCLK MCLK 7 9 IS DAC CH703B Figure 7: CH703B IIS or SPDIF Output Pins Rev.0. 0//04 7

8 GPIO GPIO0 RBIAS SPC0 SPD0 GPIO0 GPIO D SPC0 SPD0 GPIO0 GPIO NC NC D NC RDP RDN RDP RDN RDP RDN RDP RDN AVDD CHRONTEL AN-B0 3.0 REFERENCE DESIGN EXAMPLE The figures below are the reference schematic of CH703B, which is provided here for design reference only. Please contact Chrontel Applications group for further support. Table provides the BOM list for the reference schematic. 3. Reference Schematic VCC_ VCC_ C4 0uF R 453K R 00K C5 pf U 0 EN SW 9 3 FB C 4 VIN VIN 7 L5 4.7uF 5 FB SW EN.uH AT709 C 4.7uF L4.uH R3 C3 R4 00K pf 00K C 0uF VCC_ L L FB FB AVDD C5 0uF C 0uF C 0.uF C3 0.uF C4 0.uF VCC_ L L7 FB FB _DAC C 0uF C7 0uF C7 0.uF C 0.uF C 0.uF C9 0.uF L3 FB VDDPLL C9 0uF C0 0.uF Power of CH703B J RDP RX+ RDN 3 RX_shld RDP 4 RX- U 5 RX+ RDN RX_shld RDP RDP 7 RX- RDN LINE NC 0 9 RDN RX0+ 3 NC LINE 9 RX0_shld RDP RDP 0 RX0- RDN 5 LINE3 NC 7 RDN RXC+ NC LINE4 RXC_shld 3 RXC- Rclamp054 4 CEC 5 RESERVED SCL 7 SDA GPIO5V DDC_ 9 +5V C C0 0 HTPLUG 0uF 0.uF 3 U4 HDMI_A LINE NC NC LINE LINE3 NC 7 NC LINE4 Rclamp054 D SM57 R HDMI5 k R7 R HDMI input 47K 47K D AZ55-0H D VDDPLL D SD WS SCLK MCLK RB U3 VDDPLL D SD/SPDIF WS SCLK MCLK RB CH703B 3 AVDD 35 CH703B QFN40 30 RBIAS 9 DAC _DAC 7 DAC DAC0 5 _DAC 4 NC 3 NC NC RBIAS DAC _DAC DAC DAC0 _DAC U5 SD SCLK SDIN AOUTR 0 WS 3 SCLK VA 9 MCLK 4 LRCK 7 5 MCLK AOUTL VQ FILT + C C7 C5 0uF CS4344 0uF 0.uF Audio IS to L, R CHANNEL C C3 0uF C4 R5 7.5K 3.3uF 3.3uF J PJ R9 7.5K D3 D4 AZ55-0H AZ55-0H DAC C pf L Pr CN JACK-RCA-P R0 0.33uH C9 00pF C3 C30 7pF D5 AZ55-0H CN JACK-RCA-P DAC pf L9 Y SPC0 SPD0 R3.K R4.K GPIO5V R 0K R 0K R 47K R5 0K % R9 M R DAC0 R uh C3 C34 pf 00pF L uh C3 00pF C35 7pF C33 7pF D AZ55-0H Pb D7 AZ55-0H CN3 JACK-RCA-P RB Reserved C37 0.uF CH703B interface Rev.0. 0//04

9 CHRONTEL AN-B0 3. Reference Board Preliminary BOM Table 3: CH703B Reference Design BOM List Item Quantity Reference Part 3 CN, CN, CN3 RCA Jack C, C 4.7uF 3 C, C, C9, C, C4, C5, C7, C, C, C7 0uF 4 C3, C4, C7, C, C0, C, C, C9, C0, C5, C37 0.uF 5 C5, C3 pf 3 C, C3, C34 pf 7 3 C9, C3, C3 00pF 3 C30, C33, C35 7pF 9 C, C4 3.3uF 0 D SM57 D, D3, D4, D5, D, D7 AZ55-0H J HDMI_A 3 J PJ 4 5 L, L, L3, L, L7 FB 5 L4, L5.uH 3 L, L9, L0 0.33uH 7 R 453K 3 R, R3, R4 00K 9 R k 0 3 R7, R, R7 47K 3 R0, R5, R9 R, R3.K 3 R 0K 4 R4 0K % 5 R M R5, R9 7.5K 7 R 0K U AT709 9 U, U4 Rclamp U3 CH703B 3 U5 CS Rev.0. 0//04 9

10 CHRONTEL AN-B0 4.0 REVISION HISTORY Table 3: Revisions Rev. # Date Section Description 0. /4/0 All Initial release 0. 0//04 All Update for CH703B Rev.0. 0//04

11 CHRONTEL Disclaimer AN-B0 This document provides technical information for the user. Chrontel reserves the right to make changes at any time without notice to improve and supply the best possible product and is not responsible and does not assume any liability for misapplication or use outside the limits specified in this document. We provide no warranty for the use of our products and assume no liability for errors contained in this document. The customer should make sure that they have the most recent data sheet version. Customers should take appropriate action to ensure their use of the products does not infringe upon any patents. Chrontel, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such rights. Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used as directed can reasonably expect to result in personal injury or death. 04 Chrontel - All Rights Reserved. Chrontel Chrontel International Limited 9 Front Street, 5th floor, Hamilton, Bermuda HM sales@chrontel.com Rev.0. 0//04