PCB Layout and Design Guide for CH7102A HDMI to BT656 Converter with IIC Slave
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1 Chrontel AN-B07 Application Notes PCB Layout and Design Guide for CH70A HDMI to BT Converter with IIC Slave.0 INTRODUCTION The CH70A is a low-cost, low-power semiconductor device, which can convert HDMI signals into bits YCbCr :: outputs with IIS or SPDIF audio output. This application note focuses only on the basic PCB layout and design guidelines for CH70A Converter. Guidelines in component placement, power supply decoupling, grounding, input /output signal interface are discussed in this document. The discussion and figures that follow reflect and describe connections based on the 0-pin QFN package of the CH70A. Please refer to the CH70A datasheet for the details of the pin assignments..0 COMPONENT PLACEMENT AND DESIGN CONSIDERATIONS Components associated with the CH70A should be placed as close as possible to the respective pins. The following discussion will describe guidelines on how to connect critical pins, as well as describe the guidelines for the placement and layout of components associated with these pins.. Power Supply Decoupling The optimum power supply decoupling is accomplished by placing a 0.µF ceramic capacitor to each of the power supply pins as shown in Figure. These capacitors (C, C, C, C, C, C, C7) should be connected as close as possible to their respective power and ground pins using short and wide traces to minimize lead inductance. Whenever possible, a physical connecting trace should connect the ground pins of the decoupling capacitors to the CH70A ground pins, in addition to ground vias... Ground Pins The grounds of the CH70A should be connected to a common ground plane to provide a low impedance return path for the supply currents. Whenever possible, each of the CH70A ground pins should be connected to its respective decoupling capacitor ground lead directly, then connected to the ground plane through a ground via. Short and wide traces should be used to minimize the lead inductance. Refer to Table for the Ground pins assignment... Power Supply Pins The power supply includes VDDPLL, DVDD,, and AVDD. Refer to Table for the Power supply pins assignment. Refer to Figure for Power Supply Decoupling. Table : Power Supply Pins Assignment of the CH70A (QFN) Rev 0. //0
2 AN-B07 Pin Assignment # Of Pins Type Symbol Description Power VDDPLL PLL Power Supply (.V), Power DVDD Digital supply voltage (.V), 9 D Digital Ground,, Power Analog supply voltage (.V) Power AVDD HDMI receiver power supply (.V) Thermal pad Ground Power supply ground U QFN DVDD D VDDPLL Thermal Pad,, 9 AVDD,, C7 0.uF C 0.uF C 0uF C 0.uF C 0.uF C7 C 0uF 0uF C C 0.uF 0.uF C 0uF C 0.uF 7R 00MHz L 7R 00MHz L 7R 00MHz L 7R 00MHz L VCC_ VCC_ CH70A Figure : Power Supply Decoupling and Distribution Note: All the Ferrite Beads described in this document are recommended to have an impedance of less than 0.0 Ω at DC; Ω at MHz & 7 Ω at 00MHz. Please refer to Fair Rite part #7097 for details or an equivalent part can be used for the diagram.. Internal Reference Pins RBIAS pin This pin sets the DAC current. A 0 KΩ, % tolerance resistor should be connected between RBIAS and as shown in Figure. A smaller resistance will create more DAC current. This resistor should be placed with short and wide traces as near as possible to CH70A. U RBIAS 9 QFN R 0K(%) Thermal Pad CH70A Figure : RBIAS pin connection Rev 0. //0
3 . General Control Pins AN-B07 RB This pin is the chip reset pin for CH70A, which is internally pulled-up, places the device in the power on reset condition when this pin is low. A power-reset switch can be placed on the RB pin on the PCB as a hardware reset for CH70A as shown in Figure. When the pin is high, the reset function can also be controlled through the serial port. U RB 0 RB R M SW P0SS-ND C 0.uF CH70A Figure : RB pin connection. Serial Port Control for CH70A SPC0 and SPD0 SPD0 and SPC0 function as a serial interface where SPD0 is bi-directional data and SPC0 is an input only serial clock. In the reference design, SPD0 and SPC0 pins are pulled up to +.V with.k resistors always as shown in Figure. and and are used to interface with the DDC of HDMI Source or transmitter and the serial PROM. This DDC pair needs to be pulled up to V through 7 KΩ resistors (Refer to Figure ). VCC_ U R9.K R0.K SPC0 SPD0 SPC0 SPD0 VDD QFN R7 7K R 7K CH70A Figure : Serial Port Control Rev 0. //0
4 . HDMI receiver Pins AN-B07 The,, RD [:0] P, RD [:0] N signals are high frequency differential signals that need to be routed with special precautions. Since those signals are differential, they must be routed in pairs... Differential Pair Impedance To match the external cable impedance and maintain the maximal energy efficiency it is important to meet the impedance target of 00-Ω ± 0% for the differential data/clock traces. The restriction of this impedance target is to prevent any loss of signal strengths resulting from a reflection of unwanted signals. The impedance can be acquired by proper design of trace length, trace width, signal layer thickness, board dielectric, etc. The HDMI differential pairs should be routed on the top layer directly to the HDMI connector pads if possible... Trace Routing Length To prevent from capacitive and impedance loading, trace lengths should be kept as minimal as possible. Vias and bends should always be minimized; inductive effects may be introduced, causing spikes in the signals. Trace routing lengths from the HDMI connector to CH70A are limited to a maximum of inches. The CH70A should be as close to the HDMI connector as possible... Length Matching for Differential Pairs It is recommended that length matching of both signals of a differential pair be within mils. Length matching should occur on a segment-by-segment basis. Segments might include the path between vias, resistor pads, capacitor pads, a pin, an edge-finger pad, or any combinations of them, etc. Length matching from one pair to any other should be within 00 mils. Note that lengths should only be counted to the pins or pad edge. Additional etch within the edge-finger pad, for instance, is electrically considered part of the pad itself... ESD Protection for HDMI Interface In order to minimize the hazard of ESD, a set of protection diodes are highly recommended for each HDMI input (data and clock). International standard EN 0:99 establishes kv as the common immunity requirement for contact discharges in electronic systems. kv is also established as the common immunity requirement for air discharges in electronic systems. International standard EN 000--:99 / IEC 000--:99 establishes the immunity testing and measurement techniques. System level ESD testing to International standard EN 000--:99 / IEC 000--:99 has confirmed that the proper implementation of Chrontel recommended diode protection circuitry, using BCD AT0 diode array devices, will protect the CH70A device from HDMI transmitter discharges of greater than 9kV (contact) and 0kV (air). The AT0 have a typical capacitance of only 0.0pF between I/O pins. This low capacitance won t bring too much bad effect on HDMI eye diagram test. Figure (A) and (B) show the connection of HDMI connectors, including the recommended design of AT0 diode array devices. HDMI connector is used to connect the CH70A HDMI inputs from HDMI transmitter Rev 0. //0
5 AN-B07 U QFN CH70A RDN 7 RDP 9 RDN 0 RDP 0 RDN RDP RDN RDP Figure (A): The connection of the HDMI input J RDP RDN RDP RDN U LINE 9 NC 0 NC LINE 7 LINE NC NC LINE AT0 C 0.uF U LINE 9 NC 0 NC LINE 7 LINE NC NC LINE RDP RDN RDP RDN VDD_0 C9 0uF VDD_0 RDP RDN RDP RDN VDD_0 RX+ RX_shld RX- RX+ RX_shld RX- RX0+ RX0_shld RX0- RXC+ RXC_shld RXC- CEC RESERVED SCL SDA DDC_ +V HTPLUG HDMI_A AT0 R k D SM7 JP HEADER D AZ-0H D R7 7K R 7K D HDMI input AZ-0H AZ-0H Figure (B): The connection of the HDMI inputs-ch70a HDMI connectors The following is the description for each HDMI interface pins HDMI Link Data Channel (RD [:0] P and RD [:0] N) Rev 0. //0
6 AN-B07 These pins provide HDMI differential inputs for data channel 0 (blue), data channel (green) and data channel (red). (Refer to Figure (A)). HDMI Link Clock Outputs ( and ) These pins provide the HDMI differential clock inputs for HDMI corresponding to data on the RD [:0] P and RD [:0] N inputs (Refer to Figure (A)). (HDMI Hot Plug Detect) This output pin connects to the +V power through a KΩ resistor. Refer to Figure (B) for the design example.. BT Outputs BT output CH70A support bit YCbCr ::(BT) output format. (Refer to Figure ) U CH70A QFN 7 D7 D D D D D D 0 D0 HO VO DEO CLKO 7 D7 D D D D D D D0 HO VO DEO CLKO Figure : CH70A BT output.7 Audio Output IIS IIS audio output can be configured through programming CH70A registers. (Refer to Figure 7) SPDIF For SPDIF output, CH70A supports audio sample frequencies from Khz to 9kHz. (Refer to Figure 7) Rev 0. //0
7 AN-B07 J HEADER U SPDIF SD/SPDIF WS 7 SCLK MCLK 9 IS DAC CH70A Figure 7: CH70A IIS or SPDIF Output Pins Rev 0. //0 7
8 AN-B07.0 REFERENCE DESIGN EXAMPLE The figures below are the reference schematic of CH70A, which is provided here for design reference only. Please contact Chrontel Applications group for further support. Table provides the BOM list for the reference schematic.. Reference Schematic VDD_ C 0uF VDD_0 R 00K % C0 L.7uF.uH R 00K % C pf U EN SW FB VIN VIN FB SW EN AT R C K % pf VDD_ VDD_0 L C FB.7uF VDD_ L C9.uH 0uF VDD_ L R 00K % FB Power of CH70 C 0uF AVDD C 0uF C C 0.uF 0.uF C 0.uF C 0.uF VDD_ L VDDPLL FB C7 C 0.uF 0uF VDD_ L DVDD FB C C C7 0.uF 0uF 0.uF J RDP RDN RDP RDN U LINE NC NC LINE LINE NC NC LINE AT0 U LINE NC NC LINE LINE NC NC LINE AT C 0.uF RDP RDN RDP RDN VDD_0 C9 0uF VDD_0 R k RDP RDN RDP RDN RX+ RX_shld RX- RX+ RX_shld 7 RX- RX0+ 9 RX0_shld 0 RX0- RXC+ RXC_shld RXC- CEC RESERVED SCL 7 SDA DDC_ 9 +V 0 HTPLUG HDMI_A VDD_0 D SM7 DD VDDPLL DVDD DD SD/SPDIF WS SCLK MCLK RB U VDDPLL DVDD D RDP 0 SD/SPDIF WS SCLK MCLK RB RDP RDN 9 RDN RDP 7 RDP RDN RDN AVDD AVDD CH70 0pin QFN RBIAS DO7 DO DO DO DO DO DO RBIAS D7 D D D D D D D7 D D D D D D D0 HO VO DEO JP HEADER D AZ-0H D R 7K R7 7K D CH70A SPC0 SPC0 SPD0 SPD0 VO VO HO HO DEO DEO 7 CLKO CLKO DVDD DVDD 9 DD D 0 D0 DO0 CLKO HDMI input AZ-0H AZ-0H JP VCC_ SD/SPDIF SD HEADER DD SPC0 SPD0 R.K JP R9.K RBIAS R 0K % VDD_ R M SW RB C 0.uF SD SCLK WS MCLK C 0.uF C 0uF U SDIN SCLK LRCK MCLK VQ SC AOUTR 0 VA 9 7 AOUTL FILT+ Audio IS to L, R CHANNEL C 0uF VDD_ C0 C 0uF C 7uF 7uF R0 7.K J R 7.K PJ HEADER CH70 interface Rev 0. //0
9 . Reference Board Preliminary BOM AN-B07 Table : CH70A Reference Design BOM List Item Quantity Reference Part C, C0.7uF C, C pf 0 C, C7, C9, C, C, C, C9, C, C, C 0uF 0 C, C, C, C, C, C, C7, C, C, C 0.uF C0, C 7uF D SM7 7 D, D, D AZ-0H JP, JP HEADER 9 JP HEADER 0 J HDMI_A J PJ L, L, L, L FB L, L.uH R, R, R 00K % R K % R k 7 R, R7 7K R, R9.K 9 R0, R 7.K 0 R M R 0K % U AT709 U, U AT0 U CH70A U SC Rev 0. //0 9
10 AN-B07.0 REVISION HISTORY Table : Revisions Rev. # Date Section Description 0. //0 All Initial release Rev 0. //0
11 Disclaimer AN-B07 This document provides technical information for the user. Chrontel reserves the right to make changes at any time without notice to improve and supply the best possible product and is not responsible and does not assume any liability for misapplication or use outside the limits specified in this document. We provide no warranty for the use of our products and assume no liability for errors contained in this document. The customer should make sure that they have the most recent data sheet version. Customers should take appropriate action to ensure their use of the products does not infringe upon any patents. Chrontel, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such rights. Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used as directed can reasonably expect to result in personal injury or death. Chrontel Chrontel International Limited 9 Front Street, th floor, Hamilton, Bermuda HM sales@chrontel.com 0 Chrontel - All Rights Reserved Rev 0. //0
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