IMM2G72D3LRVQ8AG (Die Revision C) 16GByte (2048M x 72 Bit)

Transcription

1 Daashee Rev IMM2G72D3LRVQ8AG (Die Revision C) 16GBye (2048M x 72 Bi) 16GB DDR3 VLP Regisered DIMM RoHS Complian Produc Remark: Please refer o he las page of he i) Conens ii) Lis of Table iii) Lis of Figures. We Lisen o Your Commens Any informaion wihin his documen ha you feel is wrong, unclear or missing a all? Your feedback will help us o coninuously improve he qualiy of his documen. Please send your proposal (including a reference o his documen) o: sales@inelligenmemory.com 1 IMM2G72D3LRVQ8AG

2 Feaures 240-Pin Regisered Dual-In-Line Memory Module Capaciy: 16GB JEDEC-Sandard Bi-direcional Differenial Daa-Srobe 72 Bi Daa Bus Widh wih ECC Programmable CAS Laency (CL): o PC : 5, 6, 7, 8, 9, 10, 11 o PC : 5, 6, 7, 8, 9, 10 Programmable CAS Wrie Laency (CWL): o PC : 5, 6, 7, 8 o PC : 5, 6, 7 Programmable Addiive Laency (Posed ): 0, CL-2 or CL-1(Clock) On-Die Terminaion (ODT) ZQ Calibraion Suppored Burs Type (Sequenial & Inerleave) Burs Lengh: 4, 8 Refresh Mode: Auo and Self 8192 Refresh Cycles / 64ms Asynchronous Rese On-board I2C Temperaure Sensor wih Inegraed Serial Presence Deec (SPD) EEPROM Gold Edge Conacs 100% RoHS-Complian Very Low Profile Module Heigh: 18.75mm (0.738 inch) 2 IMM2G72D3LRVQ8AG

3 Table 1 - Ordering Informaion for RoHS Complian Produc Par Number Module Densiy Configuraion # of Ranks Module Type IMM2G72D3xRVQ8AG-Czzzy 16GB 2Gx GB DDR3 VLP Regisered DIMM Noes: x: Operaing Volage y: Operaing Temperaure zzz: Speed Grade Table 2 - Operaing Volage Par Number L Operaing Volage VDD, VDDQ = 1.35V (1.283V-1.45V) Backward compaible o VDD, VDDQ = 1.5V (1.425V-1.575V) Table 3 - Temperaure Grade Par Number Temperaure Grade Tcase Blank Commercial emperaure 0 C o 95 C I Indusrial emperaure -40 C o 95 C Remark: Tcase is he case surface emperaure on he cener/op side of he DRAM. The refresh rae is required o double when 85 o C < T case <= 95 o C. Table 4 - Speed Grade Par Number Speed Grade Max Clock Frequency (min. Clock Cycle min. CAS Laency) 125 PC (DDR3-1600) 800MHz (1.25ns@CL=11) 15E PC (DDR3-1333) 667MHz (1.5ns@CL=9) Table 5 - Memory Chip Informaion Par Number Base Device Brand Base device Volage Type Chip Packing IMM2G72D3LRVQ8AG-Czzzy I M IM8G08D3FCDG 1.35V 512Mx8x2 DDP Lead Free 3 IMM2G72D3LRVQ8AG

4 Par Number Decoder IMM 2G72 D3 L RV Q 8 A G - C 125 (I) Inelligen Temperaure Grade Memory Blank = Commercial Temperaure Module (0 C o 95 C T C ) I = Indusrial Temperaure Module Configuraion (-40 C o 95 C TC) 2G72 = 2Gx72 (16GB) Speed Grade Memory Type 15E = PC / DDR D3 = DDR3 125 = PC / DDR DDR3L opion L = 1.35 or 1.5 Vol (DDR3L) Module Form-Facor RV = VLP Regisered DIMM Number of Ranks Q = Quad Rank IC Revision C = Revision C RoHS compliance G = Green / RoHS Module PCB Revision A = Revision A DRAM Bi widh 8 = using x8 componens Table 6 - Addressing Parameer 16GB Refresh coun 8K Row address 64K A[15:0] Device bank address 8 BA[2:0] Device configuraion 8Gb (512Mx8x2 DDP) Column address 1K A[9:0] Module rank address 4 /S[3:0] Number of devices IMM2G72D3LRVQ8AG

5 Table 7 - Pin Assignmen Pin Name Pin Name Pin Name Pin Name 1 VREFDQ A2 181 A D4 62 VDD 182 VDD 3 D0 123 D VDD 4 D / DM0, T9 65 VDD 185 /0 6 /0 126 NC, /T9 66 VDD 186 VDD VREFCA 187 /EVENT D6 68 PAR_IN 188 A0 9 D2 129 D7 69 VDD 189 VDD 10 D A10, AP 190 BA D12 71 BA0 191 VDD 12 D8 132 D13 72 VDD D /S DM1, T VDD 15 /1 135 NC, /T10 75 VDD /S1 196 A D VDD 18 D D15 78 VDD 198 /S3 19 D /S D D36 21 D D21 81 D D37 22 D D DM2, T DM4, T13 24 /2 144 NC, /T11 84 /4 204 NC, /T D D38 27 D D23 87 D D39 28 D D D D44 30 D D29 90 D D45 31 D D DM3, T DM5, T14 33 /3 153 NC, /T12 93 /5 213 NC, /T D D46 36 D D31 96 D D47 37 D D CB D52 39 CB0 159 CB5 99 D D53 40 CB D DM8, T DM6, T15 42 /8 162 NC, /T /6 222 NC, /T CB D54 45 CB2 165 CB7 105 D D55 46 CB D NC D60 48 VTT 168 /RESET 108 D D61 49 VTT 169 E1 109 D E0 170 VDD DM7, T16 51 VDD 171 A /7 231 NC, /T16 52 BA2 172 A /ERR_OUT 173 VDD D62 54 VDD 174 A12, /BC 114 D D63 55 A A9 115 D A7 176 VDD VDDSPD 57 VDD 177 A8 117 SA0 237 SA1 58 A5 178 A6 118 SCL 238 SDA 59 A4 179 VDD 119 SA VDD 180 A3 120 VTT 240 VTT 5 IMM2G72D3LRVQ8AG

6 Table 8 - Pin Descripion Pin Name Descripion Pin Name Descripion VDD SDRAM core power supply VREFDQ SDRAM I/O reference supply VREFCA SDRAM command/address reference supply Power supply reurn (ground) A0-A15 SDRAM address bus BA0-BA2 SDRAM bank addresses 0-1 SDRAM clocks (posiive line of differenial pair) /0-/1 SDRAM clocks (negaive line of differenial pair) SDRAM row address srobe SDRAM column address srobe SDRAM wrie enable E0-E1 SDRAM clock enable lines /S0-/S3 DIMM Rank Selec Lines - On-die erminaion conrol lines 0-8 SDRAM daa srobes (posiive line of differenial pair) /0-/8 SDRAM daa srobes (negaive line of differenial pair) T9-T17 Terminaion SDRAM daa srobes (posiive line of differenial pair) /T9-/T17 Terminaion SDRAM daa srobes (negaive line of differenial pair) D0-D63 DIMM memory daa bus CB0-CB7 Daa check bis Inpu/Oupu DM0-DM8 Daa Masks SDA EEPROM daa line SCL EEPROM clock VDDSPD EEPROM posiive power supply SA0-SA2 EEPROM address inpu /EVENT Temperaure even PAR_IN Pariy Inpu /RESET Regiser and SDRAM conrol pin /ERR_OUT Pariy Error Oupu VTT Terminaion Volage NC Spare Pins (no connec) IMM2G72D3LRVQ8AG

7 Module Dimension Figure Pin DDR3 SDRAM VLP Regisered DIMM B A A B Table 9 - PCB Dimension Symbol MIN NOM MAX A A A A D D Basic D Basic e Basic e Basic E Noes: All dimensioning and olerancing conform o ASME Y14.5M Tolerances for all dimensions ±0.15 unless oherwise specified. All dimensions are in millimeers. 7 IMM2G72D3LRVQ8AG

8 Figure 2 Funcional Block Diagram (Page 1 of 3) /RRASA /RCASA /RWEA RA[15:0]A / BA[2:0]A P0A /P0A /RS0 RE0A RA /RS1 RE1A VDD P1A /P1A /RS2 RA /RS3 VDD 8 /8 DM8/17 /17 CB0-CB7 / T /T U9 / E0 E1 / T /T U18 / E0 E1 3 /3 DM3/12 /12 D24-D31 / T /T U4 / E0 E1 / T /T U13 / E0 E1 2 /2 DM2/11 /11 D16-D23 / T /T U3 / E0 E1 / T /T U12 / E0 E1 1 /1 DM1/10 /10 D8-D15 / T /T U2 / E0 E1 / T /T U11 / E0 E1 0 /0 DM0/9 /9 / T /T U1 / E0 E1 / T /T U10 / E0 E1 VTT VTT 8 IMM2G72D3LRVQ8AG

9 Figure 3 Funcional Block Diagram (Page 2 of 3) /RRASB /RCASB /RWEB RA[15:0]B/BA[2:0]B P0B /P0B /RS0 RE0B RB /RS1 RE1B VDD P1B /P1B /RS2 RB /RS3 VDD 4 /4 DM4/13 /13 D32-D39 / T /T U5 / E0 E1 / T /T U14 / E0 E1 5 /5 DM5/14 /14 D40-D47 / T /T U6 / E0 E1 / T /T U15 / E0 E1 6 /6 DM6/15 /15 D48-D55 / T /T U7 / E0 E1 / T /T U16 / E0 E1 7 /7 DM7/16 /16 D56-D63 / T /T U8 / E0 E1 / T /T U17 / E0 E1 VTT VTT 9 IMM2G72D3LRVQ8AG

10 Figure 4 Funcional Block Diagram (Page 3 of 3) /S0 /S2 /S3 BA[2:0] /RS0: U1-U9 /S1 /RS1: U1-U9 /RS2: U10-U18 /RS3: U10-U18 RBA[2:0]A: U1-U4, U9-U13, U18 RBA[2:0]B: U5-U8, U14-U17 VDDSPD VDD U20 U1-U18 A[15:0] RA[15:0]A: U1-U4, U9-U13, U18 RA[15:0]B: U5-U8, U14-U17 VTT U1-U18 /RRASA: U1-U4, U9-U13, U18 /RRASB: U5-U8, U14-U17 VREFCA U1-U18 /RCASA: U1-U4, U9-U13, U18 /RCASB: U5-U8, U14-U17 VREFDQ U1-U18 U19 1:2 REGISTER /RWEA: U1-U4, U9-U13, U18 /RWEB: U5-U8, U14-U17 RA: U1-U4, U9 RB: U5-U8 U1-U18 RA: U10-U13, U18 RB: U14-U17 Thermal Sensor wih SPD 0 P0A: U1-U4, U9 P0B: U5-U8 P1A: U10-U13, U18 P1B: U14-U17 SDA SCL SDA SCL U20 VDD /EVENT VDDSPD /EVENT /0 1 /P0A: U1-U4, U9 /P0B: U5-U8 /P1A: U10-U13, U18 /P1B: U14-U17 A0 A1 A2 SA0 SA1 SA2 /1 PAR_IN /ERR_OUT /RESET /RST: U1-U IMM2G72D3LRVQ8AG

11 Elecrical Parameer Table 10 - Absolue Maximum DC Raings Parameer Symbol Raing Uni Noes Volage on VDD, pin relaive o VDD -0.4V ~ V 1,3 Volage on VDDQ, pin relaive o VDDQ -0.4V ~ V 1,3 Volage on any pins relaive o VIN, VOUT -0.4V ~ V 1 DRAM Sorage emperaure TSTG -55 ~ 100 o C 1,2 DRAM Operaion emperaure (Sandard Produc) Tcase 0 ~ 95 o C 2,4,6 DRAM Operaion emperaure (Indusrial Temperaure Produc) Tcase -40 ~ 95 o C 2,5,6 Noes: 1 Sresses greaer han hose lised under Absolue Maximum Raings may cause permanen damage o he device. This is a sress raing only and funcional operaion of he device a hese or any oher condiions above hose indicaed in he operaional secions of his specificaion is no implied. Exposure o absolue maximum raing condiions for exended periods may affec reliabiliy. 2 Sorage Temperaure or DRAM operaion emperaure is he case surface emperaure on he cener/op side of he DRAM. For he measuremen condiions, please refer o JESD51-2 sandard. 3 V DD and V DDQ mus be wihin 300mV of each oher a all imes; and V REF mus no be greaer han 0.6 x V DDQ, when V DD and V DDQ are less han 500mV; V REF may be equal o or less han 300mV. 4 The Normal Temperaure Range specifies he emperaures when all DRAM specificaions will be suppored. During operaion, he DRAM case emperaure mus be mainained beween 0-95 C under all operaing condiions. 5 The Normal Temperaure Range specifies he emperaures when all DRAM specificaions will be suppored. During operaion, he DRAM case emperaure mus be mainained beween C under all operaing condiions. 6 Some applicaions require operaion of he Exended Temperaure Range beween 85 C and 95 C case emperaure. Full Specificaions are guaraneed in his range bu he following addiional condiions apply a) Refresh commands mus be doubled in frequency, herefore reducing he refresh inerval REFI o 3.9us. b) If Self-Refresh operaion is required in he Exended Temperaure Range, hen i is mandaory o eiher use he Manual Self-Refresh mode wih Exended Temperaure Range capabiliy (MR2 A6 = 0b and MR2 A7 = 1b) or enable he opional Auo Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b). Table 11 - DC Elecrical Characerisics and Operaing Condiions Parameer / Condiion Symbol Raing Min Typ Max Unis Noes Supply volage VDD V 1, I/O supply volage VDDQ V 1,2 Supply volage VDD V 1,2, I/O supply volage VDDQ V 1,2,3 Noes: 1 V DD and V DDQ mus rack one anoher. V DDQ mus be less han or equal o V DD. V SS = V SSQ. 2 V DD and V DDQ may include AC noise of +/-50mV (250 khz o 20 MHz) in addiion o he DC (0 Hz o 250 khz) specificaions. V DD and V DDQ mus be a same level for valid AC iming parameers. 3 Module is backward-compaible wih 1.5V operaion IMM2G72D3LRVQ8AG

12 Table 12 - DC Elecrical Characerisics and Inpu Condiions Parameer / Condiion Symbol Raing Min Typ Max VIN low; DC/commands/address buses (1.35V) VIL V VIN low; DC/commands/address buses (1.5V) VIL V VIN high; DC/commands/address buses (1.35V) VIH VDD V VIN high; DC/commands/address buses (1.5V) VIH VDD V Unis Noes Inpu reference volage; command/address bus VREFCA(DC) 0.49* VDD 0.50* VDD 0.51* VDD V 1,2 I/O reference volage DQ bus VREFDQ(DC) 0.49* VDD 0.50* VDD 0.51* VDD V 2,3 Command/address erminaion volage (sysem level, no direc DRAM inpu) VTT * VDDQ - V 4 Noes: 1 V REFCA(DC) is expeced o be approximaely 0.5 V DD and o rack variaions in he DC level. Exernally generaed peak noise (noncommon mode) on V REFCA may no exceed ±1% V DD around he V REFCA(DC) value. Peak-o-peak AC noise on V REFCA should no exceed ±2% of V REFCA(DC). 2 DC values are deermined o be less han 20 MHz in frequency. DRAM mus mee specificaions if he DRAM induces addiional AC noise greaer han 20 MHz in frequency. 3 V REFDQ(DC) is expeced o be approximaely 0.5 V DD and o rack variaions in he DC level. Exernally generaed peak noise (noncommon mode) on V REFDQ may no exceed ±1% V DD around he V REFDQ(DC) value. Peak-o-peak AC noise on V REFDQ should no exceed ±2% of V REFDQ(DC). 4 V TT is no applied direcly o he device. V TT is a sysem supply for signal erminaion resisors. MIN and MAX values are sysem-dependen IMM2G72D3LRVQ8AG

13 Table 13 - Inpu Swiching Condiions Parameer / Condiion Symbol Value 1.35V 1.5V Command and Address Inpu high AC volage: Logic 175mV VIH(AC175)min mv Inpu high AC volage: Logic 160mV VIH(AC160)min mv Inpu high AC volage: Logic 150mV VIH(AC150)min mv Inpu high AC volage: Logic 135mV VIH(AC135)min mv Inpu high DC volage: Logic 100mV VIH(DC100)min mv Inpu high DC volage: Logic 90mV VIH(DC90)min 90 - mv Inpu low DC volage: Logic VIL(DC90)max mv Inpu low DC volage: Logic VIL(DC100)max mv Inpu low AC volage: Logic VIL(AC135)max mv Inpu low AC volage: Logic VIL(AC150)max mv Inpu low AC volage: Logic VIL(AC160)max mv Inpu low AC volage: Logic VIL(AC175)max mv Unis Parameer / Condiion Symbol DQ and DM Value 1.35V 1.5V Inpu high AC volage: Logic 1 VIH(AC150)min mv Inpu high AC volage: Logic 1 VIH(AC135)min mv Inpu high DC volage: Logic 1 VIH(DC100)min mv Inpu high DC volage: Logic 1 VIH(DC90)min 90 - mv Inpu low DC volage: Logic 0 VIL(DC90)max mv Inpu low DC volage: Logic 0 VIL(DC100)max mv Inpu low AC volage: Logic 0 VIL(AC135)max mv Inpu low AC volage: Logic 0 VIL(AC150)max mv Noes: 1. All volages are referenced o V REF. V REF is V REFCA for conrol, command, and address. All slew raes and seup/hold imes are specified a he DRAM ball. V REF is V REFDQ for DQ and DM inpus. 2. Inpu seup iming parameers (IS and DS) are referenced a V IL(AC)/V IH(AC), no V REF(DC). 3. Inpu hold iming parameers (IH and DH) are referenced a V IL(DC)/V IH(DC), no V REF(DC). 4. Single-ended inpu slew rae = 1 V/ns; maximum inpu volage swing under es is 900mV (peak-o-peak). Unis 13 IMM2G72D3LRVQ8AG

14 Table 14 - Differenial Inpu Operaing Condiions (, / and, /) Parameer / Condiion Symbol Min Raing Max Unis Noes Differenial inpu volage logic high slew (1.35V) VIH,diff mv 1 Differenial inpu volage logic high slew (1.5V) VIH,diff mv 1 Differenial inpu volage logic low slew (1.35V) VIL,diff mv 1 Differenial inpu volage logic low slew (1.5V) VIL,diff mv 1 Differenial inpu volage logic high VIH,diff(AC) 2* (VIH(AC) - VREF) - mv 2 Differenial inpu volage logic low VIL,diff(AC) - 2* (VIL(AC)- VREF) mv 3 Differenial Inpu Cross Poin Volage relaive o VDD/2 for, (1.35V) VIX mv 4 Differenial Inpu Cross Poin Volage relaive o VDD/2 for, (1.5V) VIX mv Differenial Inpu Cross Poin Volage relaive o VDD/2 for, (1.35V) VIX mv Differenial Inpu Cross Poin Volage relaive o VDD/2 for, (1.5V) VIX mv Noes: 1 Defines slew rae reference poins, relaive o inpu crossing volages. 2 Minimum DC limi is relaive o single-ended signals; overshoo specificaions are applicable. 3 Maximum DC limi is relaive o single-ended signals; undershoo specificaions are applicable. 4 The relaion beween V IX Min/Max and V SEL/V SEH should saisfy following: (V DD/2) + V IX(min) - V SEL >= 25mV; V SEH -((V DD/2) + V IX(max)) >= 25mV; 5 Exended range for V IX is only allowed for clock and if single-ended clock inpu signals and / are monoonic wih a single-ended swing V SEL/V SEH of a leas V DD/2 +/-250mV, and when he differenial slew rae of -/ is larger han 3V/ns IMM2G72D3LRVQ8AG

15 Table 15 - Single-Ended Oupu Driver Characerisics Parameer / Condiion Oupu slew rae: Single-ended; For rising and falling edges, measure beween VOL(AC) = VREF * VDDQ and VOH(AC) = VREF * VDDQ (1.35V) Oupu slew rae: Single-ended; For rising and falling edges, measure beween VOL(AC) = VREF * VDDQ and VOH(AC) = VREF * VDDQ (1.5V) Single-ended high level for srobes Symbol Min Raing Max Unis Noes SRQse V/ns 1,2,3 SRQse V/ns 1,2,3 VSEH VDD/ mv 2 Single-ended high level for, / VDD/ mv 2 Single-ended low level for srobes VSEL - VDD/2-175 mv 3 Single-ended low level for, / - VDD/2-175 mv 3 Single-ended DC high-level oupu volage VOH(DC) 0.8 * VDDQ V 1 Single-ended DC mid-level oupu volage VOM(DC) 0.5 * VDDQ V 1 Single-ended DC low-level oupu volage VOL(DC) 0.2 * VDDQ V 1 Single-ended AC high-level oupu volage VOH(AC) VTT * VDDQ V 1,2 Single-ended AC low-level oupu volage VOL(AC) VTT * VDDQ V 1,2 Tes load for AC iming and oupu slew raes Oupu o VTT (VDDQ/2) via 25Ω resisor Noes: 1. RZQ of 240Ω (±1%) wih RZQ/7 enabled (defaul 34Ω driver) and is applicable afer proper ZQ calibraion has been performed a a sable emperaure and volage (V DDQ = V DD, V SSQ = V SS). 2. V TT = V DDQ/2. 3. The 6 V/ns maximum is applicable for a single DQ signal when i is swiching eiher from HIGH o LOW or LOW o HIGH while he remaining DQ signals in he same bye lane are eiher all saic or all swiching he opposie direcion. For all oher DQ signal swiching combinaions, he maximum limi of 6 V/ns is reduced o 5 V/ns. Table 16 - Differenial Oupu Driver Characerisics Parameer / Condiion Symbol Min Raing Max Unis Noes Oupu slew rae: Differenial; For rising and falling edges, measure beween VOL,diff(AC) = * VDDQ and VOH,diff(AC) = * VDDQ (1.35V) SRQdiff V/ns 1 Oupu slew rae: Differenial; For rising and falling edges, measure beween VOL,diff(AC) = * VDDQ and VOH,diff(AC) = * VDDQ (1.5V) SRQdiff 5 10 V/ns 1 Differenial high-level oupu volage VOH,diff(AC) +0.2 * VDDQ V 1 Differenial low-level oupu volage VOL,diff(AC) -0.2 * VDDQ V 1 Tes load for AC iming and oupu slew raes Oupu o VTT (VDDQ/2) via 25Ω resisor Noes: 1. RZQ of 240Ω (±1%) wih RZQ/7 enabled (defaul 34Ω driver) and is applicable afer proper ZQ calibraion has been performed a a sable emperaure and volage (V DDQ = V DD, V SSQ = V SS). 2. V REF = V DDQ/2; slew 5V/ns, inerpolae for faser slew rae IMM2G72D3LRVQ8AG

16 For par number IMM2G72D3LRVQ8AG-C125(I) Table 17 - IDD Specificaions wih Condiions and Operaion Curren Parameer / Condiion Symbol Curren Unis Noes Operaing curren 0; One bank ACTIVATE-o-PRECHARGE IDD0 954 ma 1, 2 Operaing curren 1; One bank ACTIVATE-o-READ-o-PRECHARGE IDD ma 1, 2 Precharge power-down curren (Slow Exi) IDD2P0 468 ma 1, 3 Precharge sandby ODT curren IDD2NT 1170 ma 1, 3 Acive power-down curren IDD3P 810 ma 1, 3 Acive sandby curren IDD3N 1260 ma 1, 3 Burs read operaing curren IDD4R 1539 ma 1, 2 Burs wrie operaing curren IDD4W 1584 ma 1, 2 Refresh curren IDD5B 2664 ma 1, 2 Self refresh emperaure curren: MAX Tc = 85 o C IDD6 540 ma 1, 3 Self refresh emperaure curren (SRT-enabled): MAX Tc = 95 o C IDD6ET 720 ma 1, 3 All banks inerleaved read curren IDD ma 1, 2 RESET Low Curren IDD8 540 ma 1, 3 Noes: 1 Value shown for DDR3 SDRAM only and are compued from values specified in he 8Gbi componen daa shee. 2 One module rank in he acive IDD, he oher rank in IDD2P0. 3 All ranks in his IDD condiions IMM2G72D3LRVQ8AG

17 For par number IMM2G72D3LRVQ8AG-C125(I) Table 18 - AC Timing Parameer and Operaing Condiions Parameer / Condiion Symbol Min Max Unis Clock Timing Clock period average: T C = 0 o C o 85 o C (DLL_DIS) DLL disable mode T C => 85 o C o 95 o C ns Clock periods average: DLL enable mode (CL = 11, CWL = 8) (AVG) 1.25 <1.5 ns Clock periods average: DLL enable mode (CL = 9, CWL = 7) (AVG) 1.5 <1.875 ns High pulse widh average CH (AVG) Low pulse widh average CL (AVG) Clock period jier DLL locked JITper ps DLL locking JITper,Ick ps Clock absolue period (ABS) (AVG) MIN + (AVG) MAX + JITper MIN JITper MAX ps Clock absolue high pulse widh CH (ABS) (AVG) Clock absolue low pulse widh CL (ABS) (AVG) Cycle-o-cycle jier DLL locked JITcc ps DLL locking JITcc,Ick ps 2 cycles ERR2per ps 3 cycles ERR3per ps 4 cycles ERR4per ps 5 cycles ERR5per ps 6 cycles ERR6per ps 7 cycles ERR7per ps Cumulaive error across 8 cycles ERR8per ps 9 cycles ERR9per ps 10 cycles ERR10per ps 11 cycles ERR11per ps 12 cycles ERR12per ps n = 14, 49, 50 cycles ERRnper DQ Inpu Timing (1+0.68ln[n]) * JITper MIN (1+0.68ln[n]) * JITper Max Daa seup ime o, / (1.35V) Base (specificaion) DS (AC135) 25 - ps Daa seup ime o, / (1.5V) Base (specificaion) DS (AC150) 10 - ps Daa hold ime from, / (1.35V) Base (specificaion) DH (DC90) 55 - ps Daa hold ime from, / (1.5V) Base (specificaion) DH (DC100) 45 - ps Minimum daa pulse widh DIPW ps DQ Oupu Timing, / o DQ skew, per access Q ps DQ oupu hold ime from, / QH (AVG) DQ Low-Z ime from, / LZDQ ps DQ High-Z ime from, / HZDQ ps DQ Srobe Inpu Timing, / rising o, / rising S , / differenial inpu low pulse widh L ps 17 IMM2G72D3LRVQ8AG

18 For par number IMM2G72D3LRVQ8AG-C125(I) Parameer / Condiion Symbol Min Max Unis, / falling seup o, / rising DSS , / falling hold from, / rising DSH , / differenial inpu high pulse widh H , / differenial WRITE preamble WPRE 0.9 -, / differenial WRITE posamble WPST DQ Srobe Oupu Timing, / rising o/from, / ps, / differenial oupu high ime QSH , / differenial oupu low ime QSL , / Low-Z ime (RL-1) LZ ps, / High-Z ime (RL+BL/2) HZ ps, / differenial READ preamble RPRE 0.9 greaer of LZ() (MIN), K (MAX), / differenial READ posamble RPST 0.3 greaer of (MIN) + QSH (MIN), HZ() (MAX) Command and Address Timing DLL locking ime DLLK CTRL, CMD, ADDR seup o, / (1.35V) Base (specificaion) IS (AC160) 60 - ps CTRL, CMD, ADDR seup o, / (1.5V) Base (specificaion) IS (AC175) ps CTRL, CMD, ADDR seup o, / (1.35V) Base (specificaion) IS (AC135) ps CTRL, CMD, ADDR seup o, / (1.5V) Base (specificaion) IS (AC150) ps CTRL, CMD, ADDR hold from, / (1.35V) Base (specificaion) IH (DC90) ps CTRL, CMD, ADDR hold from, / (1.5V) Base (specificaion) IH (DC100) ps Minimum CTRL, CMD, ADDR pulse widh IPW ps ACTIVATE o inernal READ or WRITE delay RCD ns PRECHARGE command period RP ns ACTIVATE-o-PRECHARGE command period RAS 35 9 * REFI ns ACTIVATE-o-ACTIVATE command period RC ns ACTIVATE-o-ACTIVATE minimum period RRD greaer of 4 or 6ns - Four ACTIVATE windows (2KB page size) FAW 30 - ns Wrie recovery ime WR 15 - ns Delay from sar of inernal WRITE ransacion o inernal READ command WTR greaer of 4 or 7.5ns - READ-o-PRECHARGE ime RTP greaer of 4 or 7.5ns - -o- command delay CCD 4 - Auo precharge wrie recovery + precharge ime DAL WR + RP/ (AVG) - MODE REGISTER SET command cycle ime MRD 4 - MODE REGISTER SET command updae delay MOD greaer of 12 or 15ns - MULTIPURPOSE REGISTER READ burs end o mode regiser se for mulipurpose regiser exi MPRR IMM2G72D3LRVQ8AG

19 For par number IMM2G72D3LRVQ8AG-C125(I) Parameer / Condiion Symbol Min Max Unis Calibraion Timing POWER-UP and ZQCL command: Long ZQini greaer of 512 RESET operaion or 640ns - calibraion ime Normal operaion ZQoper greaer of 256 or 320ns - ZQCS command: Shor calibraion ime ZQcs greaer of 64 or 80ns - Iniializaion and Rese Timing Exi rese from E HIGH o valid command XPR greaer of 5 or RFC(min)+10ns - Refresh Timing REFRESH-o-ACTIVATE or REFRESH command period RFC ns Tc<=85 C 64 (1X) Maximum refresh period - Tc>85 C 32 (2X) ms Maximum average Tc<=85 C 7.8 (64ms/8192) REFI periodic refresh Tc>85 C 3.9 (32ms/8192) us Self Refresh Timing Exi self refresh o commands no requiring a locked DLL XS greaer of 5 or RFC+10ns - Exi self refresh o commands requiring a locked DLL XSDLL DLLK (MIN) - Minimum E low pulse widh for self refresh enry o self refresh exi iming ESR E (MIN) + - Valid clocks afer self refresh enry or power down enry SRE greaer of 5 or 10ns - Valid clocks before self refresh exi, power-down exi, or rese exi SRX greaer of 5 or 10ns - Power-Down Timing E MIN pulse widh E (MIN) greaer of 3 or 5ns Command pass disable delay CPDED 1 - Power-down enry o power exi iming PD E (MIN) 9 * REFI Power-Down Enry Minimum Timing ACTIVATE command o power-down enry ACTPDEN 1 - PRECHARGE/PRECHARGE ALL command o powerdown enry PRPDEN 1 - REFRESH command o power-down enry REFPDEN 1 - MRS command o power-down enry MRSPDEN MIN = MOD (MIN) READ/READ wih auo precharge command o power-down enry RDPDEN MIN = RL BL8 (OTF, MRS) WRITE command o powerdown enry WRPDEN MIN = WL BC4OTF WR/ (AVG) BC4MRS WRPDEN MIN = WL WR/ (AVG) WRITE wih auo precharge BL8 (OTF, MRS) command o power-down BC4OTF WRAPDEN MIN = WL WR + 1 enry BC4MRS WRAPDEN MIN = WL WR + 1 Power-Down Exi Timing DLL on, any valid command, or DLL off o commands no requiring locked DLL XP greaer of 3 or 6ns - Precharge power-down wih DLL off o commands requiring a locked DLL XPDLL greaer of 10 or 24ns -- ODT Timing R TT urn-on from ODTL on reference AON ps R TT urn-off from ODTL off reference AOF (AVG) 19 IMM2G72D3LRVQ8AG

20 For par number IMM2G72D3LRVQ8AG-C125(I) Parameer / Condiion Symbol Min Max Unis Asynchronous R TT urn-on delay (power-down wih DLL off) AONPD ns Asynchronous R TT urn-off delay (power-down wih DLL off) AOFPD ns ODT high ime wihou wrie command or wih wrie command and BC4 ODTH4 4 - ODT high ime wih Wrie command and BL8 ODTH8 6 - Dynamic ODT Timing R TT dynamic change skew ADC (AVG) Wrie Leveling Timing Firs, / rising edge WLMRD 40 -, / delay WLEN 25 - Wrie leveling seup from rising, / crossing o rising, / crossing WLS ps Wrie leveling hold from rising, / crossing o rising, / crossing WLH ps Wrie leveling oupu delay WLO ns Wrie leveling oupu error WLOE 0 2 ns 20 IMM2G72D3LRVQ8AG

21 For par number IMM2G72D3LRVQ8AG-C125(I) Table 19 - SPD Informaion Bye NO. Descripion Noe Hex 0 Number of Serial PD Byes Wrien / SPD Device Size / CRC Coverage 176 / 256 / SPD Revision Key Bye / DRAM Device Type DDR3 SDRAM 0B 3 Key Bye / Module Type 72bi Regisered DIMM 01 4 SDRAM Densiy and Banks 4Gb 8banks 04 5 SDRAM Addressing Row 16 / Col Module Nominal Volage, VDD 1.35V/1.5V 02 7 Module Organizaion 4Rank, x Module Memory Bus Widh ECC, 72bi 0B 9 Fine Timebase (FTB) Dividend and Divisor 2.5ps Medium Timebase (MTB) Dividend 1/8 (0.125ns) Medium Timebase (MTB) Divisor 1/8 (0.125ns) SDRAM Minimum Cycle Time (min) 1.25ns 0A 13 Reserved CAS Laencies Suppored, Leas Significan Bye 5, 6, 7, 8, 9, 10, 11 FE 15 CAS Laencies Suppored, Mos Significan Bye Minimum CAS Laency Time (AAmin) ns Minimum Wrie Recovery Time (WRmin) 15ns Minimum o Delay Time (RCDmin) ns Minimum Row Acive o Row Acive Delay Time (RRDmin) 6ns Minimum Row Precharge Time (RPmin) ns Upper Nibbles for RAS and RC Minimum Acive o Precharge Time (RASmin), LSB 35ns Minimum Acive o Acive/Refresh Time (RCmin), LSB ns Minimum Refresh Recovery Time (RFCmin), LSB 260ns Minimum Refresh Recovery Time (RFCmin), MSB 260ns Minimum Inernal Wrie o Read Command Delay Time (WTRmin) 7.5ns 3C 27 Minimum Inernal Read o Precharge Command Delay Time (RTPmin) 7.5ns 3C 28 Upper Nibble for FAW 30ns Minimum Four Acivae Window Delay Time (FAWmin), LSB 30ns F0 30 SDRAM Opional Feaures DLL off Mode, RZQ/6, RZQ/ SDRAM Thermal and Refresh Opions 0-95oC Op. Temp. w/2x refresh Module Thermal Sensor Wih TS SDRAM Device Type Non-Sandard SDRAM A IMM2G72D3LRVQ8AG

22 Bye NO. Descripion Noe Hex Reserved, General Secion Module Nominal Heigh 18< Heigh <= Module Maximum Thickness 1< Tf <=2 (mm); 1< Tb <=2 (mm) Reference Raw Card Used Raw card V Address Mapping from Edge Connecor o DRAM 1 Row of DRAM / 1 Regiser Used Hea Spreader Soluion Wihou HS Regiser vendor ID code (LSB) Regiser vendor ID code (MSB) Regiser Revision Number - FF 68 Regiser Type SSTE Regiser Conrol Word Funcion (RC0/RC1) Regiser Conrol Word Funcion (RC2/RC3) Moderae Drive Regiser Conrol Word Funcion (RC4/RC5) Moderae Drive Regiser Conrol Word Funcion (RC6/RC7) Regiser Conrol Word Funcion (RC8/RC9) Regiser Conrol Word Funcion (RC10/RC11) Regiser Conrol Word Funcion (RC12/RC13) Regiser Conrol Word Funcion (RC14/RC15) Reserved Module ID: Module Manufacurer s JEDEC ID Code Reserved Reserved 119 Module ID: Module Manufacuring Locaion Reserved Reserved Module ID: Module Manufacuring Dae Reserved Reserved Module ID: Module Serial Number Reserved Reserved Cyclical Redundancy Code Module Par Number Reserved Reserved Module Revision Code Reserved Reserved DRAM Manufacurer s JEDEC ID Code Reserved Reserved Manufacurer s Specific Daa Reserved Reserved Open For Cusomer Use Reserved Reserved 22 IMM2G72D3LRVQ8AG

23 Revision Hisory Revision Descripions Release Dae 1.0 Iniial release Mar, IMM2G72D3LRVQ8AG

24 Conens Feaures 2 Table 1 - Ordering Informaion for RoHS Complian Produc 3 Table 2 - Operaing Volage 3 Table 3 - Temperaure Grade 3 Table 4 - Speed Grade 3 Table 5 - Memory Chip Informaion 3 Par Number Decoder 4 Table 6 - Addressing 4 Table 7 - Pin Assignmen 5 Table 8 - Pin Descripion 6 Module Dimension 7 Figure Pin DDR3 SDRAM VLP Regisered DIMM 7 Table 9 - PCB Dimension 7 Figure 2 Funcional Block Diagram (Page 1 of 3) 8 Figure 3 Funcional Block Diagram (Page 2 of 3) 9 Figure 4 Funcional Block Diagram (Page 3 of 3) 10 Table 10 - Absolue Maximum DC Raings 11 Table 11 - DC Elecrical Characerisics and Operaing Condiions 11 Table 12 - DC Elecrical Characerisics and Inpu Condiions 12 Table 13 - Inpu Swiching Condiions 13 Table 14 - Differenial Inpu Operaing Condiions (,/ and, /) 14 Table 15 - Single-Ended Oupu Driver Characerisics 15 Table 16 - Differenial Oupu Driver Characerisics 15 Table 17 - IDD Specificaions wih Condiions and Operaion Curren 16 Table 18 - AC Timing Parameer and Operaing Condiions 17 Table 19 - SPD Informaion 21 Revision Hisory 23 Conens 24 Lis of Tables 25 Lis of Figures IMM2G72D3LRVQ8AG

25 Lis of Tables Table 1 - Ordering Informaion for RoHS Complian Produc 3 Table 2 - Operaing Volage 3 Table 3 - Temperaure Grade 3 Table 4 - Speed Grade 3 Table 5 - Memory Chip Informaion 3 Table 6 - Addressing 4 Table 7 - Pin Assignmen 5 Table 8 - Pin Descripion 6 Table 9 - PCB Dimension 7 Table 10 - Absolue Maximum DC Raings 11 Table 11 - DC Elecrical Characerisics and Operaing Condiions 11 Table 12 - DC Elecrical Characerisics and Inpu Condiions 12 Table 13 - Inpu Swiching Condiions 13 Table 14 - Differenial Inpu Operaing Condiions (,/ and, /) 14 Table 15 - Single-Ended Oupu Driver Characerisics 15 Table 16 - Differenial Oupu Driver Characerisics 15 Table 17 - IDD Specificaions wih Condiions and Operaion Curren 16 Table 18 - AC Timing Parameer and Operaing Condiions 17 Table 19 - SPD Informaion 21 Lis of Figures Figure Pin DDR3 SDRAM VLP Regisered DIMM 7 Figure 2 Funcional Block Diagram (Page 1 of 3) 8 Figure 3 Funcional Block Diagram (Page 2 of 3) 9 Figure 4 Funcional Block Diagram (Page 3 of 3) IMM2G72D3LRVQ8AG