IMM1G72D2FBD4AG (Die Revision A) 8GByte (1024M x 72 Bit)

Transcription

1 Datasheet Rev IMM1G72D2FBD4AG (Die Revision A) 8GByte (1024M x 72 Bit) 8GB DDR2 Fully Buffered DIMM RoHS Compliant Product Datasheet Version IMM1G72D2FBD4AG

2 Version: Rev. 1.0, DEC Initial release Remark: Please refer to the last page of the i) Contents ii) List of Table iii) List of Figures. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: sales@intelligentmemory.com Datasheet Version IMM1G72D2FBD4AG

3 Features 240-Pin Fully Buffered Dual-In-Line Memory Module Capacity: 8GB JEDEC-Standard Power Supply: VDD, VDDQ = 1.8± 0.1 V Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature) 72 Bit Data Bus Width with ECC Buffer interface with high-speed differential point-to-point link at 1.5 volt Channel error detection and reporting Channel fail over mode support Programmable CAS Latency (CL): o PC2-6400: 4, 5, 6 o PC2-5300: 4, 5 Programmable Additive Latency (Posted /CAS): 0, CL-2 or CL-1(Clock) Write Latency (WL) = Read Latency (RC) - 1 Posted /CAS On-Die Termination (ODT) Off-Chip Driver (OCD) Impedance Adjustment ZQ Calibration Supported Burst Type (Sequential & Interleave) Burst Length: 4, 8 Refresh Mode: Auto and Self 8192 Refresh Cycles / 64ms Serial Presence Detect (SPD) with EEPROM Gold Edge Contacts 100% RoHS-Compliant Standard Module Height: 30.35mm (1.195 inch) Datasheet Version IMM1G72D2FBD4AG

4 Table 1 - Ordering Information for RoHS Compliant Product Part Number Module Density Configuration # of Ranks Module Type IMM1G72D2FBD4AG-Azzzy 8GB 1Gx72 2 Notes: y: Operating Temperature zzz: Speed Grade 8GB DDR2 Fully Buffered DIMM Table 2 - Temperature Grade Part Number Temperature Grade T case Blank Commercial temperature 0 C to 85 C I Industrial temperature -40 C to 95 C Remark: Tcase is the case surface temperature on the center/top side of the DRAM. The refresh rate is required to double when 85 o C < Tcase <= 95 o C. Table 3 - Speed Grade Part Number Speed Grade Max Clock Frequency (min. Clock Cycle min. CAS Latency) 25 PC (DDR2-800) 400MHz (2.5ns@CL=6) 3 PC (DDR2-667) 333MHz (3.0ns@CL=5) Table 4 - Memory Chip Information Part Number Base Device Brand Base device Voltage Type Chip Packing IMM1G72D2FBD4AG-Azzzy Intelligent Memory IM2G04D2DABG 1.8V 512Mx4 Lead Free Datasheet Version IMM1G72D2FBD4AG

5 Part Number Decoder IMM 1G72 D2 FB D 4 A G - A 25 I Intelligent Memory Temperature Grade Blank = Commercial Temperature Module (0 C to 85 C T C ) I = Industrial Temperature Module Configuration (-40 to 95 C T C ) 1G72 = 1Gx72 (8GB) Memory Type D2 = DDR2 Speed Grade 3 = PC / DDR = PC / DDR2-800 Module Form-Factor Factor FB = Fully Buffered DIMM Number of Ranks D = Dual Rank IC Revision A = Revision A B = Revision B C = Revision C RoHS-compliance G = Green / RoHS Module PCB Revision A = Revision A B = Revision B C = Revision C DRAM Bit width w 4 = using x4 components Table 5 - Addressing Parameter 8GB Refresh count 8K Row address 32K A[14:0] Device bank address 8 BA[2:0] Device configuration 2Gb (512Mx4) Column address 2K A[9:0], A11 Module rank address 2 /S[1:0] Number of devices 36 Datasheet Version IMM1G72D2FBD4AG

6 Table 6 - Pin Assignment Pin Name Pin Name Pin Name Pin Name 1 VDD 121 VDD 61 /PN9 181 /SN9 2 VDD 122 VDD 62 VSS 182 VSS 3 VDD 123 VDD 63 PN SN10 4 VSS 124 VSS 64 /PN /SN10 5 VDD 125 VDD 65 VSS 185 VSS 6 VDD 126 VDD 66 PN SN11 7 VDD 127 VDD 67 /PN /SN11 8 VSS 128 VSS 68 VSS 188 VSS 9 VCC 129 VCC 69 VSS 189 VSS 10 VCC 130 VCC 70 PS0 190 SS0 11 VSS 131 VSS 71 /PS0 191 /SS0 12 VCC 132 VCC 72 VSS 192 VSS 13 VCC 133 VCC 73 PS1 193 SS1 14 VSS 134 VSS 74 /PS1 194 /SS1 15 VTT 135 VTT 75 VSS 195 VSS 16 VID1 136 VID0 76 PS2 196 SS2 17 /RESET 137 DNU,M_Test 77 /PS2 197 /SS2 18 VSS 138 VSS 78 VSS 198 VSS 19 RFU 139 RFU 79 PS3 199 SS3 20 RFU 140 RFU 80 /PS3 200 /SS3 21 VSS 141 VSS 81 VSS 201 VSS 22 PN0 142 SN0 82 PS4 202 SS4 23 /PN0 143 /SN0 83 /PS4 203 /SS4 24 VSS 144 VSS 84 VSS 204 VSS 25 PN1 145 SN1 85 VSS 205 VSS 26 /PN1 146 /SN1 86 RFU 206 RFU 27 VSS 147 VSS 87 RFU 207 RFU 28 PN2 148 SN2 88 VSS 208 VSS 29 /PN2 149 /SN2 89 VSS 209 VSS 30 VSS 150 VSS 90 PS9 210 SS9 31 PN3 151 SN3 91 /PS9 211 /SS9 32 /PN3 152 /SN3 92 VSS 212 VSS 33 VSS 153 VSS 93 PS5 213 SS5 34 PN4 154 SN4 94 /PS5 214 /SS5 35 /PN4 155 /SN4 95 VSS 215 VSS 36 VSS 156 VSS 96 PS6 216 SS6 37 PN5 157 SN5 97 /PS6 217 /SS6 38 /PN5 158 /SN5 98 VSS 218 VSS 39 VSS 159 VSS 99 PS7 219 SS7 40 PN SN /PS7 220 /SS7 41 /PN /SN VSS 221 VSS 42 VSS 162 VSS 102 PS8 222 SS8 43 VSS 163 VSS 103 /PS8 223 /SS8 44 RFU 164 RFU 104 VSS 224 VSS 45 RFU 165 RFU 105 RFU 225 RFU 46 VSS 166 VSS 106 RFU 226 RFU 47 VSS 167 VSS 107 VSS 227 VSS 48 PN SN VDD 228 SCK 49 /PN /SN VDD 229 /SCK 50 VSS 170 VSS 110 VSS 230 VSS 51 PN6 171 SN6 111 VDD 231 VDD 52 /PN6 172 /SN6 112 VDD 232 VDD 53 VSS 173 VSS 113 VDD 233 VDD 54 PN7 174 SN7 114 VSS 234 VSS 55 /PN7 175 /SN7 115 VDD 235 VDD 56 VSS 176 VSS 116 VDD 236 VDD 57 PN8 177 SN8 117 VTT 237 VTT 58 /PN8 178 /SN8 118 SA2 238 VDDSPD Datasheet Version IMM1G72D2FBD4AG

7 Pin Name Pin Name Pin Name Pin Name 59 VSS 179 VSS 119 SDA 239 SA0 60 PN9 180 SN9 120 SCL 240 SA1 Table 7 - Pin Description Pin Name Description Pin Name Description SCK System Clock Input, positive line 1 /Reset AMB reset signal /SCK System Clock Input, negative line 1 VCC PN[13:0] Primary Northbound Data, positive lines VDD /PN[13:0] Primary Northbound Data, negative lines VTT AMB Core Power and AMB Channel Interface Power SDRAM Power and AMB DRAM I/O Power SDRAM Address/Command/Clock Termination Power (VDD/2) PS[9:0] Primary Southbound Data, positive lines VSS Ground /PS[9:0] Primary Southbound Data, negative lines VDDSPD EEPROM Power SN[13:0] /SN[13:0] SS[9:0] /SS[9:0] VID[1:0] DNU, M_Test Secondary Northbound Data, positive lines Secondary Northbound Data, negative lines Secondary Southbound Data, positive lines Secondary Southbound Data, negative lines SDA SCL SA[2:0] EEPROM Data Input / Output EEPROM Clock Input EEPROM Address Inputs, also used select DIMM number in the AMB RFU Reserved for Future use 2 Voltage ID: These pins must be unconnected for DDR2-based Fully Buffered DIMMs. VID[0] is VDD value: OPEN = 1.8V, GND = 1.5V VID[1] is VCC value: OPEN = 1.5V, GND = 1.2V The DNU / M_Test pin provides an external connect on R/Cs A-D for testing the margin of Vref which is produced by a voltage divider on the module. It is not intended to be used in normal system operation and must not be connected (DNU) in a system. This test pin may have other features on future card designs and if it does, will be included in this specification at that time. 1. System Clock Signals SCK and /SCK switch at one half the DRAM CK, /CK frequency 2. Eight pins reserved for forwarded clocks, eight pins reserved for future architecture flexibility Datasheet Version IMM1G72D2FBD4AG

8 Figure 1 Module Dimension 240 Pin DDR2 SDRAM Fully Buffered DIMM A B A B Datasheet Version IMM1G72D2FBD4AG

9 Table 8 - PCB Dimension Symbol MIN NOM MAX A A Basic A Basic A D D Basic D Basic D Basic D Basic e Basic e Basic E Notes: All dimensioning and tolerancing conform to ASME Y14.5M Tolerances for all dimensions ±0.15 unless otherwise specified. All dimensions are in millimeters. Datasheet Version IMM1G72D2FBD4AG

10 Datasheet Version IMM1G72D2FBD4AG Figure 2 Functional Block Diagram (Page 1 of 3) /S1 /S0 U2 U18 0 U1 U17 U4 U20 U3 U D4-D7 2 2 D8-D D12-D15 0 U5 U21 4 D16-D19 U6 U22 U7 U23 U8 U D20-D D24-D D28-D31 4 U33 U CB0-CB3

11 Datasheet Version IMM1G72D2FBD4AG Figure 3 Functional Block Diagram (Page 2 of 3) /S1 /S0 U10 U26 9 D32-D35 U9 U25 U12 U28 U11 U D36-D D44-D47 9 U13 U29 13 D48-D51 U14 U30 U15 U31 U16 U D52-D D56-D D60-D63 13 D40-D43 U35 U CB4-CB7

12 Figure 4 Functional Block Diagram (Page 3 of 3) VTT Terminators VCC B1 VDDSPD E1, B1 VDD U1-U36, B1 VREF U1-U36 VSS U1-U36, E1, B1 All address / command / control / clock VTT D0-D63 PN0-PN13 CB0-CB7 /PN0-/PN PS0-PS /PS0-/PS9 /S0-> (U1-U16,U33,U35) SN0-SN13 CKE0->CKE (U1-U16,U33,U35) /SN0-/SN13 SS0-SS9 /SS0-/SS9 AMB B1 /S1-> (U17-U32,U34,U36) CKE1->CKE (U17-U32,U34,U36) ODT->ODT0 (U1-U36) SCL BA0-BA2 (U1-U36) SDA A0-A15 (U1-U36) SA1-SA2 /RAS (U1-U36) SA0 /CAS (U1-U36) /RESET /WE (U1-U36) SCK, /SCK CK, /CK (U1-U36) SDA SDA VDD VDDSPD SCL SCL E1 WP SA0 SA1 SA2 SA0 SA1 SA2 Datasheet Version IMM1G72D2FBD4AG

13 Electrical Parameter Table 9 Absolute Maximum DC Ratings Parameter Symbol Rating Unit Notes Voltage on V DD pin relative to V SS V DD -1.0V ~ 2.3 V Voltage on V DDQ pin relative to V SS V DDQ -0.5V ~ 2.3 V Voltage on V DDL pin relative to V SS V DDL -0.5V ~ 2.3 V Voltage on any pin relative to V SS V IN, V OUT -0.5V ~ 2.3 V DRAM Storage temperature T STG -55 ~ 100 DRAM Operation temperature (Standard Product) T CASE 0 ~ 85 DRAM Operation temperature (Industrial T CASE -40 ~ 95 o C 2,5,6 Temperature Product) Notes: 1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 Storage Temperature or DRAM operation temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3 VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than 0.6 x VDDQ, when VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV. 4 The Normal Temperature Range specifies the temperatures when all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0-85 C under all operating conditions. 5 The Normal Temperature Range specifies the temperatures when all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between C under all operating conditions. 6 Some applications require operation of the Extended Temperature Range between 85 C and 95 C case temperature. Full Specifications are guaranteed in this range but the following additional conditions apply a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval trefi to 3.9us. b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b). o C o C 1,3 1, ,2 2,4 Datasheet Version IMM1G72D2FBD4AG

14 Table 10 - DC Electrical Characteristics and Operating Conditions Parameter / Condition Symbol Rating Units Notes Min Typ. Max Supply voltage V DD V Supply voltage for I/O V DDQ V Supply voltage for DLL V DDL V Supply voltage for AMB V CC V Input Reference Voltage V REF 0.49 x V DDQ 1.5 x V DDQ 0.51 x V DDQ V Termination Voltage V TT V REF V REF V REF V Notes: 1 VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDL tied together. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. Peak to peak ac noise on VREF may not exceed ± 2% VREF (dc) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in die dc level of VREF ,3 4 Datasheet Version IMM1G72D2FBD4AG

15 For part number IMM1G72D2FBD4AG-A25(I) Table 11 - SPD Information Byte NO. Description Note Hex 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage CRC coverage Byte, SPD Byte Total: 256Byte, SPD Use: 176Byte 1 SPD Revision Rev Key Byte / DRAM Device Type DDR2 SDRAM FB-DIMM 09 3 Voltage Levels of this Assembly Channel 1.5V; 12 DRAM 1.8V 4 SDRAM Addressing No. of Row: 15; No. of Col: 11; No. of Rank: Module Physical Attributes Height: 30.35mm Thickness: Max 8mm 23 6 Module Type / Thickness Fully Buffered DIMM 07 (width: mm) 7 Module Organization 2 Rank / x Fine Timebase Dividend and Divisor 5/2 (2.5ps) 52 9 Medium Timebase Dividend 1/4 (0.25ns) Medium Timebase Divisor 1/4 (0.25ns) SDRAM Minimum Cycle Time (tckmin) 2.5ns 0A 12 SDRAM Maximum Cycle Time (tckmax) 8ns SDRAM /CAS Latencies Supported CL 4, 5, SDRAM Minimum /CAS Latency Time (tcas) 15ns 3C 15 SDRAM Write Recovery Times Supported 2, 3, 4, 5, 6 CLK SDRAM Write Recovery Time (twr) 15ns 3C 17 SDRAM Write Latencies Supported 2, 3, 4, 5, 6, 7, 8 CLK SDRAM Additive Latencies Supported 0, 1, 2, 3, 4 CLK SDRAM Minimum /RAS to /CAS Delay (trcd) 15ns 3C 20 SDRAM Minimum Row Active to Row Active 7.5ns 1E Delay (trrd) 21 SDRAM Minimum Row Precharge Time (trp) 15ns 3C 22 SDRAM Upper Nibbles for tras and trc SDRAM Minimum Active to Precharge Time 45ns B4 (tras) 24 SDRAM Minimum Auto-Refresh to Active/Auto- 50ns C8 Refresh Time (trc) SDRAM Minimum Auto-Refresh to Active/Auto- 195ns 0C 03 Refresh Command Period (trfc) 27 SDRAM Internal Write to Read Command Delay 7.5ns 1E (twtr) 28 SDRAM Internal Read to Precharge Command 7.5ns 1E Delay (trtp) 29 SDRAM Burst Lengths Supported BL 4, SDRAM Terminations Supported 50, 75, 150 ohm SDRAM Drivers Supported Weak Driver SDRAM Average Refresh Interval (trefi) / Double Refresh mode bit / High Temperature self-refresh rate support indication 7.8us (Double above 85 o C) 33 Bits 7:4: Tcasemax Delta. Bits 3:0: DT4R4W Delta 85 o C Thermal resistance of SDRAM device package from top (case) to ambient (Psi T-A SDRAM) at still air condition based on JESD51-2 standard C2 Datasheet Version IMM1G72D2FBD4AG

16 Byte NO. Description Note Hex 35 DT0: Case temperature rise from ambient due to IDD0/activate-precharge operation minus 2.8oC offset temperature DT2N/DT2Q: Case temperature rise from ambient - 00 due to IDD2N/precharge standby operation from UDIMM and due to IDD2Q/precharge quiet standby operation for RDIMM. 37 DT2P: Case temperature rise from ambient due - 00 to IDD2P/precharge power-down operation 38 DT3N: Case temperature rise from ambient due - 00 to IDD3N/active standby operation 39 DT4R/Mode Bit: Bits 7:1 Case temperature rise - 00 from ambient due to IDD4R/page open burst read operation. Bit 0: Mode bit to specify if DT4W is greater or less than DT4R. 40 DT5B: Case temperature rise from ambient due - 00 to IDD5B/burst refresh operation 41 DT7: Case temperature rise from ambient due to - 00 IDD7/bank interleave read mode operation Reserved Reserved FB-DIMM ODT Values Rank0/1 (150ohm) Reserved FB-DIMM Channel Protocols Supported Back-to-Back Access Turnaround Time AMB Read Access Time for DDR (AMB.LINKPARNXT[1:0]=11) 85 AMB Read Access Time for DDR (AMB.LINKPARNXT[1:0]=10) 86 AMB Read Access Time for DDR (AMB.LINKPARNXT[1:0]=01) 87 Thermal Resistance of AMB Package from top - 32 (case) to ambient (Psi T-A AMB) 88 AMB DT Idle_ AMB DT Idle_1-6C 90 AMB DT Idle_2-6C 91 AMB DT Active_1-8B 92 AMB DT Active_ AMB DT L0s Reserved AMB Case Temperature Maximum (Tcase_max) 111 o C Airflow impedance and category bits - 0A 100 Reserved AMB Personality Bytes: Pre-initialization (1) AMB Personality Bytes: Pre-initialization (2) AMB Personality Bytes: Pre-initialization (3) AMB Personality Bytes: Pre-initialization (4) AMB Personality Bytes: Pre-initialization (5) AMB Personality Bytes: Pre-initialization (6) AMB Personality Bytes: Post-initialization (1) AMB Personality Bytes: Post-initialization (2) AMB Personality Bytes: Post-initialization (3) AMB Personality Bytes: Post-initialization (4) AMB Personality Bytes: Post-initialization (5) - 00 Datasheet Version IMM1G72D2FBD4AG

17 Byte NO. Description Note Hex 112 AMB Personality Bytes: Post-initialization (6) AMB Personality Bytes: Post-initialization (7) AMB Personality Bytes: Post-initialization (8) AMB Manufacturer s JEDEC ID Code Reserved Reserved Module ID: Module Manufacturer s JEDEC ID Reserved Reserved Code 119 Module ID: Module Manufacturing Location Reserved Reserved Module ID: Module Manufacturing Date Reserved Reserved Module ID: Module Serial Number Reserved Reserved Cyclical Redundancy Code Module Part Number Reserved Reserved Module Revision Code Reserved Reserved SDRAM Manufacturing s JEDEC ID Code Reserved Reserved Manufacturer s Specific Date Reserved Reserved Open for customer use Reserved Reserved Datasheet Version IMM1G72D2FBD4AG

18 Contents Features 3 Table 1 - Ordering Information for RoHS Compliant Product 4 Table 2 - Temperature Grade 4 Table 3 - Speed Grade 4 Table 4 - Memory Chip Information 4 Part Number Decoder 5 Table 5 - Addressing 5 Table 6 - Pin Assignment 6 Table 7 - Pin Description 7 Figure 1 Module Dimension 240 Pin DDR2 SDRAM Fully Buffered DIMM 8 Table 8 - PCB Dimension 9 Figure 2 Functional Block Diagram (Page 1 of 3) 10 Figure 3 Functional Block Diagram (Page 2 of 3) 11 Figure 4 Functional Block Diagram (Page 3 of 3) 12 Electrical Parameter 13 Table 9 Absolute Maximum DC Ratings 13 Table 10 - DC Electrical Characteristics and Operating Conditions 14 Table 11 - SPD Information 15 Contents 18 List of Tables 19 List of Figures 19 Datasheet Version IMM1G72D2FBD4AG

19 List of Tables Table 1 - Ordering Information for RoHS Compliant Product 4 Table 2 - Temperature Grade 4 Table 3 - Speed Grade 4 Table 4 - Memory Chip Information 4 Table 5 - Addressing 5 Table 6 - Pin Assignment 6 Table 7 - Pin Description 7 Table 8 - PCB Dimension 9 Table 9 Absolute Maximum DC Ratings 13 Table 10 - DC Electrical Characteristics and Operating Conditions 14 Table 11 - SPD Information 15 List of Figures Figure 1 Module Dimension 240 Pin DDR2 SDRAM Fully Buffered DIMM 8 Figure 2 Functional Block Diagram (Page 1 of 3) 10 Figure 3 Functional Block Diagram (Page 2 of 3) 11 Figure 4 Functional Block Diagram (Page 3 of 3) 12 Datasheet Version IMM1G72D2FBD4AG