RML1531MH48D8F-667A. Ver1.0/Oct,05 1/8

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1 DESCRIPTION The Ramaxel RML1531MH48D8F memory module family are low profile Unbuffered DIMM modules with 30.48mm height based DDR2 technology. DIMMs are available as ECC (x72) modules. The module family based on 18 (x72) x8 DDR2 DRAM components, and the DIMMs feature serial presence detect based on a serial EEPROM device. FEATURE 240-pin Dual-in-line DDR2 memory module. JEDEC Standard with 1.8 V (±0.1 V) power supply 2 Rank Organizations based x8 DDR2 DRAM components Fast data transfer rates: PC Differential data strobe (DQS, DQS#) option Differential clock inputs (CK, CK#) Commands entered on each rising CK edge Four-bit pre-fetch architecture DQS edge-aligned with data for READs DQS center-aligned with data for WRITEs DLL to align DQ and DQS transitions with CK Data mask (DM) for masking write data Programmable burst lengths: 4 or 8 Adjustable data-output drive strength Concurrent auto pre-charge option is supported Auto Refresh (CBR) and Self Refresh Mode Off-chip driver (OCD) impedance calibration On-die termination (ODT) Serial Presence Detect (SPD) with EEPROM Gold edge contacts Ver1.0/Oct,05 1/8

2 PART NUMBER DECODER Ramaxel Module R M L M H 48 D 8 F- 667 Module Type L:240pin DDR2 Unbufferd DIMM Speed: 667: PC PCB Number 800: PC DRAM Package: ECC: F: FBGA 0: Without ECC W: WBGA 1: With ECC DRAM Vendor: Module Density M: Micron 4: 128MB H: Hynix 5: 256MB S: Infineon 6: 512MB L: Longmax 7: 1GB E: Elpida 8: 2GB SSTL_18 DRAM DIE Revision (Refer to DRAM manufacturer) DRAM Density: 18: 128Mb (16M*8) 28: 256Mb (32M*8) 38: 512Mb (64M*8) 48: 1Gb (128M*8) Ver1.0/Oct,05 2/8

3 PINOUT, PIN LOCATION and FUNCTIONAL DESCRIPTION PINOUT Front Side Back Side PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 1 Vref 31 DQ19 61 A4 91 Vss 2 Vss 32 Vss 62 VDDQ 92 DQS5# 3 DQ0 33 DQ24 63 A2 93 DQS5 4 DQ1 34 DQ25 64 VDD 94 Vss 5 Vss 35 Vss 65 Vss 95 DQ42 6 DQS0# 36 DQS3# 66 Vss 96 DQ43 7 DQS0 37 DQS3 67 VDD 97 Vss 8 Vss 38 Vss 68 NC 98 DQ48 9 DQ2 39 DQ26 69 VDD 99 DQ49 10 DQ3 40 DQ27 70 A10/AP 100 Vss 11 Vss 41 Vss 71 BA0 101 SA2 12 DQ8 42 CB0 72 VDDQ 102 NC 13 DQ9 43 CB1 73 WE# 103 Vss 14 Vss 44 Vss 74 CAS# 104 DQS6# 15 DQS1# 45 DQS8# 75 VDDQ 105 DQS6 16 DQS1 46 DQS8 76 NC 106 Vss 17 Vss 47 Vss 77 NC 107 DQ50 18 NC 48 CB2 78 VDDQ 108 DQ51 19 NC 49 CB3 79 Vss 109 Vss 20 Vss 50 Vss 80 DQ DQ56 21 DQ10 51 VDDQ 81 DQ DQ57 22 DQ11 52 CKE0 82 Vss 112 Vss 23 Vss 53 VDD 83 DQS4# 113 DQS7# 24 DQ16 54 BA2* 84 DQS4 114 DQS7 25 DQ17 55 NC 85 Vss 115 Vss 26 Vss 56 VDDQ 86 DQ DQ58 27 DQS2# 57 A11 87 DQ DQ59 28 DQS2 58 A7 88 Vss 118 Vss 29 Vss 59 VDD 89 DQ SDA 30 DQ18 60 A5 90 DQ SCL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 121 Vss 151 Vss 181 VDDQ 211 DM5 122 DQ4 152 DQ A3 212 NC 123 DQ5 153 DQ A1 213 Vss 124 Vss 154 Vss 184 VDD 214 DQ DM0 155 DM3 185 CK0 215 DQ NC 156 NC 186 CK0# 216 Vss 127 Vss 157 Vss 187 VDD 217 DQ DQ6 158 DQ A0 218 DQ DQ7 159 DQ VDD 219 Vss 130 Vss 160 Vss 190 BA1 220 CK2 131 DQ CB4 191 VDDQ 221 CK2# 132 DQ CB5 192 RAS# 222 Vss 133 Vss 163 Vss 193 S0# 223 DM6 134 DM1 164 DM8 194 VDDQ 224 NC 135 NC 165 NC 195 ODT0 225 Vss 136 Vss 166 Vss 196 A13* 226 DQ CK1 167 CB6 197 VDD 227 DQ CK1# 168 CB7 198 Vss 228 Vss 139 Vss 169 Vss 199 DQ DQ DQ VDDQ 200 DQ DQ DQ NC 201 Vss 231 Vss 142 Vss 172 VDD 202 DM4 232 DM7 143 DQ A15* 203 NC 233 NC 144 DQ A14* 204 Vss 234 Vss 145 Vss 175 VDDQ 205 DQ DQ DM2 176 A DQ DQ NC 177 A9 207 Vss 237 Vss 148 Vss 178 VDD 208 DQ VDDSPD 149 DQ A8 209 DQ SA0 150 DQ A6 210 Vss 240 SA1 Notes: (1)CB0-7 Pins are the check bits of DQs for ECC Unbuffered DIMMs. (2)BA2/A13/A14/A15 are used for high density memory modules. Ver1.0/Oct,05 3/8

4 PIN LOCATION (Followed JEDEC standard MO237) FUNCTIONAL DESCRIPTION Pin Name Description Pin Name Description A[15:0] Row and Column Address Inputs CB[7:0] ECC Check Pins BA[2:0] SDRAM Bank Select DQS[8:0] Write/Read Data Strobes (Positive) A10/AP Column Address Input for Auto Precharge DQS[8:0]# Write/Read Data Strobes (Negative) CK[2:0] Clock Input (Positive) DM[8:0] Data Input Mask CK[2:0]# Clock Input (Negative) SCL Serial Bus Clock RAS# Row Address Strobe SDA Serial Bus Data Input/Output CAS# Column Address Strobe SA[2:0] Slave Address Select WE# Write Enable VDD Power Supply Pin S[1:0] Rank Select VDDQ Power Supply Pin CKE[1:0] Clock Enable Vref I/O Reference Supply ODT[1:0] Active Termination Control Lines Vss GND DQ[63:0] Data Input/Output VDDSPD Power Supply for EEPROM RESET# Register and PLL Reset NC No Connection Notes (1)A15, A14, A13/BA2 are used on high density DIMMs only. (2)CKE1,ODT1,S1# are used on 2 ranks DIMMs only. (3)RESET# is used on Registered DIMMs only. (4)CB[7:0],DQS8,DQS8#,DM8 are used on ECC DIMMs only. (5)CK1,CK2,CK1#,CK2# are used on Unbuffered DIMMs only. Ver1.0/Oct,05 4/8

5 COMMAND TRUTH TABLE Function CKE(CKE1 or CKE0) Previous Cycle Current Cycle CS#(S0# or S1#) RAS# CAS# WE# BA[2:0] A[13:11] A10 A[9:0] Notes Mode Register Set H H L L L L BA OP code 1,2 Refresh H H L L L H X X X X 1 Self-Refresh Entry H L L L L H X X X X 1 Self-Refresh Exit L H H X X X X X X X 1,7 L H H H Single Device Bank Precharge H H L L H L BA X L X 1,2 All Devices Banks Precharge H H L L H L BA X H X 1 Device Bank Active H H L L H H BA Row Address 1,2 Write Column L Column 1,2,3 H H L H L L BA Write with Auto-Precharge Address H Address 1,2,3 Read Column L Column 1,2,3 H H L H L H BA Read with Auto-Precharge Address H Address 1,2,3 No Operation H X L H H H X X X X 1 Device Deselect H X H X X X X X X X 1 Power-down Entry Power-down Exit Notes: (3)Burst reads or writes at BL=4 cannot be terminated or interrupted. (4)The Power Down Mode does not perform any refresh operations. (5)The state of ODT does not affect the states described in this table. (6)"X" means "H" or "L",but it must be a defined logic level. (7)Self refresh exit is asynchronous. H L L H H X X X X X X X L H H H X X X X H X X X X X X X L H H H X X X X (1)All DDR2 SDRAM commands are defined by states of #CS,#RAS,#CAS,#WE and CKE at the rising edge of the clock. (2)Bank addresses BA[2:0] determine which bank is to be operated upon.for (E)MRS BA[[2:0] selects an (Extended) Mode Register. 1,4 1,4 Ver1.0/Oct,05 5/8

6 BLOCK DIAGRAM Ver1.0/Oct,05 6/8

7 ABSOLUTE MAXIMUM RATING Symbol Parameter Rating Units Notes VDD Voltage on VDD pin relative to Vss -1.0V ~ 2.3V V 1 VDDQ Voltage on VDDQ pin relative to Vss -0.5V ~ 2.3V V 1 VDDL Voltage on VDDL pin relative to Vss -0.5V ~ 2.3V V 1 VIN, VOUT Voltage on any pin relative to Vss -0.5V ~ 2.3V V 1 TSTG Storage Temperature -55 to NOTE 1 : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not impled. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING TEMPERATURE and DC/AC OPERATING CONDITION OPERATING TEMPERATURE Operating Temperature(ambient) Rating: Note: The component maximum case temperature (Tc) shall not exceed the value specified in the DDR2 DRAM component specification: DC/AC OPERATING CONDITION Parameter Symbol Limit Level Min. Max. Units Notes Device Power Supply Vdd V Device I/O Power Supply Vddq V 1 Input Reference Voltage Vref 0.49*Vddq 0.51*Vddq V 2 EEPROM Power Supply Vspd V I/O Termination Power Supply Vtt Vref-40 Vref+40 mv 3 Input Logic High (DC) Vih(dc) Vref+125 Vddq+300 mv Input Logic Low (DC) Vil(dc) -300 Vref-125 mv Input Logic High (AC) Vih(ac) Vref+250 mv Input Logic Low (AC) Vil(ac) Vref-250 mv Notes: (1)Under all conditions,vddq must be less than or equal to Vdd. (2)Peak to peak AC noise on Vref may not exceed ±2%.Vref is also expected to track noise variations on Vddq (3)Vtt is not applied to the module,vtt is a system supply for signal termination resistors,and it is expected to be set equal to Vref and track noise variations in the DC leval of Vref. Ver1.0/Oct,05 7/8

8 DIMENSIONS (Unit: mil) Ver1.0/Oct,05 8/8