Designing Embedded Processors in FPGAs
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1
2 Designing Embedded Processors in FPGAs 2002
3 Agenda Industrial Control Systems Concept Implementation Summary & Conclusions
4 Industrial Control Systems Typically Low Volume Many Variations Required High Customization Number of Attached Sensors Types of Attached Sensors Required User Interface Needs Storage & Recording Needs Touch Panel Displays Increasing Use to Reduce Cost Industrial Equipment Touch Panel Display
5 Concept Flexibility Need to Easily Modify Design Allowing for Customization or Feature Enhancements Reaction to Customer Needs Changing Solution Needs: New Sensors/ New Control Time to Market Capability to Complete Development Work for Solution in Time to Meet Specific Market Window Rapid Design of New Control Solutions Reusability Ability to Reuse Much of Existing Design As Starting Point for New Solution
6 Concept Solution Requirements Minimal Cost Overall Solution Measured Not Only By Cost of Components, But Cost of Board The Lower the Solution Cost, The Easier It becomes to Win Business & Sustain Margins Manufacturability Can Existing Implementation Be Maintained If Devices Fail i.e., Is Supply Guaranteed? Device Qualification If Company Has Stringent Device Qualification Needs, Advantages of Utilizing Single Device for Many Applications Becomes Apparent
7 Conceptual Solution Industrial Control Flow Diagram Hardware Block Diagram Software System
8 Industrial Control Flow Diagram Example: PID Controller Typical Transfer Function Y U 2 ( s) K Ds + K Ps + K I = 2 () s ( m + K D ) s + ( b + K P ) s + K I ϑ + - KP KI KD <=UL >=LL Lag Process
9 Hardware Block Diagram Hardware Block Diagram Control Processor Memory Custom I/F Custom I/F UART UART SPI SPI I2C I2C IDE Ethernet LCD Touch Panel Storage Control Devices/Sensors
10 Software System User Applications HTTP Server HTML Browser Telnet Server Telnet Client SMB Server SMB Client Window Server CGI Apps Custom App Operating System Graphical Services Networking Services File System Services Inter-Process Services Device Drivers Task Services Kernel Touch Panel LCD Interface Ethernet IDE I2C SPI UART Custom Interface
11 Implementation Selected System Components Cyclone FPGA Nios Embedded Processor µclinux Software Solution Development
12 Cyclone FPGA Advantages High-Density, Full-Featured FPGA Maximizes Flexibility, Avoids Obsolescence & Device Qualification Issues Low Cost Reduces Production Costs without Reducing Solution Functionality High Performance Maximizes Longevity of Solution & Functional Economy Migration Path Enables Same Board to Be Used for Different Solutions Enables High Levels of Integration Minimizes Component Count & Board Costs
13 Powerful Cyclone Functionality External Memory Interface Dedicated SDRAM & FCRAM Interface Circuitry 266-Mbps Performance Differential Signaling 311-Mbps Performance Up to 129 Channels Embedded Memory Up to 294,912 RAM Bits 200-MHz Performance Phase-Locked Loops System Clock Management Features Up to 2 PLLs
14 Nios Processor Systems Not Just A Processor Complete Microprocessor Subsystem Processor Core Plus Peripherals & Memory Interfaces Custom Peripherals Custom Instructions Simultaneous Multi-Master Avalon Bus Connects All Components Multiprocessor Systems Possible PIO: Parallel I/O SPI: Serial Peripheral Interface Nios Custom Logic Nios Nios Nios CPU On-Chip ROM On-Chip RAM Avalon Bus UART PIO Timer SPI SDRAM Controller Your Design Here
15 Nios System Architecture Nios CPU On-Chip Debug Core Off-Chip Software Trace Memory Instr. Data Address decoder Interrupt Controller Wait State Generation Data In Multiplexer Master Arbitration Avalon Master/ Slave Port Interfaces UART 0 Timer 0 SPI 0 GPIO 0 DMA 0 Memory Interface UART n Timer n SPI n GPIO n DMA n Dynamic Bus Sizing Avalon Bus Module User-Defined Interface
16 Peripheral Components Memory Interface On-Chip RAM, ROM Off-Chip SDRAM Controller SSRAM SRAM Flash, ROM DMA Controller Memory-Peripheral Memory-Memory Peripheral-Peripheral Bridges AHB to Avalon Bus Bridge Parallel I/O (PIO) Registers General-Purpose I/O Registers (PIO) Input Output Bidirectional User-Defined Interface Serial I/O UART SPI Timer Simple Timer Pulse Generator Watchdog Timer
17 Nios Embedded Processor Standard RISC Components Optimized for Size & Performance in PLDs Fully Synchronous Interface Instruction Address Instruction In 16 Instruction Fetch & Decode Program Counter Operand Fetch & Store ALU Read/Write Byte Enable Data Out Data Address Clock Wait Reset Clock Enable General Purpose Register File M U X Interrupt Control 6 Data In IRQ IRQ Number IRQ: Interrupt Request ALU: Arithmetic Logic Unit
18 Simultaneous Multi-Master Bus Master 1 (Nios CPU) I D Master 2 (100Base-T) Master n (100Base-T) Multi-Master Avalon Bus Avalon Bus Avalon Bus Avalon Bus Arbiter Arbiter Program Memory I/O 1 I/O 2 Data Memory 1 Data Memory n
19 Simultaneous Multi-Master Bus Master 1 (Nios CPU) I D Master 2 (100Base-T) Master n (100Base-T) Fetch Code Receive Packets Send Packets Avalon Bus Avalon Bus Avalon Bus Arbiter Arbiter Program Memory I/O 1 I/O 2 Data Memory 1 Data Memory n
20 State Machine/PLC Replacement System Development Complexity Development Time Resource Utilization Design Flexibility A High High High Low B Lower Lower Lower Higher System A Circuit 1 Circuit 2 System B Circuit 1 Circuit 2 Control Circuit 3 Control Control Circuit 4 Control Nios Circuit 3 Circuit 4
21 Nios Embedded Processor Advantages Highly Configurable 16-,32-Bit Variants, Add Peripherals as Required Optimized For PLD Implementation Minimal Size, Reduces Device Costs Royalty Free No per Product Fee Low Cost Minimal Investment Obsolescence Proof Migration to New Altera Device Families Longevity Associated with Altera Device Families
22 µclinux Software Linux 2.4 C++ Support μclibc Embedded Library Source Code Provided SOPC Builder Support Fully Supported in Cygwin Environment
23 µclinux Software Advantages Open Source Environment Availability of Solutions Simplifies Development HTTP Server, HTTP Browser, Telnet Server, Telnet Client Driver Availability Large Driver Resource Ability to Integrate Custom Drivers Integration with Altera Tools Quartus Software SOPC Builder
24 Solution Development Example System: Cookie Factory Network Control System Touch Panel Display Program # Temp Speed System # STOP RESET Motor Control Digital Sensor
25 Solution Development Cyclone Logic Element Implementation Cost Block LEs Block LEs 16-Bit Nios 900-1,100 IDE Interface LCD I/F 100-2,500 Customer Interface 200 Touch Panel I/F 200-5,000 UART, SPI, I2C Ethernet 100-2,500 CAN 100
26 Solution Development Memory Control Processor Cyclone UART UART UART UART IDE Ethernet I/F LCD I/F T. Panel I/F LCD Touch Panel Storage Memory
27 Solution Development Function Amount LE Cost Total Processor 1 1,200 1,200 UART ,200 Touch Panel Interface LCD Interface Ethernet Interface IDE Total 3,800
28 Solution Development EP1C6 Has 5,980 Logic Elements Solution Requires 3,800 Logic Elements Device 63.5% Utilized Memory Requirements EP1C6 Has 92,160 RAM Bits External Memory Only for LCD Image Memory 614,400 RAM Bits Required for QVGA
29 Solution Development Processor Library Peripheral Library Hardware Development EDIF Netlist HDL Source Files Testbench SOPC Builder GUI Configure Processor Select & Configure Peripherals, IP Connect Blocks Generate Custom Instructions IP Modules Software Development C Header files Custom Library Peripheral Drivers Synthesis & Fitter Hardware Configuration File Verification & Debug Executable Code GNUPro Compiler User Design JTAG,Serial, or Ethernet User Code Other IP Blocks Quartus II Altera PLD On-Chip Debug Software Trace Hard Breakpoints SignalTap II Libraries RTOS GNUPro Tools
30 SOPC Builder Design Tool System Customization Component Integration Software Generation System Verification IP Testbench Software User Logic
31 SoPC Builder - Customization Pool of SOPC Builder-Ready Components Communications DSP User Created in DSP Builder Bus Interfaces Bridges Processors Nios and ARM Web-Based IP Deployment
32 SoPC Builder - Customization Table of Active Components Configure Each Component Interrupt Request (IRQ) Base Address Hardware Parameters Software Parameters Wizard-Based Configuration
33 SoPC Builder - Integration Bus Connection Patch Panel Multi-Master Bus Slave-Side Arbitration Optimized for Throughput Bus Bridging AMBA Advanced High-Performance Bus (AHB) Avalon Bus Atlantic Interface PCI
34 Nios OS / RTOS Support Provider Accelerated Technology Mapusoft Technologies Microtronix Shugyo Design MiSPO Co., Ltd. Product Nucleus PLUS OSChanger µclinux KROS NORTi Royalty-Free, Source-Available RTOS Tool to Convert psos / VxWorks Applications to Nucleus PLUS Open-Source OS Description Small-Footprint, Royalty-Free, POSIX- Compliant RTOS µitron 4.0-Compatible Real-Time Kernel
35 Nios Debug Solutions Provider Viosoft Microtronix Microtronix Sophia Systems Red Hat Product Arriba! Debugger Module OCD Solutions Kit WatchPoint GDB / Insight* IDE with Integrated Support for Nios On-Chip Debug Module - Hardware Breakpoints & Processor Trace External Memory Daughter Card for Use as Software Trace Capture Buffer Insight (gdb) Debugger Enhanced to Support Hard Breakpoints & Software Trace Full-Featured Debug Environment with Advanced On-Chip Debug Support Software Debugger Description Altera Tracelink* * Included in Nios Development Kit Interface to Nios On-Chip Debug Module Hardware Breakpoints & Processor Trace
36 Nios Development Kits Altera 10/100 Ethernet Development Kit PCI Development Kit 32-Bit 33-MHz PCI Master/Target PCI Bus Hosting Features Third Party Linux Development Kit IDE Interface Compact Flash SDRAM Controller VGA/LCD Touchscreen ADC/DAC Analog Module ACEX EP1K100 Development Kit The List Keeps Growing...
37 Other Industrial Applications 2002
38 Factory Automation System Video Input Video Input Video Input Buffer Memory Buffer Memory Buffer Memory FIR Filter 32-Bit Nios Processor Image to Data Conversion UART Profibus Controller Recognition Module System in Cyclone Host System
39 Process Control System Host System PHY Ethernet MAC 10/100 Receiver Module Measurement Device Profibus Controller A/D Converter Flash Memory EPROMS Clock 32-Bit Nios Processor Bus Interface 12C UART CAN Controller & Interface Automation System System in Cyclone
40 Network Test Equipment System 10/100 10/100 10/100 PHY PHY PHY Configuration Control Backplane Control Test Chassis 10/100 10/100 Ethernet PHY PHY MAC Network Traffic Generator Network Traffic Capture & Analysis 32-Bit Nios Processor ROM RAM DRAM System in Cyclone
41 Summary & Conclusions Provides Best All-Round Solution Addresses Major Design & Implementation Issues Design Considerations Flexibility Time to Market Reusability Solution Requirements Minimal Cost Manufacturability Device Qualification Remote Accessibility Multiple Applications
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