Technology Roadmap 2002

Transcription

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2 2002 Technology Roadmap

3 Agenda Investing in Our Future Advanced Process Technology Rising Costs of ASIC Development Core Technology Improvements Product Family Roadmaps Development Tools Programmable Systems

4 2002 Investing in Our Future

5 Revenue & R&D Investment Continued Investment in New Products 30% 25% 20% $M % R&D % Reduces with Revenue Growth % 5% 0% $M Revenue $M Revenue Projected R&D %

6 Product Development Process Technology Interconnect Structure Logic, Memory, I/O Hardware Acceleration Architecture Development Customer Feedback Requirements SOPC Value Features, Pricing Power, Packaging SOPC Quartus Development Tools Design Methodology Synthesis, Simulation Verification, Debug IP Integration Hard vs. Soft Functions Cost, Performance, Power, Complexity Stability

7 Accelerated Architecture Development 15 Months October 2001 Project Concept June 2002 Requirements Refined & Architecture Defined Beta Software December 2002 First Silicon April 2002 Customer Requirements Defined September 2002 Design & Layout Complete Over 60% of Time Invested with Customers!

8 Advanced Process Technology 2002

9 TSMC Roadmap Outpacing ITRS Drawn Gate Width (Microns) µm 0.15 µm 0.13 µm TSMC ITRS* Roadmap µm (90 nm) nm Silicon on Insulator & Hi-K Dielectric 45 nm Source: *International Technology Roadmap for Semiconductors 2001 TSMC 2002 Technology Seminar

10 0.13µm Status Process 9 Layers of Metal Copper / FSG High Performance Device Lithography: 248nm / 193nm Altera Ramp Up 9 Months Production APEX II Stratix: 4 Products Already Shipped 1S80 ~ 230 Million Transistors

11 Stratix 9-Layer Copper Interconnect

12 Stratix Transistor Leff 90nm

13 90nm Status Process Up to 10 Layers Of Copper Second Gen. Low-k (K < 3) Vcc: 1.2V (16A Tox) Lithography: 193nm Project Status Started In May 2001 Actively Optimizing Process with TSMC Process Available Early 2003 Production Targeted 2H mm Status Development & Qualification Completed in 2001 Production Ready for as Demand Increases Provide Cost Reduction (Lower Defect Density)

14 Technology Integration 100M 10M 1M 100K 10K 1K Double Density Every 2 Years 4, , Classic EPM900 APEX20400 FLEX10K100 Pentium 486 Pro PII MAX5192 Stratix1S80 APEX20K1500 FLEX81188 P3 P4 Stratix 1S80 230M Transistors

15 Rising Costs of ASIC Development 2002

16 Dramatic Mask Cost Increase µm Migration to Extreme Ultraviolet 4.0 Drawn Gate Width (Microns) µm 0.13 µm TSMC µm (90 nm) SOI nm 45 nm $M Source: International Technology Roadmap for Semiconductors 2001 TSMC 2002 Technology Seminar

17 Increasing Development Cost Total Development Cost (M$) In 5 Years Advanced Technology Development >$20M Design & Verification Layout Test Mask µm 0.15 µm 0.13 µm 90 nm 65 nm 45 nm

18 Increased Market Opportunities ASIC Stratix ASSP Rising Technology & Development Costs Favour SOPC Design

19 Core Technology Improvements 2002

20 Logic Resource Growth Roadmap Next Generation 35,000 30,000 Logic Elements (K) K250A 10K130V 20K600E 20K1500E Stratix 1S80 2A70 Stratix 1S120 Stratix II 25,000 20,000 15,000 10,000 5,000 RAM Bits (K)

21 Core Logic Evolution Performance FLEX 8000 APEX 20K Enhanced Memory Features Fast Arithemetic Functions DSP/COMM Blocks DDRII Additional IO Standards 1 Gbps LVDS / DPA 6.5 Gbps HSSI Mercury Stratix Stratix II Tri-Matrix Memory Enhanced PLLs DSP/MAC Blocks On-Chip Termination 840 Mbps LVDS Hierarchical Clocks

22 LUT Core Performance Roadmap Typical Core Performance (MHz) FLEX 10KA 2X Performance Every 3 Years Process Enhancements Architectural Enhancements FLEX 10KE APEX 20K APEX II Stratix Stratix II Next Generation

23 High-Speed Interface Chip- to- Chip Backplane Line Card Interconnect PL2 I/O Interconnect PCI PL3 HyperTransport RapidIO (Parallel) PL4 1-Gigabit Clock Data Recovery (CDR) Wall 3GIO RapidIO (Serial) PL Gbps 16 Channels < 150 Mbps 1.25 Gbps 2.5 to Gbps 5-10 Gbps Line Side (LAN) Gigabit Ethernet 1.25 Gbps 10-Gigabit Ethernet Gbps 4 Channels 40- Gigabit Ethernet

24 High-Speed I/O Roadmap Architecture Channel Performance Electrical Standards Bus Protocols 1.25 Gbps Gbps 6 Gbps 12 Gbps 1.25-Gbps CDR 1.25-Gbps LVDS 1.25-Gbps PCML 1.25-Gbps LVPECL 1-Gbps HyperTransport 250-MHz HSTL PCI-X SPI-4 Phase 2 Gigabit Ethernet 1-Gbps Fibre Channel 1-Gbps RapidIO 415-Mbps Utopia IV 200-MHz CSIX Stratix GX Gbps LVDS With CDR RapidIO Serial/Parallel 1G, 2G Fibre Channel InfiniBand 10G Ethernet (XAUI) Lineside Backplane SONET Backplane Stratix II GX Gbps CML With CDR RapidIO FChannel InfiniBand SPI5, 3GIO SONNET Next Generation PAM Chip-Chip Backplane Emerging High Speed Standards

25 Integrated Memory High Speed Data Processing & Communications Faster Wire Speeds High Port Integration More Latency Example: Stratix EP1S80 9 Mega RAMs 86G Bits/Sec 314 Pins /RAM 2800 Pins Provide Same External Memory Bandwidth Write 144 Address 11 Control MHZ Operation Mega RAM 144 Bits x 4K Words Read 144 Address 11 Control 2

26 Embedded Memory Roadmap Architecture Stratix Stratix II Next Generation Features Performance Technology True Dual-Port Mode Packing Mode Mixed Width Mode 250 MHz SRAM Embedded Shift Register Mode DDR Mixed Width Mode Three Sizes of Blocks Byte Enable Mixed Clock Mode Preload 300 MHz 550 MHz SRAM Embedded Error Control Circuitry (ECC) DDR Tri-Matrix SRAM Embedded CAMs Embedded Error Control Circuitry (ECC) High Density Storage 750 MHz SRAM Embedded DRAM

27 Excalibur Nios Roadmap Processor Performance Features Version 2.0 Version MHz / 40 DMIPS 150 MHz / 75 DMIPS 250 MHz / 167 DMIPS Simultaneous Multi- Master Bus Intelligent Peripherals User-Defined Instructions SDRAM Controller 10/100 Ethernet I/F PCI MT32 Software IDE On-Chip Debug Software Trace Linux, ATI Nucleus Speed / Size Optimizations Communication Controller HDLC, T1/E1 Framer Time-Slot Assigner Integrated MMU Configurable On-Chip Cache High-Speed Memory Interface C-Level Simulation Hardware & Software Multi-Processor Support Inter-Processor Communication Software Debug Application-Specific Processor Extensions II System Profiler Hardware & Software Optimized Extensions Based on Target Application (Critical Loop) Speed Enhancements Additional Peripherals

28 Packaging Technology Roadmap 0.18 µm 0.15 µm 0.13 µm 90 nm 65/45 nm Wire-Bonded BGAs FlipChip BGAs Multiple Stacked Die MCMs & Embedded Passives LRC 1.27 mm 1.0 mm 0.8 mm 0.5 mm PCB

29 Pricing Roadmap FPGA Sales / Logic Elements (Normalized to 2000) /10 Price in Four Years with Twice the Features Reduced Logic Element Pricing Continued Use of New Processes 300mm Wafers Improved Redundancy Technology Architecture Efficiencies Next Generation Continue at > 25% Lower per Year

30 Product Family Roadmaps 2002

31 Altera s General-Purpose Product Portfolio Relative Cost Relative Density & Features Addressing Features & Cost

32 Altera FPGA Roadmap Performance Performance IP Integration Cost-Effective APEX 0.18µ / 0.15µ / 0.13µ f MAX = MHz Max Density = 70K LE Stratix 0.13µ f MAX = MHz Maximum Density = 100K LE APEX Embedded RAM = 1.2 MBit Maximum Transceiver = 1.25Gbps Stratix II 90nm f MAX = MHz Max Density = 170K LE Memory = 16 Mbit Maximum Transceiver = 6.5 Gbps APEX E Mercury ACEX Stratix Tri-Matrix Memory = 10 Mbit Maximum Transceiver = Gbps APEX II Excalibur Next Gen. Stratix E Stratix GX Cyclone Excalibur II

33 Altera CPLD Roadmap Cost Reduction & Flexibility 5V Core 3.3V Core 2.5V Core 1.8V Core MAX µ/0.3/0.22µ Process ISP tpd = 3.5 ns Core = 5 / 3.3 / 2.5V MAX 3000 IO Tolerance = 5 / 3.3 / 2.5 / 1.8V 0.3µ Process ISP MAX3000A Tpd= 4.5 ns Core = 3.3V IO Tolerance =5 / 3.3 / 2.5V A 7000B Future MAX 0.18µ Process ISP Tpd = 3.5 ns Core = 3.3 / 2.5 / 1.8V IO Tol. = 5 / 3.3 / 2.5 / 1.8V Nex Gen

34 Altera HardCopy Roadmap Cost Reduction & Flexibility Performance Processor Transceiver APEX HardCopy APEXE 1500/1000 APEXE 600/400 Stratix Function & Pin Compatible Stratix 1S Package Options Faster Low Power APEXE APEXII Stratix Stratix II 90nm f MAX = MHz Max Density = 170K LE Memory = 16 Mbit max. Transceiver = 6.5Gbps GX

35 POP QUIZ

36 Pop Quiz Stratix 의생산공정과 Core Voltage 로서맞는것은? um, 2.5V um, 1.8V um, 1.8V um, 1.5V

37 Pop Quiz Stratix 의생산공정과 Core Voltage 로서맞는것은? um, 2.5V um, 1.8V um, 1.8V um, 1.5V

38 2002 Development Tools

39 Tools Roadmap Altera Will Continue to Focus on Areas Where We Add Most Value Continue to Partner with Leading 3 rd Parties Where They Provide Incremental Expertise & Focus SOPC Builder & System Design Automation Will Be Our Major Focus

40 SOPC Design Tools SOPC Builder CPU UART Timer RAM I/F Architecture User Logic IP User DSP IP PLD Fabric

41 SOPC Design Tools SOPC Builder Traditional Synthesis Flow Flow DSP DSP Builder CPU User Logic User DSP DSP IP DSP IP UART Timer PLD Fabric RAM I/F Architecture IP IP Embedded SW SW Toolset Mega Mega Wizard Wizard

42 SOPC 3.0 Builder Build Custom Companion Chip for Your Processor-Based System with SOPC Builder Interface to Popular Microprocessors PowerPC TI DSP PCI Custom Peripheral Content Communications IP Signal Processing Algorithms Memory Interfaces Hardware Acceleration Functions Security IP Image Processing Traffic Management / Routing Algorithms

43 SOPC Builder Roadmap Q Q1 Q Q3 Q4 Quartus II v 2.2 SOPC Builder 2.7 Quartus II v. 3.0 SOPC Builder 3.0 Native Synthesis Support Cyclone Device Support External Device Bus Standards PowerPC (60x Bus) TI C6X PCI IP Bus Standards AMBA PVCI Wishbone DSP Builder Integration Atlantic Bus Support SignalTap II Support Web Update

44 Programmable Systems 2002

45 Programmable System Reconfiguration In Production Today Using Altera FPGAs Requires Complex Hardware/Software Support Group 1 Group 2 Group 3 Group 4 1 Year Months Days - Hours Mins-100mS 1ms-1us System Upgrades Bug Fixes Feature Upgrades Remote System Monitor Reboot & Upgrade Multifunction Platform for Different Users Reuse Hardware to Perform Multi- Functions Reduce Redundant Hardware Costs Reconfigurable Computing Context Switch Based Upon Function Under Real-Time Software Control

46 Re-Configurable Solutions Increasing Use of Remote System Updates FPGA Images Uploaded Over Internet or Private Network Mainly Using Ethernet Both System Upgrades & Remote Monitoring Using Programmability of FPGAs Bug Fixes, System Upgrades, New Features Significant Cost Advantages over Technician Visit % Network Attached Applications Using Remote Updates Programmable Logic Differentiates Production Solution Reconfiguration %

47 Future System Design DSP SRAM Flash DRAM DRAM Back Plane ASSP BP I/F ASSP BP I/F FPGA Queue Traffic ASIC Policy Engine Network Packet Processor ASSP Framer O/E O/E Line Side Interface

48 Future System Design Microprocesor DSPs Memory SOPC Analog ASIC & ASSP for High-Volume Projects Back Plane FPGA BP I/F FPGA BP I/F DSP FPGA Queue Traffic FPGA Policy Engine SRAM Flash DRAM Network Packet Processor FPGA Framer O/E O/E DRAM

49 Conclusions Altera Continues to Innovate & Deliver Compelling SOPC Solutions Focused on Complete Solutions Programmable Device Families Leading Design Automation Tools Broad Range of IP Comprehensive Worldwide Technical Support Performance, Price, Integration Will Dramatically Expand SOPC Market Altera SOPC Solution for Rapid Growth