Open Innovation with Power8

Transcription

1 2011 IBM Power Systems Technical University October Fontainebleau Miami Beach Miami, FL IBM Open Innovation with Power8 Jeffrey Stuecheli Power Processor Development Copyright IBM Corporation 2013 Materials may not be reproduced in whole or in part without the prior written permission of IBM. 5.3

2 Open Innovation with Power8 Agenda - Strength of IBM Vertical Stack - OpenPOWER and Innovation - POWER8 Details 2

3 Need for Innovation Relative % of Improvement 100% Gain by Technology Scaling Gain by Innovation 80% Gate Source Drain Field effect transistor 60% 40% 20% 0% 180 nm 130 nm 90 nm 65 nm 45 nm 32 nm 22 nm

4 Strength of IBM Vertical Stack: What is it? From Semiconductors to Solutions Solutions and Services Middleware / Software Operating System Hypervisor and Firmware Vertical Integration Systems and Packaging Micro-Architecture Semiconductor Technology 4

5 Strength of IBM Vertical Stack 22nm 15-layer copper wire IBM has world class technology with value-added features for server business. Research Futures Dense interconnect - Faster connections - Low latency distance paths - High density complex circuits Carbon Nanotubes Quantum Computing Huge on-chip edram - 6x latency improvement - No off-chip signaling rqmt - 8x bandwidth improvement - 3x less area than SRAM - 5x less energy than SRAM Semiconductor Technology DT DT 22nm edram Cell 5

6 Strength of IBM Vertical Stack POWER8 DFU ISU FXU VSU L2 L2 L2 SMP L2 L2 Acc POWER8 Cache L2 Memory Chip Interconnect Memory IFU LSU L2 L2 L2 SMP PCIe L2 L2 L2 Micro-Architecture Semiconductor Technology CAPI App Centaur Memory Buffer IBM s processor core, memory hierarchy, and SMP micro-architectures lead the industry. 6

7 Strength of IBM Vertical Stack IBM is both chip and system company, enabling significant multi-chip packaging synergies. Glue-less Large SMP topologies High Function System Planars and MCM s Systems and Packaging Micro-Architecture Semiconductor Technology CAPI Flash Robust Scaling - High bandwidth coherence and data interconnect - Adherence to rigid signaling and topology rules - Innovative energy delivery and cooling solutions Research Futures 3D Chip Stacking 7

8 Strength of IBM Vertical Stack IBM owns Software, Silicon, and the Intermediate layers that connect them Opportunity to plumb across stack Leadership Middleware on Leadership Hardware Middleware / Software Operating System Hypervisor and Firmware Systems and Packaging System Plumbing Enablement Micro-Architecture Semiconductor Technology Solution Specific Hardware Acceleration 8

9 Strength of IBM Vertical Stack Solutions and Services Middleware / Software Operating System Hypervisor and Firmware Systems and Packaging Micro-Architecture Semiconductor Technology More than Leadership IT Infrastructure: Also Leadership People who put it to work For Your Business 9

10 Strength of IBM Vertical Stack IBM Research: Innovation Strengthens the Stack Solutions and Services Middleware / Software Operating System Hypervisor and Firmware Systems and Packaging Micro-Architecture Semiconductor Technology IBM is Unique in the World - No other company plays in all the layers. IBM is world-class in all layers - Those that play in multiple layers are world-class only in few. IBM R&D investment - $6 Billion annually - Human capital and culture Researchers U.S. patents in Patent leader past 20 years As CMOS scaling slows, Value comes from Innovating across the Stack 10

11 OpenPOWER and Innovation OpenPOWER: Giving Ecosystem Partners a License to Innovate IBM Stack Research And Innovation What is OpenPOWER? Industry Consortium focused on Innovation - Across Server HW / SW stack - For customized servers and components - Leveraging complementary skills and investments - To provide differentiated architectural alternatives Mellanox TYAN IBM OpenPower Open Innovation Google NVIDIA Benefits for Clients New Innovators on Power Platform = More Value OpenPOWER = Greater choice for IBM Clients More Innovation = Increased Adoption of Power 11

12 The OpenPOWER Foundation: Open & Collaborative Innovation Growing Fast System/Software/Services I/O, Storage, Acceleration Boards/Systems Chip/SOC 12

13 OpenPOWER: Architecture to unleash innovation Compute COMPUTE MEMORY IO NETWORK STORAGE Differentiating DB2 database on Power/Linux using GPU acceleration Cost optimized in memory like nosql infrastructure with CAPI + IBM FlashSystem Distributed store accelerated by RDMA Next-gen big data architecture leveraging GPFS/GSS, Platform, & FPGA based compression acceleration 13

14 POWER8 Processor

15 POWER8 Vision Leadership Performance System Innovation Open System Innovation Increase core throughput at single thread, SMT2, SMT4, and SMT8 level Large step in per socket performance Enable more robust multisocket scaling Higher capacity cache hierarchy and highly threaded processor Enhanced memory bandwidth, capacity, and expansion Dynamic code optimization Hardware-accelerated virtual memory management Coherent Accelerator Processor Interface (CAPI) Agnostic Memory interface Open system software

16 POWER8: The First Processor Designed for Big Data IBM 22nm Technology Silicon-on-Insulator 15 metal layers Deep trench edram POWER8 Processor Compute 12 cores (thread strength optimized) SMT8, 16-wide execution 2X internal data flows Transactional Memory Cache 64KB L KB L2 / core 96MB + up to 128MB L4 / socket 2X bandwidths System Interfaces 230 GB/s memory bandwidth / socket Up to 48x Integrated PCI gen 3 / socket CAPI (over PCI gen 3) Robust, Large SMP Interconnect On chip Energy Mgmt, VRM / core

17 POWER8 Execution Improvement vs. POWER7 SMT4 SMT8 8 dispatch 10 issue 16 execution pipes: 2 FXU, 2 LSU, 2 LU, 4 FPU, 2 VMX, 1 Crypto, 1 DFU, 1 CR, 1 BR Larger Issue queues (4 x 16-entry) Larger global completion, Load/Store reorder Improved branch prediction Improved unaligned storage access IFU ISU FXU LSU DFU VSU Larger Caching Structures vs. POWER7 2x L1 data cache (64 KB) 2x outstanding data cache misses 4x translation Cache Wider Load/Store 32B 64B L2 to L1 data bus 2x data cache to execution dataflow Enhanced Prefetch Instruction speculation awareness Data prefetch depth awareness Adaptive bandwidth awareness Topology awareness Performance vs. POWER7 ~1.6x Thread ~2x Max SMT

18 POWER8 On-chip Caches L2: 512 KB 8 way per core : 96 MB (12 x 8 MB 8 way ) NUCA Cache policy (Non-Uniform Cache Architecture) Scalable bandwidth and latency Migrate hot lines to local L2, then local (replicate L2 contained footprint) Chip Interconnect: 150 GB/sec x 12 segments per direction = 3.6 TB/sec L2 L2 L2 SMP L2 L2 Acc L2 Memory Chip Interconnect Memory L2 L2 L2 SMP PCIe L2 L2 L2

19 Cache Bandwidth L GB/sec shown assuming 4 GHz Product frequency will vary based on model type Across 12 core chip 4 TB/sec L2 BW 3 TB/sec BW

20 Memory Organization DRAM Chips Centaur Memory Buffers Centaur Memory Buffers DRAM Chips POWER8 Processor Up to 8 high speed channels, each running up to 9.6 Gb/s for up to 230 GB/s sustained Up to 32 total DDR ports yielding 410 GB/s peak at the DRAM Up to 1 TB memory capacity per fully configured processor socket

21 Memory Buffer Chip with 16MB of Cache DRAM Chips Memory Buffer DDR Interfaces Intelligence Moved into Memory Scheduling logic, caching structures Energy Mgmt, RAS decision point Formerly on Processor Moved to Memory Buffer Processor Interface 9.6 GB/s high speed interface More robust RAS On-the-fly lane isolation/repair Extensible for innovation build-out Performance Value End-to-end fastpath and data retry (latency) Cache latency/bandwidth, partial updates Cache write scheduling, prefetch, energy 22nm SOI for optimal performance / energy 15 metal levels (latency, bandwidth) Scheduler & Management 16MB Memory Cache POWER8 Link

22 Centaur Memory DIMM POWER8 Processor Memory DIMM Form factors

23 POWER7 Native PCIe Gen 3 Support Direct processor integration Replaces proprietary GX/Bridge Low latency Gen3 x16 bandwidth (16 Gb/s) POWER8 I/O Bridge GX Bus PCIe G2 Transport Layer for CAPI Protocol Coherently Attach Devices connect to processor via PCIe Protocol encapsulated in PCIe Processor Service Layer (PSL) Present robust, durable interfaces to applications Offload complexity / content from CAPP PCIe G3 PCI Devices CAPI = Coherent Accelerator Processor Interface FPGA or ASIC Customizable Hardware Application Accelerator Specific system SW, middleware, or user application Written to durable interface provided by PSL PCI Device

24 Coherent Accelerator Processor Interface (CAPI) Overview CAPI FPGA IBM Supplied POWER Service Layer CAPP PCIe Function 0 Function 1 Function 2 Function n POWER8 Processor Typical I/O Model Flow DD Call Copy or Pin Source Data MMIO Notify Accelerator Acceleration Poll / Int Completion Copy or Unpin Result Data Ret. From DD Completion Flow with a Coherent Model Shared Mem. Notify Accelerator Acceleration Shared Memory Completion Advantages of Coherent Attachment Over I/O Attachment Virtual Addressing & Data Caching (significant latency reduction) Easier, Natural Programming Model (avoid application restructuring) Enables Apps Not Possible on I/O (Pointer chasing, shared mem semaphores, )

25 CAPI Attached Flash Optimization Application Read/Write Syscall strategy() strategy() Pin buffers, Translate, Map DMA, Start I/O File System LVM iodone() iodone() Disk & Adapter DD Interrupt, unmap, unpin,iodone scheduling 20K Instructions < 500 Instructions Posix Async I/O Style API Application User Library Shared Memory Work Queue aio_read() aio_write() Attach TMS Flash to POWER8 via CAPI coherent Attach Issues Read/Write Commands from applications to eliminate 97% of instruction path length CAPI Flash controller Operates in User Space Saves 10 s per 1M IOPs

26 Differentiation of NoSQL on POWER8 w/capi: 5X cost reduction Power CAPI-attached Flash model for NoSQL offers dramatic (24:1) density advantage Today s NoSQL in memory (x86) WWW 10Gb Uplink Load Balancer Differentiated NoSQL (POWER8 + CAPI Flash) WWW 500GB Cache 500GB Node Cache 500GB Node Cache 500GB Node Cache 500GB Node Cache 500GB Node Cache Node Backup Node 10Gb Uplink POWER8 Server Flash Array w/ up to 40TB Infrastructure Requirements Large Distributed (Scale out) Large Memory per node Networking Bandwidth Needs Load Balancing Infrastructure Attributes 192 threads in 4U Server drawer 40 TB of memory based Flash per 4U Drawer Shared Memory & Cache for dynamic tuning Elimination of I/O and Network Overhead Cluster solution in a box