OpenPOWER Innovations for HPC. IBM Research. IWOPH workshop, ISC, Germany June 21, Christoph Hagleitner,

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1 IWOPH workshop, ISC, Germany June 21, 2017 OpenPOWER Innovations for HPC IBM Research Christoph Hagleitner, IBM Research - Zurich Lab

2 IBM Research - Zurich Established in different nationalities Open Collaboration 43 funded projects and 500+ partners in Horizon 2020 Binnig and Rohrer Nanotechnology Centre opened in 2011 (Public Private Partnership with ETH Zürich and EMPA) 7 European Research Council Grants Two Nobel Prizes: 1986 for the scanning tunneling microscope (Binnig and Rohrer) 1987 for the discovery of hightemperature superconductivity (Müller and Bednorz) 2

3 Agenda Cognitive Computing & HPC HPC Software ecosystem HPC system roadmap HPC Processor HPC Accelerators 3

4 Cognitive Computing Applications Computational Complexity O(N 3 ) Graph Analytics Deep Learning HADOOP HPC Classic HPC Applications Dim. Reduction O(N 2 ) Uncertainty Quantification Knowledge Graph Creation Information Retrieval O(N) Database queries MB GB TB PB Data Volume 4

5 Cognitive Computing: Integration & Disaggregation hadoop-style workloads... scale-out via network main metrics cost (capital, energy) compute density scalability homogeneous nodes (CPU / FPGA / NVMe plus compute) datacenter disaggregation complex HPC-like workloads... scale-up via high-speed buses main metrics memory / accelerator / inter-node BW optimal mix of heterogeneous resources (CPU / GPU / FPGA / HBM / DRAM / NVMe) compute density, scalability heterogeneous nodes data centric design 5

6 Dense, Energy Efficient Computing: Hyperscale FPGA Cloud economics density (>1000 nodes / rack) integrated NICs switch card (backplane, no cables) medium to low-cost compute chips Passive liquid cooling ultimate density (cooling >70W / node) energy re-use Built to integrate heterogeneous resources CPUs Accelerators 6

7 Cognitive Computing: Integration & Disaggregation hadoop-style workloads... scale-out via network main metrics cost (capital, energy) compute density scalability homogeneous nodes (CPU / FPGA / NVMe plus compute) datacenter disaggregation complex HPC-like workloads... scale-up via high-speed buses main metrics memory / accelerator / inter-node BW optimal mix of heterogeneous resources (CPU / GPU / FPGA / HBM / DRAM / NVMe) compute density, scalability heterogeneous nodes data centric design 7

8 OpenPOWER, a catalyst for Open Innovation Open Development OpenPOWER enables greater innovation through both open software and open hardware Collaboration across multiple thought leaders Collaborative development model drives collective thought leadership, simultaneously across multiple disciplines Performance of leading POWER architecture Broadens the capability and performance of the POWER platform The OpenPOWER Foundation creates an open ecosystem, using the POWER Architecture to share expertise, investment, and server-class intellectual property to serve the evolving needs of customers. IBM Research - Zurich Lab

9 OpenPOWER Foundation: 230+ Partners, 24 countries

10 SuperVessel: OpenPOWER Cloud Open cloud platform based on Power/OpenPOWER and OpenStack technology for business partners, developers, and university students Heterogeneous Computing Zurich Research Lab IBM Research - Zurich Lab

11 SuperVessel: OpenPOWER Cloud for Developers 11

12 OpenPOWER Software Support 50+ IBM Innovation Centers, over 2,300 Linux ISVs developing on Power Moving to little endian (almost complete) IBM Research - Zurich Lab

13 OpenPOWER OS & Compiler Support Choose your favorite and latest Linux flavor RHEL Ubuntu in little endian (ppc64le) Standard compilers : GCC 4.8.5, MPICH 3.0.4, CUDA 8.0 AT9.0.3 compilers: GCC 5.3.1, Python 3.4, and more optimized for POWER AT compilers: GCC 6.2.1, Python 3.5, and more optimized for POWER IBM compilers: XLF, XLC,... Optimized libraries: MASS (math functions) ESSL (BLAS) and MPI 13

14 Introducing PowerAI: Enterprise Deep Learning Distribution Package of Pre-Compiled Major Deep Learning Frameworks Easy to install & get started with Deep Learning with Enterprise-Class Support Optimized for Performance To Take Advantage of NVLink Enabled by High Performance Computing Infrastructure IBM Research - Zurich Lab 14

15 PowerAI Deep Learning Software Distribution Deep Learning Frameworks Caffe NVCaffe IBMCaffe Torch TensorFlow Distributed TensorFlow Theano Chainer Supporting Libraries OpenBLAS Bazel Distributed Communications NCCL DIGITS Accelerated Servers and Infrastructure for Scaling Cluster of NVLink Servers Spectrum Scale: High-Speed Parallel File System Scale to Cloud IBM Research - Zurich Lab

16 S822LC: IBM POWER8+ for HPC 16

17 OpenPOWER Core Technology Roadmap Mellanox Interconnect Connect-IB FDR Infiniband PCIe Gen3 ConnectX-4 EDR Infiniband CAPI over PCIe Gen3 ConnectX-5 Next-Gen Infiniband Enhanced CAPI over PCIe Gen4 NVIDIA GPUs Kepler PCIe Gen3 Pascal NVLink Volta Enhanced NVLink IBM CPUs POWER8 PCIe Gen3 & CAPI Interface POWER8 NVLink & CAPI POWER9 Enhanced NVLink, OpenCAPI & PCIe Gen4 Accelerator Links PCIe Gen3 1x GPU FPGA NVLINK 5x GPU FPGA 25G Accelerator Link 7-10x 4x PCIe Gen4 GPU FPGA IBM Research - Zurich Lab

18 Looking Ahead: POWER9 Chip New Core Microarchitecture Stronger thread performance Efficient agile pipeline POWER ISA v3.0 Enhanced Cache Hierarchy 120MB NUCA L3 architecture 12 x 20-way associative regions Advanced replacement policies Fed by 7 TB/s on-chip bandwidth Cloud + Virtualization Innovation Quality of service assists New interrupt architecture Workload optimized frequency Hardware enforced trusted execution 14nm finfet Improved device performance and reduced energy 17 layer metal stack and edram 8.0 billion transistors IBM Research - Zurich Lab Leadership Hardware Acceleration Platform Enhanced on-chip acceleration Nvidia NVLink 2.0: High bandwidth, advanced features CAPI 2.0: Coherent accelerator and storage attach (PCIe G4) OpenCAPI: Improved latency and bandwidth, open interface State of the Art I/O Subsystem PCIe Gen4 48 lanes High Bandwidth Signaling Technology 16 Gb/s interface: Local SMP 25 Gb/s interface: 25G Link for Accelerator and remote SMP

19 POWER9 marchitecture Re-factored Core Provides Improved Efficiency & Workload Alignment Enhanced pipeline efficiency with modular execution and intelligent pipeline control Increased pipeline utilization with symmetric data-type engines: Fixed, Float, 128b, SIMD Shared compute resource optimizes data-type interchange 19

20 POWER9: POWER ISA v3.0 Broader data type support 128-bit IEEE 754 Quad-Precision Float Full width quad-precision for financial and security applications Expanded BCD and 128b Decimal Integer For database and native analytics Half-Precision Float Conversion Optimized for accelerator bandwidth and data exchange Support Emerging Algorithms Enhanced Arithmetic and SIMD Random Number Generation Instruction Accelerate Emerging Workloads Memory Atomics For high scale data-centric applications Hardware Assisted Garbage Collection Optimize response time of interpretive languages Cloud Optimization Enhanced Translation Architecture Optimized for Linux New Interrupt Architecture Automated partition routing for extreme virtualization Enhanced Accelerator Virtualization Hardware Enforced Trusted Execution Energy & Frequency Management POWER9 Workload Optimized Frequency Manage energy between threads and cores with reduced wakeup latency 20

21 POWER8 Caches L2: 1 MB 8 way per core L3: 96 MB (12 x 8 MB 8 way Bank) L4: 128 MB (on Centaur) NUCA Cache policy (Non-Uniform Cache Architecture) Cache bandwidth 4 TB/sec L2 BW 3 TB/sec L3 BW 21

22 Lookin ahead: POWER9 Data Capacity & Throughput L3 Cache: 120 MB Shared Capacity NUCA Cache 10 MB Capacity + 512k L2 per 2x SMT4 Core Enhanced Replacement with Reuse & Data- Type Awareness High-Throughput On-Chip Fabric Over 7 TB/s On-chip Switch Move Data in/out at 256 GB/s per 2x SMT4 Core 22

23 Looking Ahead: POWER9 Accelerator Interfaces Extreme Accelerator Bandwidth and Reduced Latency PCIe Gen 4 x 48 lanes 192 GB/s peak bandwidth (duplex) IBM BlueLink 25Gb/s x 48 lanes 300 GB/s peak bandwidth (duplex) Coherent Memory and Virtual Addressing Capability for all Accelerators CAPI 2.0-4x bandwidth of POWER8 using PCIe Gen 4 NVLink 2.0 Next generation of GPU/CPU bandwidth and integration using BlueLink OpenCAPI High bandwidth, low latency and open interface using BlueLink opencapi opencapi 23

24 POWER9 + Accelerators: GPUs See GTC

25 POWER9 + GPU: Unified Memory Pascal Volta See GTC

26 CAPI... Coherent Accelerator Processor Interface Standard I/O Model Flow DD Call Copy/Pin MMIO Notify Accelerate Poll / Int Copy/Unpin Return DD Shared Mem. Notify Accelerator Flow with a Coherent Model Accelerate Shared Memory Completion CAPI FPGA CAPP PCIe POWER8 Processor POWER Service Layer AFU n AFU 2 AFU 1 AFU 0 26

27 IBM Research - Zurich Lab 6/22/

28 CAPI SNAP OpenCAPI v3.0 and NVLINK 2.0 with POWER9 POWER9 CPU 2 CAPI v2 Proxy Cores P9 Core Memory Bus P9 Core CAPP CAPP OpenCAPI and NVLink processing unit PHB NPU 25G PCIe Gen4 PCIe Accelerator Card FPGA PSL SNAP Action0 Action1 Memory - Streaming Layer for CAPI v Simplifies accelerator development and use - Supports High-Level-Synthesis (HLS) for FPGA development - Available as open source OpenCAPI Accelerator OpenCAPI OpenCAPI Accelerator Card OpenCAPI Accelerator Storage Accelerator Card Class Memory Card Card IBM Research - Zurich Lab NVIDIA NVIDIA Pascal NVIDIA Pascal GPU Pascal GPU GPU Device or Network PCIe Gen 4 x 48 lanes 192 GB/s duplex bandwidth 25G Link x 48 lanes 300 GB/s duplex bandwidth

29 Available Accelerator Cards Nallatech team explaining CAPI Flash card: 6/22/2017 IBM Research - Zurich Lab 29

30 Dense Memory (distributed) Prototype Dense Memory integration software stack available byte addressable, distributed globally accessable DM resource exports industry standard asynchronous RDMA API for DM read and write access Implements efficient local and remote DM access zero copy local access via direct DMA device - application buffer zero copy remote access via IB RDMA remote host - application buffer Performance measurements local DM access at NVMe devices performance limits (3.5 GB/s read, 1.8 GB/s write of 4k buffers) remote DM access at network (100Gb/s InfiniBand) and device limits: 12.5 GB/s distributed DM random read with 4 storage nodes, all equipped with one NVMe SSD each close to 900k IOPs for single device short sequential red/write operations 30

31 But be willing take incremental steps when you can! IBM Research - Zurich Lab 31