Design Space Exploration for Memory Subsystems of VLIW Architectures

Transcription

1 E University of Paderborn Dr.-Ing. Mario Porrmann Design Space Exploration for Memory Subsystems of VLIW Architectures Thorsten Jungeblut 1, Gregor Sievers, Mario Porrmann 1, Ulrich Rückert 2 1 System and Circuit Technology, University of Paderborn 2 Cognitive Interaction Technology Center of Excellence, Bielefeld University

2 Motivation(1) - Increasing complexity of mobile applications - More functionality - New algorithms (LTE; LTE Advanced) - Multimedia applications (Video, 3-D, ) - Nonflexible hardware Flexible software implementation (Software-Defined Radio - SDR) Powerful CPU necessary - High requirements to ressource efficiency! 2

3 Motivation(2) In embedded processors size of on-chip memories is limited External (SDRAM) memory Low costs per bit Slow/high latency Intermediate storage of accesses in the cache Loading of entire cache lines from the external memory Use of temporal and spatial locality Size of the caches is limited by the operating frequency of the processor core Cache hierachie Level-1 cache is matched to the core frequency additional levels with higher latency Register Level-1 cache Level-2 cache Main memory Hard disk 3

4 Outline Concurrent design flow for DSE VLIW architecture/cache architecture Prototyping Environment Performance results and resource requirements Conclusion/Outlook Specification FE Instruction Fetch / L1 Instruction Cache Instruction Memory DC Vice-UPSLA Instruction Decode Benchmarks Source Code Bypass RTL-Description RD UPSLA Register Read Compiler RTL-Code Assembler Code Register RTL-Simulator ALU Condition RTL-Code EX Register * / Synthesis-Tool LD/ST Netlist ME Emulator (Prototyp) Assembler ALU ALU ALU Object-Files * / * / * / Linker LD/ST LD/ST LD/ST Executables ASIC-Realization L1 Data-Cache Software Simulator Data Memory Profiling-Data Functional WR Verification Register Write Visualization Ressource Efficiency 4

5 Design Space Exploration Tool Flow Specification Goal: Highly automated design flow Vice-UPSLA Benchmarks Source Code RTL-Description UPSLA Compiler RTL-Code Assembler Code RTL-Simulator Assembler RTL-Code Object-Files Synthesis-Tool Linker Netlist Executables Emulator (Prototyp) ASIC-Realization Software Simulator Functional Verification Visualization Profiling-Data Ressource Efficiency 5

6 The CoreVA architecture Modular Design FE Instruction Fetch / L1 Instruction Cache Instruction Memory DC Instruction Decode Bypass RD Register Read Condition Register EX * ALU / ALU ALU ALU * / * / * / Register ME LD/ST LD/ST LD/ST LD/ST L1 Data-Cache Data Memory WR Register Write 6

7 Dynamically Reconfigurable Platform RAPTOR-X64 Prototypic Implementation of Microelectronic Circuits on FPGAs Up to 200 Million transistors emulated Flexible, modular concept: PCI-Busmotherboard with up to six modules Partial dynamic reconfiguration at high reconfiguration bandwidth USB Controller USB 2.0-High-Speed USB-OTG System Monitor Voltage, Tempature, Analog Inputs Clock Sythesis, Distribution TST-JTAG CFG-JTAG USB Logic Local-Bus Master Local-Bus Slave OTG-Control CTRL+Config Logic Arbiter, MMU Diagnostics, CLK, Configuration, etc. Xilinx SystemACE CF CF Access, JTAG Control PCI-X-Bus (64Bit Data / 32Bit Address) PCI-Bus- Bridge Master, Slave, DMA Dual-Port SRAM Module 6 CTRL, SMB 128 SelectMAP, CFG-JTAG Local-Bus (32Bit Data / 32Bit Address) 85 Module 1 75 CTRL, SMB 128 SelectMAP, CFG-JTAG 85 Module 2 75 CTRL, SMB 128 SelectMAP, CFG-JTAG 85 Module Module 4 Broadcast-Bus 7

8 System Environment Multi master system bus Generic I/D cache interfaces to external memory 4 GB SDRAM Penalty cycles on cache misses: Instr. cache: >73 clock cycles Data cache: >61 clock cycles Internal memories can be accessed from host system Generic interface for dedicated hardware extensions 9.1 Gbit/s external bandwidth SDRAM SDRAM Controller Systembus Controller Localbus Interface Arbiter Instr. Cache Data Cache Systembus MMIO CoreVA CPU Host PC FIFO CRC UART Xilinx FPGA ASIC RAPTOR2000 System 8

9 Cache Architecture Overview I-Cache: 32 bit per issue slot 4 slot configuration: 128 bit interface Direct mapped (low latency/power/area) 16kB cache size, 64 bytes line width (configurable) D-Cache: 1-/2-port configuration possible Direct mapped 16kB cache size, 32 bytes line width (configurable) Write-back policy, non-blocking Two programmable allocation modes: fetch-on-write-miss/allocate-on-write-miss I-/D-Caches can dynamically be configured as scratch pad memories Higher performance for timing critical parts of an application (cache misses are avoided) Energy improvements due to nonexistent external memory accesses 9

10 Cache Architecture Synthesis Results 10

11 Application Evaluation Different Cache Configurations Applications: synthetic benchmarks, baseband, cryptography, multimedia, LTE protocol stack 50% LD/ST-units per #FUs best trade-off Concurrent LD/ST Speedup! Speedup dependent on scheduling! 11

12 Results(1) Hit Rates High hit rates for all applications Allocate-on-write-miss Fetch-on-write-miss 12

13 Results(2) Portion of Stall Cycles to Execution Time Latencies of SDRAM accesses may vary dependent on the order, distribution and frequency of the accesses. 13

14 Results(3) Performance 14

15 Results(4) Energy 15

16 Results(5) Energy-Delay 16

17 Register File 1.66 mm The CoreVA VLIW architecture ASIC realization 4-issue VLIW processor, 2x MLA,DIV 1-Port I-Cache (16kByte,128 Bit), 2-Port D-Cache (16kByte, 32 Bit) 65nm ST Microelectronics, Low Power (Thick Oxide), 1.2V MixedVT, 1.8V I/Os (configurable pullups) Hardware extensions (incl. ECC) 1.66 mm Instruction Cache Comp. Cell Execute Frequency Area (32kB SRAM) Power Consumption 400 MHz 2.7 mm² 0.1 W 1.6 GOP/s in scalar mode 3.2 GOP/s in SIMD mode Data Cache ECC 17

18 Conclusion/Outlook Framework for the design-space exploration of processor architectures and memory subsystems Rapid prototyping environment RAPTOR Dynamic configurable cache architecture 2-slot configuration/allocate-on-write-miss shows best energy trade-off Performance/Energy gains up to 25% Future work: Include associativity Combination of caches/scratch-pad memories to enhance memory bandwidth 18

19 Questions? Specification Vice-UPSLA Benchmarks Source Code RTL-Description UPSLA Compiler RTL-Code Assembler Code RTL-Simulator Assembler RTL-Code Object-Files Synthesis-Tool Linker Netlist Executables Emulator (Prototyp) ASIC-Realization Software Simulator Functional Verification Visualization Profiling-Data Ressource Efficiency Design space exploration VLIW architecture SDRAM SDRAM Controller Systembus Controller Arbiter Instr. Cache Data Cache Systembus CoreVA CPU Localbus Interface MMIO Host PC FIFO CRC UART Xilinx FPGA ASIC Rapid prototyping RAPTOR2000 System System Architecture 19

20 E University of Paderborn Dr.-Ing. Mario Porrmann Thank you for your attention! Heinz Nixdorf Institute University of Paderborn System and Circuit Technology Dipl.-Ing. Thorsten Jungeblut Fürstenallee Paderborn Tel.: / Fax.: / tj@hni.upb.de