Configuring the Default Setting of the CDC7005 Using a MSP430 Microcontroller

Transcription

1 Application Report SCAA071 - AUGUST 2004 Configuring the Default Setting of the CDC7005 Using a MSP430 Microcontroller Daniel T. Pherson TI Clock Solutions ABSTRACT This application report demonstrates how the power-up default setting of the CDC7005 can be configured using a Texas Instruments MSP430 Ultralow Power Microcontroller. Included in this document is a description of how to create the hardware interface between the two devices as well as example code that can be easily modified to fit any application. The target audience of this report is project managers and application engineers with a basic understanding of electrical circuit design, computer programming, and embedded controllers. The technology demonstrated in this report is typically used in radio frequency (RF) applications such as wireless base stations. 1

2 Contents 1 Introduction Background Information The CDC7005 High Performance Clock Synthesizer The MSP430F1011A Ultralow Power Microcontroller The SN74LVC257A Quad 2-Input Multiplexer Theory of Operation The CDC7005 SPI Control Interface Using the MSP430F1101 Microcontroller to Generate the SPI Interfacing the MSP430, an External Device, and the CDC7005 Using a MUX Implementing the Solution Materials Needed to Program the MSP430F Programming Hardware Programming Software Modifying the Example Program to Fit Your application Initializing The MSP430 Device Defing the Default Setting of the CDC Verify that the 2 LSBs of Each Word Are Correct Write the Data to the CDC Terminating the MSP430 Communication with the CDC Explaination of Additional Code Segments The Hardware Interface Between The MSP430 and the CDC Schematic Materials List References Appendix A. Full Version of Sample Code Appendix B. CDC7005 Internal Registers Figures Figure 1. CDC7005 SPI Communication Block Diagram... 4 Figure 2. Timing Diagram SPI Control Interface... 5 Figure 3. MSP430 Program Flowchart... 7 Figure 4. Functional Block Diagram... 8 Tables Table B-1. Word Table B-2. Word Table B-3. Word Configuring the Default Setting of the CDC7005 Using a MSP430 Microcontroller

3 1 Introduction The CDC7005 is a high-performance clock synthesizer and jitter cleaner typically used in RF applications. It is a highly configurable device that can be programmed using a three-line serial port interface (SPI). Typically, a peripheral device is connected to the CDC7005 via the serial port interface to configure the run-time setting or the power-up default setting. The purpose of this application report is to demonstrate how the power-up default setting of the CDC7005 clock synthesizer can be manipulated using the Texas Instruments MSP430 Ultralow Power Microcontroller. This report is divided into three major sections. This first section provides information designed to familiarize the reader with all of the devices used in this application. The second section describes the theory behind the operation and design of this solution. Finally, this application report gives a complete guide to implementing the solution. This section includes all of the materials, code, and schematics necessary to control the power-up default setting of the CDC7005 using the MSP430 microcontroller. The audience of this report is expected to have a basic understanding of the CDC7005 device and embedded microcontrollers. This application report contains all of the information needed to create a complete solution. 2 Background Information The following section gives a brief introduction to the CDC7005 clock synthesizer, the MSP430F1101 microcontroller, and the SN74LVC257A multiplexer. The purpose of this section is to familiarize readers with the basic operation and functionality of these three devices. 2.1 The CDC7005 High Performance Clock Synthesizer The CDC7005 is a high performance clock synthesizer and jitter cleaner. Its design is optimized for RF applications such as wireless base stations. This device synchronizes two clock inputs: a very clean voltage controlled crystal oscillator (VCXO) differential clock input and a reference input clock signal. Input clocks can synchronized at frequencies up to 800MHz. An internal PLL circuit eliminates clock jitter and has a programmable delay for output phase adjustments. The CDC7005 also has five synchronized LVPECL outputs whose frequency can be divided by 1, 2, 4, 8, and 16. Four 32-bit write-only data registers contain device s operation configuration. This data controls the internal reference dividers, output dividers, reference delay, and charge pump current. The contents of these registers can be changed using the integrated serial port interface. This serial port interface is typically connected to an ASIC, a microcontroller or a PC Configuring the Default Setting of the CDC7005 Using a MSP430 Microcontroller 3

4 2.2 The MSP430F11011A Ultralow Power Microcontroller The MSP430D1101A is a low-power, mixed signal microcontroller. This device incorporates 14 fully configurable I/O pins with a built in 16-bit timer and an analog comparator. Five selectable low-power modes are capable of reducing the current consumption of the microcontroller to 0.1µA. The MSP430F1101A microcontroller has a supply voltage range of 1.8 V to 3.6 V. In addition to minimal power consumption, the low power modes disable the CPU and all internal and external clocks. This eliminates the risk of the MSP430 introducing coupling into noisesensitive circuitry. An interrupt will wake up the microcontroller from a low power mode allowing it to resume normal operation. The MSP430F1011A has 1KB +128B of programmable flash memory. More flash memory is available in other, more costly devices, however is not needed for this application. It also has 128B of ram and bit CPU registers. MSP430 microcontrollers can be programmed using a C or assembler compiler and are connected to a computer using a JTAG interface. This interface requires no external programming voltage and allows real-time debugging. 2.3 The SN74LVC257A Quad 2-Input Multiplexer The Texas Instruments SN74LVC257A is a quad 2-input multiplexer with high-impedance outputs. The multiplexer switch is controlled by an external input signal and determines which set of input data will be used. Although not a critical factor in most applications, the SN74LVC257A multiplexer has a maximum input-output phase delay of 4.3 ns. This multiplexer uses a 3.3-V power supply. 3 Theory of Operation In this application, the MSP430 microcontroller is connected to the CDC7005 for the purpose of loading a new power-up default setting into the CDC s internal registers. All other run-time changes to the operating mode of the CDC7005 are made using either an application specific integrated circuit (ASIC) or PC-based serial communication. To ensure predictable and consistent operation of the CDC7005, measures must be taken to ensure that the appropriate data is loaded into the SPI at the right time. This section discusses the parameters of the CDC7005 SPI control interface, generating the SPI data using the MSP430F1101A microcontroller, and using a multiplexer to distinguish which signal will be loaded into the CDC Configuring the Default Setting of the CDC7005 Using a MSP430 Microcontroller

5 Figure 1. CDC7005 SPI Communication Block Diagram 3.1 The CDC7005 SPI Control Interface The operating mode of the CDC7005 is modified using a serial port interface (SPI). This SPI writes directly to the four, 32-bit, write-only control registers; Word 0, Word 1, Word 2, and Word 3. The purpose of each bit within the four words is listed in the CDC7005 data sheet. Word 0, Word 1, and Word 2 are critical to the operating mode of this device. Word 3 is only used for factory testing purposes. The CDC7005 SPI consists of three control signals: CTRL_CLK, CTRL_DATA, and CTRL_LE. These control signals are connected to pins A1, A2, and A3, respectively. The SPI communication is initiated by a falling edge at the CTRL_LE input. For the duration of time that CTRL_LE is low, the current state of the CTRL_DATA input is read into the CDC7005 s internal shift register with every rising edge of the CTRL_CLK input. This data is written from the most significant bit (MSB) to the least significant bit (LSB). This process continues until a rising edge is detected at the CTRL_LE input. At this point, the CDC7005 moves the data from the shift register in to the appropriate word based upon the contents of the two address bits (the two LSBs). It is extremely critical that only 32 bits of data are loaded into the shift register prior to the rising edge of the CTRL_LE signal. If a different amount of bits are loaded into the device, the resulting operating condition will be unpredictable. Configuring the Default Setting of the CDC7005 Using a MSP430 Microcontroller 5

6 Figure 2. Timing Diagram SPI Control Interface When designing systems to communicate with the CDC7005 through an SPI, it is important to keep the timing specifications of the device in mind. The CDC7005 SPI can handle a relatively fast asynchronous data transfer. The maximum clock speed for this data transfer is 20 MHz. All of the timing specifications of the SPI are listed on the on the timing diagram shown in Figure 2. Figure 2 also provides a graphical description of how the data transmission is read by the device. 3.2 Using the MSP430F1101 Microcontroller to Generate the SPI The purpose of the MSP430F1101A microcontroller in this application is to change the default setting of the CDC7005 at power up. After this event has occurred, the MSP430 must enter a low power standby mode so that it does not generate any noise that may affect the operation of the CDC7005. A graphical representation of this serial data generation algorithm is shown in Figure 3. The communication protocol used by the CDC7005 SPI is relatively simple and is easy to generate using the MSP430. The hexadecimal values that are to be used for the default setting are stored in the flash memory. At power-up the settings are then copied from the flash memory into the CPU s internal registers. Immediately after this copy, the serial port communication begins. The two least significant bits of each word transferred into the CDC7005 shift register determine if the data is loaded into Word 0, Word 1, or Word 2. In the control program, it is important to include additional code that ensures that the content of the two least significant bits is always correct. Otherwise, the data will be written to the incorrect word and the CDC7005 will not function predictably. This is accomplished in the control program by clearing and rewriting the two LSBs of each word before the serial port communication takes place. 6 Configuring the Default Setting of the CDC7005 Using a MSP430 Microcontroller

7 The CDC7005 serial port interface requires the data to be written in to its internal registers with the most significant bit (MSB) first and the least significant bit (LSB) last. This is done by creating a software shift register that rotates the bits inside of each register to the left. After each rotation, the MSB is moved into the carry bit. The status of the carry bit determines whether a logical 1 or 0 will be written into the CDC7005 s internal registers. The data is then written into the CDC7005 every time a rising edge at the CTRL_CLK input occurs. After the first bit has been generated, the program immediately sets the CTRL_LE bit to zero. This enables the writing sequence to occur. When the CTRL_LE bit is high, the CDC7005 does not respond to any of the I/O activity that occurs on its SPI pins. The CTRL_LE bit is held low until the entire 32-bit word has been written. It is in this way that each word must be written separately to the CDC7005. To write the next word, the CTRL_LE bit must be in the high state for at least one clock cycle. As soon as it is reset again, the next word can be written. Configuring the Default Setting of the CDC7005 Using a MSP430 Microcontroller 7

8 Figure 3. MSP430 Program Flowchart 8 Configuring the Default Setting of the CDC7005 Using a MSP430 Microcontroller

9 3.3 Interfacing the MSP430, an External Device, and the CDC7005 Using a MUX In this application, the CDC7005 can be programmed by two devices: the MSP430F1101A microcontroller and a peripheral device such as a PC or an ASIC. The role of the MSP430 microcontroller is to configure the default setting of the CDC7005 on power-up. All other modifications that need to be made to the operation of the CDC device must be done with a peripheral device capable of serial communication. The only way to ensure that the information coming from these two sources is loaded into the CDC7005 device is to use a multiplexer. A multiplexer would only allow one device to communicate with the CDC7005 SPI at a time. On power-up, the only device that would have access to the CDC7005 SPI is the MSP430F1101A. After the MSP430 device has finished programming the default setting, it configures the multiplexer to only accept data streaming from the peripheral device. Figure 4. Functional Block Diagram Configuring the Default Setting of the CDC7005 Using a MSP430 Microcontroller 9

10 4 Implementing the Solution This section of the report contains all of the information needed to control the default setting of the CDC7005 using the MSP430. First, this section will discuss all of the materials (i.e. software, hardware) needed to implement the MSP430 and where they can be located. The second section gives instructions on how to modify the provided sample program to fit any application. Finally, a complete description of the hardware interface required to implement this solution is given. 4.1 Materials Needed to Program the MSP430F Programming Hardware The MSP430F1101A microcontroller can easily be programmed using the Texas Instruments MSP430F11x1 Flash Emulation Tool (FET). This device comes with a starter package including everything that is needed to program and test an MSP430F1101A microcontroller. Included in this package is: One MSP430F11x(1) FET development board One FET to PC adapter The IAR Embedded Workbench Kickstart software package which includes, an assembler compiler, a similar, and a source-level debugger All associated documentation, user manuals, and data sheets on a CD-ROM Two MSP430F1121 microcontrollers The MSP430F11x1 Flash Emulation Tool is the best device to use while programming MSP430 microcontrollers. Its low price and ease of use make it the ideal interface between the MSP430 microcontroller and a PC. This kit can be purchased directly from Texas Instruments Inc. at the following website: Programming Software The software required to program the MSP430F1101A microcontroller is the IAR Embedded Workbench Kickstart Version 2 (Rev. C). This program is an assembler compiler with a sourcelevel and a simulator. It also serves as a real-time debugging environment. The Kickstart version of the IAR Embedded Workbench embodies all of the features of the full version, however is limited because it can only compile assembler code. Despite this limitation, it is a powerful tool and can be used in nearly every MSP430 application. The Kickstart version of IAR Embedded Workbench is available for no cost on the following website: 10 Configuring the Default Setting of the CDC7005 Using a MSP430 Microcontroller

11 4.2 Modifying the Example Program to Fit Your application Accompanying this text is example code that programs the MSP430 microcontroller to change the power-up default setting of a CDC7005. The flow of this program follows the algorithm outlined in section 3.2. The sample code has been written in a way that requires very little modification. This section of the application report will discuss the function of each section of the code and what modifications can be made. A continuous version of the code that can easily be copied into an assembler compiler is found in Appendix A Initializing The MSP430 Device The purpose of this block of code is to set the initial operating parameters of the MSP430F1101 microcontroller. Much like the C programming language, assembler uses header files to make the code easier to manipulate. This program uses the header file MSP430x11x1.h which is designed to work with the MSP430 F1101A, F1111A, and F1121A devices. The starting addresses of the RAM and the flash memory are defined shortly after the header. Next, an external high frequency (1-8 MHz) crystal-oscillator is configured. Port pins P2.0, P2.1, P2.2, and P2.3 of this device are then configured as outputs. The port pins are set to their initial state (either on or off) to ensure that the program operates as planned. Finally, this segment of code clears all of the CPU registers that will be used in this program. This step is not necessary; however, it ensures the contents of each register will always be predictable. Normally, this segment of code does not need to be modified in any applications. #include "msp430x11x1.h" ORG 0F000h ; Program Start RESET mov.w #0300h,SP ; Initialize 'x1121 stackpointer StopWDT mov.w #WDTPW+WDTHOLD,&WDTCTL ; Stop Watchdog Timer SetUpClk bis.b #XTS,&BCSCTL1 ; LFXT1 = HF XTAL bis.b #OFIE,&IE1 ; Enable osc fault interrupt SetupP2 bis.b #00Fh,&P2DIR ; Pin are the SPI outputs & MUX bis.b #009h,&P2OUT ; Set CTRL_LE and MUX Control bic.b #006h,&P2OUT ; Clear the CTRL_CLK and the CTRL_DATA eint clr.w R10 clr.w R11 clr.w R12 clr.w R13 clr.w R14 clr.w R15 Configuring the Default Setting of the CDC7005 Using a MSP430 Microcontroller 11

12 4.2.2 Defining the Default Setting of the CDC7005 This segment of the code will be modified by every user. This segment of the code contains the actual words that create the default setting of the CDC7005. Each word programmed into the CDC7005 is 32 bits long. Since the CPU only has 16 bit registers, two registers must be used to hold the contents of one data Word. Therefore, the most significant 16 bits of Word 0 must be written into register 4. The least significant 16 bits of Word 0 are written into register 5. Currently, the example program will load the hexadecimal number 6FE401FC into the Word 0 internal register of the CDC7005. To modify the default setting of Word 0, the hexadecimal numbers that are loaded into R4 and R5 can be changed to fit any application. The tables showing the functions of Word 0, Word 1, and Word 2 can be found in Appendix B or in the CDC7005 data sheet. Word 1 and Word 2 are modified in the same way that Word 0 was modified. Register 6 and register 7 correspond to the most significant 16 bits and the least significant 16 bits of Word 1 respectively. In a similar fashion, register 8 and register 9 contain the most significant 16 bits and the least significant 16 bits of Word 2 respectively. These are the words that will be loaded into the CDC7005 on power-up and will generate the default setting of the device. ;Define the Default Setting of the CDC7005. Note that the two LSB's of each ;word will be masked to ensure the data is written into the correct location. mov.w #06FE4h,R4 mov.w #001FCh,R5 mov.w #05B44h,R6 mov.w #001FDh,R7 mov.w #00000h,R8 mov.w #0005Ah,R9 ; Word 0 MSB ; Word 0 LSB ; Word 1 MSB ; Word 1 LSB ; Word 2 MSB ; Word 2 LSB Verify that the 2 LSBs of Each Word Are Correct The two least significant bits of each word determines which CDC7005 internal register the data being transmitted from the MSP430 is loaded into. To ensure that this data is transferred to the correct internal register every time, the two LSBs of each word are cleared. They are then loaded with the correct values that correspond to each word. Word 0 requires a binary code of 00b on its two least significant bits. Word one requires 01b and Word 2 requires 10b. Using this simple step in the code, serious run-time errors are avoided. The data will always load into the correct word using the following code. There is no need to modify this code segment. ; ;Mask the LSBs of Registers R5, R7, and R9 bic.w #003h,R5 ; Clear 2 LSB's of Word 0 bic.w #003h,R7 ; Clear 2 LSB's of Word 1 bic.w #003h,R9 ; Clear 2 LSB's of Word 2 bis.w #001h,R7 ; Set Word 1 LSB's to 01b bis.w #002h,R9 ; Set Word 2 LSB's to 10b ;This should remain a permanent fixture in this program. It makes sure that the ;Data is loaded into the correct register. 12 Configuring the Default Setting of the CDC7005 Using a MSP430 Microcontroller

13 4.2.4 Write the Data to the CDC Main Data Writing Algorithim The data is now ready to be loaded into the CDC7005 via the integrated serial port interface. The MSP430 will write Word 0 first, Word 1 second, and Word 2 third. This programming sequence begins by moving the Word 0 register containing the most significant bits (Register 4) into the working register (Register 10). It then calls the Mainloop subroutine which writes the data to the serial port interface. When the Mainloop subroutine is complete, this segment of programming moves the Word 0 register, containing the 16 least significant bits, into the working register. The Mainloop subroutine is executed once again to write the least significant bits of data to the serial port interface. This procedure repeats for Word 1 and Word 2, thus writing all of the data to the serial port interface. When all of the data has been written, the software configures the output ports to disable any additional communication. Finally, the main data writing algorithm calls the final subroutine, Finished where all of the final device reconfigurations are performed. Once again, it is not necessary that changes are made to this segment of code. ;Write Word Zero MSB_Zero mov.w R4,R10 ;Copy Word 0, 16 MSB's to working Register bis.b #001h,&P2OUT ;Set The Write Bit to enable the next write call #Mainloop ;Go directly to the mainloop to transfer data LSB_Zero mov.w R5,R10 ;Copy Word 0, 16 LSB's to working Register call #Mainloop ;Go directly to the mainloop to transfer data ;Write Word One MSB_One mov.w R6,R10 ;Copy Word 1, 16 MSB's to working Register bis.b #001h,&P2OUT ;Set The Write Bit to enable the next write call #Mainloop ;Go directly to the mainloop to transfer data LSB_One mov.w R7,R10 ;Copy Word 1, 16 LSB's to working Register call #Mainloop ;Go directly to the mainloop to transfer data ;Write Word Two MSB_Two mov.w R8,R10 ;Copy Word 2, 16 MSB's to working Register bis.b #001h,&P2OUT ;Set The Write Bit to enable the next write call #Mainloop ;Go directly to the mainloop to transfer data LSB_Two mov.w R9,R10 ;Copy Word 2, 16 LSB's to working Register call #Mainloop ;Go directly to the mainloop to transfer data ;Terminate Writing Sequence EndWrite bis.b #001h,&P2OUT ;Disable Write bic.b #002h,&P2OUT ;Clear all Data bic.b #004h,&P2OUT ;Clear Clock Bits call #Finished ;Temporary Endless Loop that Toggles Pin 1.0 Configuring the Default Setting of the CDC7005 Using a MSP430 Microcontroller 13

14 Data Generation Subroutine (Mainloop) The Mainloop subroutine is the looping system that sends the data via the SPI to the CDC7005. It is a 16-cycle loop that shifts all of the bits out of the working register (R10) and writes them to the CTRL_DATA line of the SPI. This subroutine also pulses the CTRL_CLK bit to indicate to the CDC7005 that it needs to read the SPI Mainloop mov.w #0016d,R11 ;R11 is the 16 bit countdown Register RunLoop rla.w R10 ;Rotate 16 Bit Word Left jnc binzero ;If there is no carry, skip following ins bis.b #002h,&P2OUT ;If carry occurs set the data bit jmp binone ;Skip the Following as the value is one binzero bic.b #002h,&P2OUT ;Clear the Data Output Bit binone bic.b #001h,&P2OUT ;Enable CTRL_LE Bit WriteData bis.b #004h,&P2OUT ;Fire Clock Pulse bic.b #004h,&P2OUT ;clear clock pulse dec.w R11 ;Decrement 16 bit countdown register jnz RunLoop ret ;Return from Mainloop Subroutine Terminating the MSP430 Communication with the CDC7005 The final segment of code terminates the communication between the MSP430 and the CDC7005 and opens up a communication line between a peripheral device and the CDC7005. This is accomplished by clearing the MUX enable output port. After this output port is set to ground, the multiplexer blocks all communication between the MSP430 and the CDC7005. The multiplexer then permits communication between another peripheral device such as a PC serial port interface and the SPI. After the ports have been configured, the MSP430 is set to enter Low Power Mode 4. In this mode, all of the internal and external clock sources are stopped. The CPU is also shut down. This step is crucial to ensure that the MSP430 device does not contribute to clock jitter or phase noise of the clocking circuit. 14 Configuring the Default Setting of the CDC7005 Using a MSP430 Microcontroller

15 Finished bic.b #008h,&P2OUT ; Clear MUX Control. MSP No Longer Has CTRL bic.b #OFIE,&IE1 ; Disable osc fault interrupt bis.w #LPM4,SR ; Enter LPM 4 Finished2 nop jmp Finished Explaination of Additional Code Segments The Oscillator Fault Interrupt Service Routine (NMI_ISR) The remaining code segments located at the bottom of the program are also integral parts of the configuration of the MSP430. The first segment, entitled NMI_ISR is an interrupt service routine that is activated when the high-speed external crystal oscillator has generated a fault. Typically this interrupt service routine is activated on the very first CPU cycle because the external crystal oscillator has not stabilized. This segment is necessary to ensure that the microcontroller external clocking system is stable before any operations have been made. NMI_ISR; Only osc fault enabled, R15 used temporarily and not saved - bis.b #001h,&P1OUT ; P1.0= set CheckOsc bic.b #OFIFG,&IFG1 ; Clear OSC fault flag mov.w #0FFh,R15 ; R15= Delay CheckOsc1 dec.w R15 ; Additional delay to ensure start jnz CheckOsc1 ; bit.b #OFIFG,&IFG1 ; OSC fault flag set? jnz CheckOsc ; OSC Fault, clear flag again bic.b #001h,&P1OUT ; P1.0= reset bis.b #SELM_3,&BCSCTL2 ; MCLK = LFXT1 - now safe bis.b #OFIE,&IE1 ; re-enable osc fault interrupt reti The Interrupt Vector Table The final segment of code simply tells the CPU of the MSP430D1101 which interrupt service routines are being used. In this program the only interrupts being used are the reset vector and the oscillator fault vector. Configuring the Default Setting of the CDC7005 Using a MSP430 Microcontroller 15

16 ; Interrupt Vectors Used MSP430x11x1 ORG 0FFFEh ; MSP430 RESET Vector DW RESET ; ORG 0FFFCh ; NMI vector DW NMI_ISR END 4.3 The Hardware Interface Between The MSP430 and the CDC7005 The following section includes all of the material lists and schematics necessary to interface the MSP430 microcontroller and the CDC7005. This schematic requires the MSP430F1101A flash microcontroller to be programmed before it is soldered on to the PCB. 16 Configuring the Default Setting of the CDC7005 Using a MSP430 Microcontroller

17 4.3.1 Schematic REFERENCE_CLK VCXO_A VCXO_B Y3B Y3 Y2B Y2 Y1B Y1 Y0B Y0 F8 G8 H7 H6 H5 H4 H3 H2 G1 F1 U3 Y4B Y4 Y3B Y3 Y2B Y2 Y1B Y1 Y0B Y0 CTRL_LE CTRL_CLK CTRL_DATA VCXO_IN B VCXO_IN REF_IN CDC7005 A3 A2 A1 E1 D1 B1 R3 10k R9 10k R11 10k Y1 8MHz VCC 3.3V C3 10nF CTRL_DATA CTRL_CLK CTRL_LE Y4B Y4 R4 10k R5 10k VCC 3.3V R10 10k U1 1Y 2Y 3Y 4Y 1A 2A 3A 4A 1B 2B 3B 4B A/B OE SN74LVC257A MULTIPLEXER PERIPHERAL SERIAL DEVICE U2 VCC RST/NMI P2.5/ROSC P2.4/TA2 P2.1/INCLK P2.2/TA0 P2.0/ACLK P2.3/TA1 XOUT/TCLK XIN TST/VPP P1.7/TA2/TDO/TDI P1.6/TA1/TDI P1.5/TA0/TMS P1.4/SMCLK/TCK P1.3/TA2 P1.2/TA1 P1.1/TA0 P1.0/TACLK MSP430F1101A MICROCONTROLLER R1 100M C1 32pF C2 32pF R2 47k Figure 5. Hardware Interface Configuring the Default Setting of the CDC7005 Using a MSP430 Microcontroller 17

18 4.3.2 Materials List Part Name Description CDC v High Performance Clock Synthesizer and Jitter Cleaner MSP430F1101A Controls the address and data bus signals activity after completing the current bus cycle. 8 MHz Crystal External clock source for MSP430 Microcontroller 32pF Capacitor (2) Component of external MSP430 crystal 10nF Capacitor Component of the MSP430 external reset circuit 10kΩ Resistor (6) Pull-Up Resistors 47kΩ Resistor Component of the MSP430 external reset SN74LVC257A Quad 2-Input Multiplexer with 3-State Outputs References 1. MSP430C11x1, MSP430F11x1A Mixed Signal Microcontroller Data Sheet (SLAS214G) 2. CDC V High Performance Clock Synthesizer and Jitter Cleaner Data Sheet (SCAS685C) 3. MSP430x1xx Family User s Guide (SLAU049D) 4. SN74LVC257A Quad 2-Input Multiplexer With 3-State Outputs Data Sheet (SCCS019D) 18 Configuring the Default Setting of the CDC7005 Using a MSP430 Microcontroller

19 Appendix A. Full Version of Sample Code #include "msp430x11x1.h" ORG 0F000h ; Program Start RESET mov.w #0300h,SP ; Initialize 'x1121 stackpointer StopWDT mov.w #WDTPW+WDTHOLD,&WDTCTL ; Stop Watchdog Timer SetUpClk bis.b #XTS,&BCSCTL1 ; LFXT1 = HF XTAL bis.b #OFIE,&IE1 ; Enable osc fault interrupt SetupP2 bis.b #00Fh,&P2DIR ; Pin are the SPI outputs & MUX bis.b #009h,&P2OUT ; Set CTRL_LE and MUX Control bic.b #006h,&P2OUT ; Clear the CTRL_CLK and the CTRL_DATA eint clr.w R10 clr.w R11 clr.w R12 clr.w R13 clr.w R14 clr.w R15 ;Define the Default Setting of the CDC7005. Note that the two LSB's of each ;word will be masked to ensure the data is written into the correct location. mov.w #06FE4h,R4 ; Word 0 MSB mov.w #001FCh,R5 ; Word 0 LSB mov.w #05B44h,R6 ; Word 1 MSB mov.w #001FDh,R7 ; Word 1 LSB mov.w #00000h,R8 ; Word 2 MSB mov.w #0005Ah,R9 ; Word 2 LSB ; ;Mask the LSBs of Registers R5, R7, and R9 bic.w #003h,R5 ; Clear 2 LSB's of Word 0 bic.w #003h,R7 ; Clear 2 LSB's of Word 1 bic.w #003h,R9 ; Clear 2 LSB's of Word 2 bis.w #001h,R7 ; Set Word 1 LSB's to 01b bis.w #002h,R9 ; Set Word 2 LSB's to 10b ;This should remain a permanent fixture in this program. It makes sure that the ;Data is loaded into the correct register. ;Write Word Zero MSB_Zero mov.w R4,R10 ;Copy Word 0, 16 MSB's to working Register bis.b #001h,&P2OUT ;Set The Write Bit to enable the next write call #Mainloop ;Go directly to the mainloop to transfer data LSB_Zero mov.w R5,R10 ;Copy Word 0, 16 LSB's to working Register call #Mainloop ;Go directly to the mainloop to transfer data ;Write Word One MSB_One mov.w R6,R10 ;Copy Word 1, 16 MSB's to working Register bis.b #001h,&P2OUT ;Set The Write Bit to enable the next write call #Mainloop ;Go directly to the mainloop to transfer data LSB_One mov.w R7,R10 ;Copy Word 1, 16 LSB's to working Register call #Mainloop ;Go directly to the mainloop to transfer data ;Write Word Two MSB_Two mov.w R8,R10 ;Copy Word 2, 16 MSB's to working Register bis.b #001h,&P2OUT ;Set The Write Bit to enable the next write call #Mainloop ;Go directly to the mainloop to transfer data LSB_Two mov.w R9,R10 ;Copy Word 2, 16 LSB's to working Register call #Mainloop ;Go directly to the mainloop to transfer data Configuring the Default Setting of the CDC7005 Using a MSP430 Microcontroller 19

20 ;Terminate Writing Sequence EndWrite bis.b #001h,&P2OUT bic.b #002h,&P2OUT bic.b #004h,&P2OUT ;Disable Write ;Clear all Data ;Clear Clock Bits call #Finished ;Temporary Endless Loop that Toggles Pin Mainloop mov.w #0016d,R11 ;R11 is the 16 bit countdown Register RunLoop rla.w R10 ;Rotate 16 Bit Word Left jnc binzero ;If there is no carry, skip following instruction bis.b #002h,&P2OUT ;If carry occurs set the data bit jmp binone ;Skip the Following line since the value is one binzero bic.b #002h,&P2OUT ;Clear the Data Output Bit binone bic.b #001h,&P2OUT ;Enable CTRL_LE Bit WriteData bis.b #004h,&P2OUT ;Fire Clock Pulse bic.b #004h,&P2OUT ;clear clock pulse dec.w R11 ;Decrement 16 bit countdown register jnz RunLoop ret ;Return from Mainloop Subroutine Finished bic.b #008h,&P2OUT ; Clear MUX Control. MSP No Longer Has CTRL bic.b #OFIE,&IE1 ; Disable osc fault interrupt bis.w #LPM4,SR ; Enter LPM 4 Finished2 nop jmp Finished2 NMI_ISR; Only osc fault enabled, R15 used temporarly and not saved - bis.b #001h,&P1OUT ; P1.0= set CheckOsc bic.b #OFIFG,&IFG1 ; Clear OSC fault flag mov.w #0FFh,R15 ; R15= Delay CheckOsc1 dec.w R15 ; Additional delay to ensure start jnz CheckOsc1 ; bit.b #OFIFG,&IFG1 ; OSC fault flag set? jnz CheckOsc ; OSC Fault, clear flag again bic.b #001h,&P1OUT ; P1.0= reset bis.b #SELM_3,&BCSCTL2 ; MCLK = LFXT1 - now safe bis.b #OFIE,&IE1 ; re-enable osc fault interrupt reti ; Interrupt Vectors Used MSP430x11x1 ORG 0FFFEh ; MSP430 RESET Vector DW RESET ; ORG 0FFFCh ; NMI vector DW NMI_ISR END 20 Configuring the Default Setting of the CDC7005 Using a MSP430 Microcontroller

21 Appendix B. CDC7005 Internal Registers Table B-1. Word 0 Bit Bit Name Description / Function Type Power Up Condition Pin Affected 0 C0 Register Selection W 0 1 C1 Register Selection W 0 2 M0 Reference Divider M Bit 0 W 1 3 M1 Reference Divider M Bit 1 W 1 4 M2 Reference Divider M Bit 2 W 1 5 M3 Reference Divider M Bit 3 W 1 6 M4 Reference Divider M Bit 4 W 1 7 M5 Reference Divider M Bit 5 W 1 8 M6 Reference Divider M Bit 6 W 1 9 M7 Reference Divider M Bit 7 W 0 10 M8 Reference Divider M Bit 8 W 0 11 M9 Reference Divider M Bit 9 W 0 Reference Divider M 12 MD0 Reference Delay M Bit0 W 0 13 MD1 Reference Delay M Bit1 W 0 14 MD2 Reference Delay M Bit2 W 0 15 PFD0 PFD Pulse Width PFD Bit 0 W 0 A4 16 PFD1 PFD Pulse Width PFD Bit 1 W 0 A4 17 PFD2 PFD Pulse Width PFD Bit 2 W 0 A4 18 CP0 CP Current Setting Bit 0 W 1 A4 19 CP1 CP Current Setting Bit 1 W 0 A4 20 CP2 CP Current Setting Bit 2 W 0 A4 21 CP3 CP Current Setting Bit 3 W 1 A4 22 Y03St Y0 3-State W 1 F1, G1 23 Y13St Y1 3-State W 1 H2, H3 24 Y23St Y2 3-State W 1 H4, H5 25 Y33St Y3 3-State W 1 H6, H7 26 Y43St Y4 3-State W 1 G8, F8 27 CP3St CP 3-State W 1 A4 Ref. Delay M PFD Pulse Width CP Current Output 3-State 28 OP3St OPA 3-State & Disable W 0 A7 29 MUXS0 MUXSEL Select Bit 0 W 1 30 MUXS1 MUXSEL Select Bit 1 W 1 31 MUXS2 MUXSEL Select Bit 2 W 0 MUX SEL Configuring the Default Setting of the CDC7005 Using a MSP430 Microcontroller 21

22 Table B-2. Word1 Bit Bit Name Description / Function Type Power Up Condition Pin Affected 0 C0 Register Selection W 1 1 C1 Register Selection W 0 2 N0 VCXO Divider N Bit 0 W 1 3 N1 VCXO Divider N Bit 1 W 1 4 N2 VCXO Divider N Bit 2 W 1 5 N3 VCXO Divider N Bit 3 W 1 6 N4 VCXO Divider N Bit 4 W 1 7 N5 VCXO Divider N Bit 5 W 1 8 N6 VCXO Divider N Bit 6 W 1 9 N7 VCXO Divider N Bit 7 W 0 10 N8 VCXO Divider N Bit 8 W 0 11 N9 VCXO Divider N Bit 9 W 0 12 ND0 VCXO Delay N Bit0 W 0 13 ND1 VCXO Delay N Bit1 W 0 14 ND2 VCXO Delay N Bit2 W 0 15 MUX00 MUX0 Select Bit 0 W 0 F1, G1 16 MUX01 MUX0 Select Bit 1 W 0 F1, G1 17 MUX02 MUX0 Select Bit 2 W 0 F1, G1 18 MUX10 MUX1 Select Bit 0 W 1 H2, H3 19 MUX11 MUX1 Select Bit 1 W 0 H2, H3 20 MUX12 MUX1 Select Bit 2 W 0 H2, H3 21 MUX20 MUX2 Select Bit 0 W 0 H4, H5 22 MUX21 MUX2 Select Bit 1 W 1 H4, H5 23 MUX22 MUX2 Select Bit 2 W 0 H4, H5 24 MUX30 MUX3 Select Bit 0 W 1 H6, H7 25 MUX31 MUX3 Select Bit 1 W 1 H6, H7 26 MUX32 MUX3 Select Bit 2 W 0 H6, H7 27 MUX40 MUX4 Select Bit 0 W 1 G8, F8 28 MUX41 MUX4 Select Bit 1 W 1 G8, F8 29 MUX42 MUX4 Select Bit 2 W 0 G8, F8 Determines in which direction CP should 30 CP_DIR regulate, if REF_CLK is faster than VCXO_CLK and vice versa (see Figure W 1 A4 2) VCXO Divider N VCXO Delay N MUX 0 MUX 1 MUX 2 MUX 3 MUX 4 31 REXT Enable External Reference Resistor W 0 C1 22 Configuring the Default Setting of the CDC7005 Using a MSP430 Microcontroller

23 Table B-3. Word 2 Bit Bit Name Description / Function Type Power Up Condition 0 W 0 C0 Register Selection 1 C1 Register Selection W 1 2 HOLD Enables Hold Functionality, High Active W 0 A4 3 PD current Sources, reset the dividers W 1 NPD and 3-States all outputs 4 NRESET RESET all Dividers, Low Active W 1 5 ENBG Enable Bandgap (for test purpose) W 1 C1 6 LOCKW 0 Lock detect window bit 0 W 0 A8 7 LOCKW 1 Lock detect window bit 1 W 0 A8 8 RES RESERVED W X 9 RES RESERVED W X 10 RES RESERVED W X 11 RES RESERVED W X 12 RES RESERVED W X 13 RES RESERVED W X 14 RES RESERVED W X 15 RES RESERVED W X 16 RES RESERVED W X 17 RES RESERVED W X 18 RES RESERVED W X 19 RES RESERVED W X 20 RES RESERVED W X 21 RES RESERVED W X 22 RES RESERVED W X 23 RES RESERVED W X 24 RES RESERVED W X 25 RES RESERVED W X 26 RES RESERVED W X 27 RES RESERVED W X 28 RES RESERVED W X 29 RES RESERVED W X 30 RES RESERVED W X 31 RES RESERVED W X Pin Affected Configuring the Default Setting of the CDC7005 Using a MSP430 Microcontroller 23

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