MB86R12 Emerald-P. Delta Sheet Differences between ES2 and ES3. Fujitsu Semiconductor Europe GmbH

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1 Delta Sheet Differences between ES2 and ES3 Fujitsu Semiconductor Europe GmbH Rev0-01 June 20, 2012 Revised Jun. 20, 2012 dl-mb86r12-emerald-p-es2-es3-rev0-01

2 1.1 History Revision Date Author Description A. von Treuberg First release NOTE This document does not include errata corrections. Please refer to the Customer Information document on the Emerald-P website for these: (click on Support ). 2 dl-mb86r12-emerald-p-es2-es3-rev0-01 Revised Jun. 20, 2012

3 Fujitsu Semiconductor Europe GmbH Differences between Emerald-P ES2 and ES3 1.1 CHIPID CINFO Register CINFO (Chip INFOrmation) Register contains the product number and version information of the LSI. Address 3d10_0000(h) Bit Name Product number 1st_CODE[7:0] 2nd_CODE[7:0] R/W R R Initial 86(h) 52(h) Bit Name Product number VER[3:0] 3rd_CODE[11:0] R/W R R Initial 12F(h) ES2:2(h) ES3:3(h) Bit Field Explanation No Name 3-0 VER[3:0] This bitfield contains the device version information of the chip. The current version is the third edition. 2: ES2 3: ES rd_CODE[11:0] This bit is the 3rd_CODE information of the product number (MB86R12). 3rd_CODE = 0x nd_CODE[7:0] This bitfield contains the second part of the product number (MB86R12) after the 'MB'. 2nd_CODE = 0x52 (ASCII code of 'R') st_CODE[7:0] This bitfield contains the first part of the product number (MB86R12) after the 'MB'. 1st_CODE = 0x86. Product number Revised Jun. 20, 2012 dl-mb86r12-emerald-p-es2-es3-rev0-01 3

4 1.2 Serial Flash Boot When the ES3 boots from a Serial flash memory device via HS_SPI, it issues a reset command (FFh). ES2 does not issue this reset command. Background Information On a cold reset, the embedded application in internal BootROM sets Emerald-P s High-Speed SPI (HS-SPI) Flash Interface to Normal Read mode. Most SPI flash memories are set to Normal Read mode on a cold reset therefore there are no communication problems. At runtime, the Emerald-P embedded application may switch to Quad I/O High Performance Read mode. However, on a hot reset of Emerald-P, its HS-SPI Flash Interface is set back to Normal Read mode again - but the external flash memory remains in Quad I/O High Performance Read mode and the Emerald-P BootROM does not unlock this state, meaning that communication is not possible anymore. Change in ES3: The revised boot ROM solution depends on the external flash memory in use: Spansion S25FL129P: is reset to Normal Read mode when it receives 0xFF for 8 cycles. The latest Emerald-P boot program in the ROM issues this sequence, therefore the solution is in place. Winbond W25Q16BV: is reset when it receives 0xFF for 8 cycles when in Continuous Read Mode during Quad I/O operation, but 0xFFFF for 16 cycles when in Continuous Read Mode during Dual I/O operation. If you are not using Dual I/O operation mode, then the solution is in place. Do not use this device s Dual I/O operation mode with Emerald-P. NOTE A globally valid setup can not be implemented in Emerald-P. The system designer must ensure that the specific flash memory in use is returned to Normal Read mode on a hot reset of Emerald-P. SPI flash devices that support Spansion s Mode Reset Bit (MBR) instruction (two are listed above) can be used with Emerald-P (i.e. this has been validated). Please only use external SPI flash memories that either interpret the 8 cycles of 0xFF correctly (i.e. as an operation mode reset) or that ignore the instructions with no side-effects. 1.3 DDR Controller The ES3 allows the use of the self-refresh function for both DDR2 and DDR3 memory devices when the CRG is in STOP mode. 4 dl-mb86r12-emerald-p-es2-es3-rev0-01 Revised Jun. 20, 2012

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