Solid State Drives Moving into Design

Transcription

1 Solid State rives Moving into esign Y.R. Kim irector, Technical Marketing SMSUG Semiconductor Inc. ugust

2 10GHz System Performance Bottleneck Performance gap between RM & Storage is 4X greater than between CPU & RM Speed/Throughputs 1GHz 100MHz 10MHz 1985: 386, 16MHz 1982: 286, 6MHz CPU RM H 1989: 486, 25MHz 1993: P, 66MHz (52MB/s) 1985: FP, 13MHz 2003: P4, 3GHz 2010: Future, : P4, 1.5GHz 2007: R (12.8GB/s) (8.5GB/s) 2004: R : PIII, 500MHz (4.2GB/s) 1997: PII, 300MHz 2001: R266 * Measure values are average (2.1GB/s) and not max/peak 1997: SR, 133MHz (1GB/s) Max. value 1994: SR, 66MHz (528MB/s) 1993: EO, 33MHz (132MB/s) 1996: T2 (5/16 MB/s) 1998: T4 (10/33 MB/s) 2002: T6 (30/100 MB/s) 2005: P4, 3.8GHz 2000: T5 (20/66 MB/s) 2008: ST6G (100/600 MB/s) 2005: ST3G (50/300 MB/s) 2003: ST I.5G (40/150 MB/s) Source: Samsung ugust x1 x4

3 Other Existing System Hurdles? Booting time System power budget/mobility/battery life Mechanical failures of H o spindle motor o moving parts otepc Failure Report from Vendor (465 E) Source: anonymous PC OEM *F 34% Handling 1% rive 65% Memory(10%) ssembly(5%) Head 35% Elec. Stress(5%) Shock and Handling (45%) Mechanical problems 80% *F : ot efine Failure ugust

4 Why Flash Better than H? 1.8 SS 1.8 H 64GB/32GB/16GB/8GB ensity 40GB/60GB/80GB ~ $500 (32GB) Cost < $150 (80GB) 54 x 71 x 3 (mm) imension 54 x 78.5 x 8.2 (mm) 1/5x 13 g Weight 61 g 2.6x R: 53MB/s, W: 32MB/s Sequential ccess R/W: 22 ~ 48MB/s 11x R: 53MB/s, W: 13MB/s Random ccess R/W: 1 ~ 5MB/s 1/3 ctive: 0.5W Power (ctive) 1.5 W 20x 20G (10~2000Hz) Operating Vibration 1.0G (22~500Hz) 3.3x MTBF: > 2M hours (TB) Endurance MTBF: < 300K hours ugust

5 SS Wins Reliability Power Consumption Performance ugust

6 Reliability Factors Understanding of Flash endurance ECC/EC Wear-leveling Lifetime estimation worst case scenario ugust

7 Control Gate Cell Operation of Flash Erase Operation 0V 60nm Cell Program Operation 18V Floating Gate + + 0V + 0V + P-Well 20V umber of Cells Erase Operation creates negative Vt Program Operation creates positive Vt 1 0 ugust V 1.2V 3.0V 7 V th

8 Program & Erase (P/E) Cycling PGM PGM + + P-sub Before Cycle, Programmed Cell PGM + + P-sub fter Cycle, Programmed Cell PGM + + P-sub + + P-sub ugust 2007 Erased Cell 8 Erased Cell

9 Inherent Endurance Characteristics Memory Cell Vth vs. Endurance Vth [V] 3 2 Programed Cell Erased Cell Program gets faster Erase gets slower 1E+00 1E+01 1E+02 1E+03 1E+04 1E+05 1E+06 Erase failure 100K 500K - Usually erase failure first occurs over 100K P/E cycles, resulting in an invalid block without any data loss - The number of invalid blocks only gradually increases after 100K ugust

10 Read Retention Issue HTS Effect Why phenomenon occurs PGM PGM + + P-sub + + P-sub Before Cycle, Programmed Cell fter Cycle, Programmed Cell HTS (Hot Temperature Stress) PGM PGM P-sub P-sub ugust 2007 fter Bake, Programmed Cell fter Cycle+Bake, Programmed Cell 10

11 Erase/Program Verification on SS Bad Block etection during SS Operation Write or Merge Operation ew Block llocation Erase Erase Verify Program/Copying ata Program Verify Write/Merge Completion Bad Block Marking ugust

12 Failure Modes of Flash Failure Mode Condition Solution Implication Run-time write failure Read failure Erase/program fail status 1 bit error Block replacement ECC-correction o data error; Bad blocks increase o data error; o bad block increase Max. 2% of invalid blocks guaranteed up to 100K endurance Invalid blocks might be more than 2% after 100K endurance 2-bit failure rate irrelevant to write performance, only related to read - Failures too low to be observed; can only be calculated - Single bit error rate/512b(sfr): < 0.01 Cycle (60nm ) - Failure rate = (SFR) 2 x (# of sectors / chip [4Gb]) = 1 x x * 64 chips = 0.07 PPM - ST-2 has high error resilience due to 6-bit ECC per sector (512B) ugust

13 Wear-Leveling ata wear-leveling Wear-leveling on data blocks Meta wear-leveling Wear-leveling on TL context blocks (map blocks) Erase count Each physical block has its own erase count. (Static wear-leveling) FTL format makes block erase count zero Wear-level threshold value Triggering value for wear-level operation Configurable at compilation time If threshold value becomes smaller, wear-leveling happens more frequently Too frequent wear-leveling may cause performance to drop Group-based, vertical ordered block mapping Full scanning too expensive to use to find blocks with minimum erase count First round: find the minimum block within each group Second round: find the minimum within each group s minimum Vertical ordered block mapping required to avoid excessive dependence upon a specific group ugust

14 Wear Leveling (Group-based) Wear-level trigger condition WL_threshold < (min_ec in free_blks) - (min_ec in data_blks) Log blocks llocate min_ec block from free block pool Free blocks ata Queues Check diff min & pseudo_min (pseudo_min = real_min + 1) min Free Block Queues (Sorted Queue) Triggering wear-level WER-LEVEL Swap free & data block min min_ec (minimum erase count) block ata blocks!"#$%&'(')*+,-.!"#$%0'(')*+,-. ugust

15 SS s Lifetime Estimation ssuming xgb/day usage scenario, can estimate life expectancy MobileMark usage scenario: 4.8GB/day - Workload: 4.8GB write during one day - ssuming 16GB, SS lifetime estimated 1 P/E Cycle : 16GB/4.8GB = 3.34 ays 100K P/E Cycles : 3.34 x 100K = 913 Years year year year 1000 year 100 year 10 year 1 year Mobile Mark TM Usage Scenario [4.8GB/day] 0B/day 10MB/day 100MB/day 1GB/day 10GB/day 100GB/day 1TB/day ugust

16 Lifetime Estimation (Worst Case) Usage scenario - 1MB-sized hot spot area (LBs) & remains are pre-stored - Continuous hot spot updating - Full 64KB sequential writing speed ssumption: 100% running 24h X 7d Workload : 25 MB/sec 32GB SS lifetime - 1 P/E Cycle : 32GB/25MB/s = 22 Min - 100K P/E Cycles : 22Min x 100K = 4.2 Years LB 0 Total ensity : 30.5GB Pre-stored : GB Real endurance measurement - Sample size : 32GB 10 E Hot spot size : 1MB 1M P/E Cycle 2M P/E Cycle 3M P/E Cycle Test Result Pass Pass Pass ugust

17 SS Wins Reliability Power Consumption Performance ugust

18 Power Comparison -Read H 1 Sector Read (2.5 H) IO bound 100m/iv. SS 1 Sector Read (SMSUG 4GB SS) CPU bound 100m/iv. ugust

19 Power Consumption - Write SS Write Start 50m/iv. SS Write End 125mS utomatically fall into Standby Mode after Operation 50m/iv. ugust

20 SS Wins Reliability Power Consumption Performance ugust

21 SMSUG PT/ST-I SS rchitecture - Implements optimized buffering architecture using SRM (64KB) - Concurrent operation of 16 chips (4-channel/4-way interleaving) - 4 Parallel HW ECC (RS-2 bit) RM7 x32 RM IF SRM CTRL x16 ECC M x16 FIFO x16 Flash Controller X16 (Bus ) PT IF UM 33Mhz: 66MB/s x32 SRM SRM x16 66Mhz: 266MB/s ECC M 33Mhz: 133MB/s x16 FIFO x16 Flash Controller X16 (Bus B) ugust

22 SMSUG ST-II SS rchitecture - SLC/MLC support - Independent 4-channel, 4-way interleaving (CRC supports data integrity) - 6-bit ECC per sector (for SLC& MLC; can support MLC) - 16MB RM buffer (w/ CRC) & dedicated HW indexing engine Search Engine SRM (128KB) RM7 (120MHz) HB PB HOST ST (1.5/3G) Buffer Control 32 M Controller 8 Flash Controller 32 M Controller 8 Flash Controller SRM(16MB) (166MHz, x32) M Controller 8 Flash Controller M Controller 8 Flash Controller ugust

23 How to improve Performance? 15MB/s with a single 50nm 8Gb SLC in two plane mode Using multi-plane, multi-way/channel interleaving, read/write throughput increase possible! Up to now, 2-lane/4-way/4-channel interleaving supported page size: Channel: 2KB 1ch 4KB 1ch 4KB 2ch 4KB 4ch MB/s tprog: 200us / twc: 25ns 100MB/s MB/s MB/s 40MB/s 20MB/s plane plane & cache plane ugust 2007 interleave interleave plane 2-way plane 2-way 1~4 channel

24 Performance on Windows Vista Window Express Index* Primary hard disk score Test Environment 1.8 SS 5.2 System: Sony VIO type G CPU: Core Solo U1400(1.2 GHz), 1.8 H 3.4 OS: Windows Vista Business SS: 32GB, H: 60GB * Window Express Index: Standard tool for performance diagnosis in Window Vista OS Booting Time 1.8 SS Window front page shows up 50sec ll task trays ready 1min 30sec 1.8 H 1min 40sec 3 min (Source : Itmedia.co.jp) ugust

25 pplication Launching Time crobat Launching Time Comparison (PT/ST-I SS) evice Windows XP Location of files crobat PF file crobat launching time SS Flash Flash Flash 3.2s (4.4x) H-H or Robson H H Flash Flash Flash H 5.0s (2.8x) 7.5s (1.8x) H H H H 14.0s (1.0x) pplication: crobat Professional 6.0 ata: JungUmGlobal Manual_Ko.pdf (21.9MB) System: Pentium GHz, 512MB PT/ST-I SS 32GB, PT H 80GB ugust

26 Fast pplication Launch HH (7) SS (3) H(14) ugust

27 SS Future irection ugust

28 Fast BIOS Required for SS General Software developed Fast BIOS for H-H ugust

29 Windows Vista TM Optimization More sequential read command - Command: 60%, Size: 80% - Over last 15 years, OS optimized to be H-friendly Increased CPU operation time not related to isk I/O 10 sec - Boot time decreases 10 seconds, even though SS actually reduces disk service time by 20 seconds - I/O bound with H, while CPU bound with SS - More OS optimization required to attain SSs maximum performance benefits Boot time Size Time Size Write Time Total disk time 210 MB s 7.19 MB 1.18 s s 20 sec 295 MB 7.06 s 5.98 MB 0.93 s 7.99 s ugust Rea d H 34 s SS 24 s

30 SS to bridge the gap between system memory and H Performance boosting by using multiple chips SS as a primary storage system Overall System performance improvements Less power consumption (battery life and energy savings) Resistant to shock and vibration High MTBF Smaller form factor TCO benefits Robust wear leveling for long life expectancy Intelligent algorithm of Samsung proprietary wear-leveling OS optimization for SS Conclusions Cooperation with OS vendors to maximize benefits of Samsung SS ugust